TWI897283B - Optoelectronic semiconductor device - Google Patents

Abstract

An optoelectronic semiconductor device includes a substrate, a first type semiconductor structure, a second type semiconductor structure located on the first type semiconductor structure, an active structure located between the first type semiconductor structure and the second type semiconductor structure, an insulating layer located between the first type semiconductor structure and the substrate, and a contact structure located between the first type semiconductor structure and the substrate. The first type semiconductor structure includes a convex with a first thickness and a concave with a second thickness. The second thickness is between 0.01 μm to 1 μm.

Description

Optoelectronic semiconductor devices

The present invention relates to a semiconductor device, and more particularly to a photovoltaic semiconductor device.

Semiconductor devices include compound semiconductors composed of Group III-V elements, such as gallium phosphide (GaP), gallium arsenide (GaAs), or gallium nitride (GaN). Semiconductor devices can be power devices or optoelectronic semiconductor devices (such as light-emitting diodes (LEDs), laser diodes, photodetectors, and solar cells). An LED consists of a p-type semiconductor layer, an n-type semiconductor layer, and an active structure positioned between the p-type and n-type semiconductor layers. Under the action of an external electric field, electrons and holes provided by the n-type and p-type semiconductor layers, respectively, recombine in the active structure, converting electrical energy into light energy. Improving the photoelectric conversion efficiency of optoelectronic semiconductor devices is a key research priority for researchers.

This disclosure provides an optoelectronic semiconductor device comprising a substrate, a first-type semiconductor structure, a second-type semiconductor structure located on the first-type semiconductor structure, an active structure located on the first-type semiconductor structure and between the second-type semiconductor structure, an insulating layer located between the first-type semiconductor structure and the substrate, and a contact structure located between the first-type semiconductor structure and the substrate. The first-type semiconductor structure has a convex portion and a concave portion, each having a first thickness and a second thickness, respectively. The second thickness is between 0.01 μm and 1 μm.

In order to make the above-mentioned purposes, features, and advantages of the present disclosure more clearly understood, the following is a detailed description of preferred embodiments with reference to the accompanying drawings:

Figure 1 is a partial cross-sectional schematic diagram of an optoelectronic semiconductor device 100 according to an embodiment of the present disclosure. Optoelectronic semiconductor device 100 includes a semiconductor stack 1, a first contact structure 2 disposed below semiconductor stack 1, and a top electrode 3 disposed above semiconductor stack 1. Optoelectronic semiconductor device 100 may optionally include a substrate 4 and a reflective structure 5. Reflective structure 5 is disposed between substrate 4 and semiconductor stack 1 to reflect light generated by semiconductor stack 1 toward top electrode 3, thereby increasing light emission efficiency.

The semiconductor stack 1 can have a PN structure or a PIN structure. In one embodiment, the semiconductor stack 1 includes a first-type semiconductor structure 11, an active structure 12 disposed on the first-type semiconductor structure 11, and a second-type semiconductor structure 13 disposed on the active structure 12. In other words, the active structure 12 and the second-type semiconductor structure 13 are sequentially disposed on the first-type semiconductor structure 11 along a stacking direction (i.e., the Y direction in the figure, which may be substantially perpendicular to the X direction). In one embodiment, the optoelectronic semiconductor device 100 is a light-emitting device, the semiconductor stack 1 is a light-emitting stack, and the first-type semiconductor structure 11 and the second-type semiconductor structure 13 are, for example, cladding layers and/or confinement layers, and have an energy gap greater than that of the active structure 12, thereby increasing the probability of electrons and holes combining in the active structure 12 to emit light. Depending on its material, the active structure 12 can emit light with a peak wavelength between 200 nm and 1800 nm. For example, it can emit infrared light with a peak wavelength between 700 nm and 1700 nm, red light with a peak wavelength between 610 nm and 700 nm, yellow light with a peak wavelength between 530 nm and 570 nm, green light with a peak wavelength between 490 nm and 550 nm, blue light or deep blue light with a peak wavelength between 400 nm and 490 nm, or ultraviolet light with a peak wavelength between 250 nm and 400 nm. In this embodiment, the active structure 12 emits red light with a peak wavelength between 610 nm and 700 nm.

The first-type semiconductor structure 11 and the second-type semiconductor structure 13 can be single-layer or multi-layer and have different first and second conductivities, respectively, to provide holes and electrons, or electrons and holes, respectively. In one embodiment, the first-type semiconductor structure 11 and the second-type semiconductor structure 13 can optionally include a Bragg reflector (DBR). The semiconductor stack 1 can include a single heterostructure or a double heterostructure. The active structure 12 can include multiple quantum wells. The materials of the first-type semiconductor structure 11, the second-type semiconductor structure 13, and the active structure 12 are Group III/V compound semiconductors, such as GaAs, InGaAs, AlGaAs, AlInGaAs, GaP, InGaP, AlInP, AlGaInP, GaN, InGaN, AlGaN, AlInGaN, AlAsSb, InGaAsP, InGaAsN, AlGaAsP, etc. In the embodiments of the present invention, unless otherwise specified, the chemical expressions include "stoichiometric compounds" and "non-stoichiometric compounds." A "stoichiometric compound" is, for example, one in which the total elemental dosage of the Group III elements is the same as the total elemental dosage of the Group V elements. Conversely, a "non-stoichiometric compound" is, for example, one in which the total elemental dosage of the Group III elements is different from the total elemental dosage of the Group V elements. For example, the chemical formula AlGaAs represents the inclusion of Group III elements aluminum (Al) and gallium (Ga), and Group V element arsenic (As). The total elemental dosage of the Group III elements (Al and Ga) may be the same as or different from the total elemental dosage of the Group V element (As). In addition, if the compounds represented by the chemical formulas are compounds that meet the chemical dosage requirements, AlGaAs represents _{Alx1Ga1 -x1As} , wherein the aluminum content x may meet the requirement of 0＜x1＜1; AlInP represents _{Alx2In1 -x2P} , wherein the aluminum content x may meet the requirement of 0＜x2＜1; AlGaInP represents ( _{Aly1Ga1 -y1} ) _{1- x3Inx3P} , wherein 0＜x3＜1, 0＜y1＜1; AlGaN represents _{Alx4Ga1 -x4N} , wherein the aluminum content x4 may meet the requirement of 0＜x4＜1; AlAsSb represents _{AlAsx5Sb1 -x5} , wherein 0＜x5＜1; InGaP represents _{Inx6Ga1 -x6P} , wherein 0＜x6＜1; InGaAsP represents _{Inx7Ga1 -x7As (1-y2) Py2} , where 0＜x7＜1, 0＜y2＜1; InGaAsN represents In _x8 Ga _1-x8 As _1-y3 N _y3 , where 0＜x8＜1, 0＜y3＜1; AlGaAsP represents Al _x9 Ga _1-x9 As _1-y4 P _y4 , where the aluminum content x may meet 0＜x9＜1, 0＜y4＜1; InGaAs represents In _x10 Ga _1-x10 As, where 0＜x10＜1.

As shown in FIG. 1 , a recess 116 is formed in the first-type semiconductor structure 11, so that the first-type semiconductor structure 11 includes a first protrusion 111, a second protrusion 112, and a recess 113. The first protrusion 111 has a first thickness T1, and the recess 113 has a second thickness T2 that is less than the first thickness T1. In this embodiment, the second protrusion 112 has a thickness substantially equal to that of the first protrusion 111. The first thickness T1 is the shortest distance between a lower surface S of the active structure 12 and a first bottom surface S1 of the first protrusion 111. The second thickness T2 is the shortest distance between the lower bottom surface S and a second bottom surface S2 of the recess 113. Both the first bottom surface S1 and the second bottom surface S2 are spaced apart from the second-type semiconductor structure 13. When the active structure 12 has multiple layers, the lower surface S is the lower surface of the layer closest to the first-type semiconductor structure 11. In this embodiment, the first thickness T1 is 0.5 μm to 2 μm, the second thickness T2 is 0.01 μm to 1 μm, and the ratio of the first thickness T1 to the second thickness T2 is 2 to 20. The semiconductor stack 1 has a maximum thickness defined as a third thickness T3. Specifically, the third thickness T3 is the distance from the first bottom surface S1 to the top electrode 3. In this embodiment, the third thickness T3 is 4.5 μm to 6.5 μm.

The second protrusion 112 has a third bottom surface S3 that is remote from the second-type semiconductor structure 13. The first protrusion 111 has a first side surface S4 connected to the first bottom surface S1, and the second protrusion 112 has a second side surface S5 connected to the second bottom surface S2 and the third bottom surface S3. The first side surface S4, the second side surface S5, and the second bottom surface S2 collectively define a groove 116, and the first side surface S4 faces the second side surface S5. The first side surface S4 is not perpendicular to the first bottom surface S1, and the second side surface S5 is also not perpendicular to the third bottom surface S3. Specifically, the first side surface S4 and the first bottom surface S1 have a first angle θ1 between 100° and 165°, and the second side surface S5 and the third bottom surface S3 have a second angle θ2 between 100° and 165°. The reflective structure 5 is disposed below the first protrusion 111, the second protrusion 112, and the recess 113 of the first-type semiconductor structure 11. The first bottom surface S1, the second bottom surface S2, the third bottom surface S3, the first side surface S4, and the second side surface S5 are all covered by the reflective structure 5. Therefore, when light emitted from the active structure 12 travels toward the reflective structure 5, it is reflected by the reflective structure 5 and emitted toward the top electrode 3 from the optoelectronic semiconductor device 100. Specifically, when light emitted from the active structure 12 travels toward the reflective structure 5, it is directed toward the light-emitting surface 141 at different angles by the side surfaces S4, S5 and the bottom surfaces S1, S2, and S3. This reduces the probability of total internal reflection at the light-emitting surface 141, thereby increasing the light extraction efficiency of the optoelectronic semiconductor device 100.

Because the first side surface S4 and/or the second side surface S5 are not perpendicular to the second bottom surface S2, the groove 116 has a gradually varying width. For example, in this embodiment, the width of the groove 116 gradually increases in a direction away from the second-type semiconductor layer 13. Alternatively, in another embodiment, the width of the groove 116 gradually decreases in a direction away from the second-type semiconductor layer 13. The maximum width of the groove 116 is defined as the first width W1. Furthermore, the groove 116 has a height H (H = T1 - T2). In this embodiment, the height H is 0.5 μm to 1.5 μm, so that the first side surface S4 and the second side surface S5 have a specific range, thereby reflecting light from the first side surface S4 and the second side surface S5. The first width W1 and the height H have a ratio (W1/H) greater than 3 and less than 8, for example, 3, 3.5, 4, 5, 6, or 7.

As shown in FIG. 1 , semiconductor stack 1 optionally includes a window layer 14 disposed on second-type semiconductor structure 13. Window layer 14 is transparent to light generated by active structure 12. For example, the energy gap of window layer 14 is greater than that of active structure 12. Furthermore, window layer 14 can increase the light extraction efficiency and/or current distribution uniformity of optoelectronic semiconductor device 100. The thickness of window layer 14 is greater than 1500 nm and less than 4000 nm, for example, 1500 nm, 2000 nm, 2500 nm, 3000 nm, 3500 nm, or 4000 nm. In one embodiment, the window layer 14 has a doping concentration greater than 110 ¹⁷ /cm ³ and less than 110 ¹⁹ /cm ³ , for example, 110 ¹⁷ /cm ³ , 510 ¹⁷ /cm ³ , 110 ¹⁸ /cm ³ , or 510 ¹⁸ /cm ^3. The window layer 14 includes a light-emitting surface 141. Light generated by the active structure 12 is emitted from the optoelectronic semiconductor device 100 through the light-emitting surface 141. The light-emitting surface 141 can be a rough surface to reduce the probability of total internal reflection and scatter light emitted by the semiconductor stack 1, thereby improving the light extraction efficiency of the optoelectronic semiconductor device 100.

The semiconductor stack 1 optionally includes a second contact structure 15 on the window layer 14. The second contact structure 15 is disposed on a portion of the light-emitting surface 141, while the second contact structure 15 is not disposed on another portion of the light-emitting surface 141. The second contact structure 15 is disposed between the second-type semiconductor layer 14 and the top electrode 3. In this embodiment, a low resistance exists between the second contact structure 15 and the window layer 14. For example, the resistance between the second contact structure 15 and the window layer 14 is less than the resistance between the top electrode 3 and the window layer 14. In this embodiment, the top electrode 3 covers the second contact structure 15. In other words, when viewed from a cross-section, the top electrode 3 has a third width W3 that is greater than the width of the second contact structure 15. The window layer 14 and the second contact structure 15 are made of III-V compound semiconductors, such as GaAs, InGaAs, AlGaAs, AlInGaAs, GaP, InGaP, AlInP, AlGaInP, GaN, InGaN, AlGaN, AlInGaN, AlAsSb, InGaAsP, InGaAsN, and AlGaAsP.

The first contact structure 2 is disposed below the first-type semiconductor structure 11. The first contact structure 2 includes a plurality of separate contact portions 21 located below the second protrusion 112. In this embodiment, no contact portions 21 are disposed below the first protrusion 111 and the recess 113 (i.e., the contact portions 21 are located only below the second protrusion 112). Consequently, most of the current flows through the contact portions 21 below the second protrusion 112 to the reflective structure 5. Specifically, the first contact structure 2 and the third bottom surface S3 of the second protrusion 112 are in contact with each other to form an electrical connection. The material of the first contact structure 2 can be a metal, an alloy, or a semiconductor. Examples of metals include gold (Au), silver (Ag), germanium (Ge), or benzene (Be). Alloys are alloys containing the above metals. Semiconductors are Group III-V semiconductor compounds, such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), and gallium phosphide (GaP).

When the material of the first contact structure 2 is a Group III-V semiconductor compound, the first contact structure 2 may optionally contain an N-type dopant or a P-type dopant, with the dopant concentration being between 110 ¹⁸ /cm ³ and 110 ²⁰ /cm ³ . In another embodiment, the dopant concentration in each contact portion 21 increases from closer to the first semiconductor structure 11 toward farther away from the first semiconductor structure 11. In this embodiment, as viewed from a cross-section of the optoelectronic semiconductor device 100, the plurality of contact portions 21 each have a second width W2, and the third bottom surface S3 has a fifth width W5. When the first contact structure 2 is made of a semiconductor, the sum of the second widths W2 accounts for a percentage of the fifth width W5 ranging from 5% to 50%. In another embodiment, when the first contact structure 2 is made of a metal or alloy, the sum of the second widths W2 accounts for a percentage of the fifth width W5 ranging from 1% to 20%. Furthermore, the plurality of contact portions 21 may have the same shape and/or size, such as all being circular, triangular, or irregular. In other embodiments, the plurality of contact portions 21 may have different shapes and/or sizes, but the present disclosure is not limited thereto.

Continuing with Figures 1 and 2, a portion of the upper electrode 3 corresponds to the first protrusion 111. Specifically, a portion of the upper electrode 3 overlaps with the first protrusion 111 in the vertical direction (i.e., the Y-axis direction in the figure). In this embodiment, the projection of the upper electrode 3 toward the first protrusion 111 is completely within the range of the first protrusion 111, and the first side surface S4 does not overlap with the upper electrode 3 in the vertical direction. The upper electrode 3 has a third width W3, and the first bottom surface S1 of the first protrusion 111 has a fourth width W4 that is greater than the third width W3, and the third bottom surface S3 of the second protrusion 112 has a fifth width W5 that is greater than the fourth width W4. A first distance D1 is defined between the top electrode 3 and the second protrusion 112. A second distance D2 is defined between the top electrode 3 and one of its plurality of contacts 21 (i.e., the contacts closest to the top electrode 3), which is greater than the first distance D1. The second distance D2 is greater than 3 μm and less than 20 μm, such as 5 μm, 8 μm, 10 μm, 12 μm, or 15 μm. This allows current to be transmitted to locations farther from the top electrode 3 and reduces the probability of light emitted by the active structure 12 being reflected and then blocked by the top electrode 3. In one embodiment, the difference (D2-D1) between the second distance D2 and the first distance D1 is less than 20 μm and greater than 2 μm, for example, 15 μm, 10 μm, 8 μm, 5 μm, or 3 μm. This allows light emitted from the active structure 12 to be reflected by the second side surface S5 and effectively emitted toward the light-emitting surface 141, thereby increasing the light extraction efficiency of the optoelectronic semiconductor device 100. In one embodiment, when the second distance D2 and the difference (D2-D1) meet the above description, the optoelectronic semiconductor device 100 can simultaneously achieve the aforementioned advantages, thereby increasing the light extraction efficiency.

In one embodiment, the second distance D2 is greater than the third thickness T3 of the semiconductor stack 1, and the ratio (D2/T3) is greater than 5 and less than 20, for example, 5, 6, 7, 8, 9, 10, 12, 14, 16, 18, or 20, to prevent light emitted from the active structure 12 from being blocked by the top electrode 3 and thus reducing the light emission efficiency. Similarly, when the ratio (D2/T3) and the difference (D2-D1) meet the above description, the optoelectronic semiconductor device 100 can simultaneously achieve the above advantages and thereby increase the light extraction efficiency. The first distance D1 is the horizontal distance from the intersection of the third bottom surface S3 and the second side surface S5 to the edge of the upper electrode 3 (i.e., along the X-axis direction of the drawing), and the second distance D2 is the horizontal distance from the edge of the upper electrode 3 to the edge of the nearest contact portion 21.

Figure 2 is a top view schematically illustrating an optoelectronic semiconductor device 100 according to an embodiment of the present disclosure. Dashed lines indicate structures not directly observable from the top view. The top electrode 3 of the optoelectronic semiconductor device 100 includes at least one electrode pad 31, a plurality of first extended electrodes 32, and a plurality of second extended electrodes 33. The plurality of first contact structures 2 are offset from the electrode pad 31, the plurality of first extended electrodes 32, and the plurality of second extended electrodes 33, respectively. In this embodiment, the first extended electrode 32 is connected to the electrode pad 31, and the second extended electrode 33 is connected to the first extended electrode 32. The width of the first extended electrode 32 is greater than the width of the second extended electrode 33 to facilitate current distribution in the optoelectronic semiconductor device 100. In this embodiment, the first extended electrode 32 is perpendicular to the second extended electrode 33, but the top electrode 3 of the optoelectronic semiconductor device 100 of the present invention is not limited to this arrangement.

The structure of the cross-section taken along line A-A' in Figure 2 is a cross-sectional view of the portion of optoelectronic semiconductor device 100 shown in Figure 1. The third width W3 of the top electrode 3 in Figure 1 refers to the width of the second extended electrode 33. However, this is merely an example of one embodiment. In another embodiment, the top electrode 3 in Figure 1 may be an electrode pad 31, and the top electrode may optionally not include any extended electrodes. Therefore, the third width W3 of the top electrode 3 may also be the width of the electrode pad 31.

The substrate 4 can be used to support the semiconductor stack 1 and other layers or structures located thereon. The semiconductor stack 1 can be grown on the substrate 4 or another growth substrate (not shown) through an epitaxial method such as metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydrogenation vapor phase epitaxy (HVPE). If the semiconductor stack 1 is grown on the growth substrate, the semiconductor stack 1 can be bonded to the substrate 4 using substrate transfer technology and the growth substrate can be selectively removed. In one embodiment, the semiconductor stack 1 is grown on the growth substrate and then bonded to the substrate 4 through a conductive adhesive layer 6 using substrate transfer technology. Specifically, substrate 4 can be transparent, translucent, or opaque to light emitted by active structure 12, and can be conductive, semiconducting, or insulating. In this embodiment, optoelectronic semiconductor device 100 is a vertical type, and therefore, substrate 4 is a conductive material, including a metal material, a metal alloy material, a metal oxide material, a semiconductor material, or a carbon-containing material. The metal material includes copper (Cu), aluminum (Al), chromium (Cr), tin (Sn), gold (Au), nickel (Ni), titanium (Ti), platinum (Pt), lead (Pb), zinc (Zn), cadmium (Cd), antimony (Sb), molybdenum (Mo), tungsten (W) or cobalt (Co); the metal alloy material is an alloy containing the above metal materials; the metal oxide material may include but is not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium oxide (Ga ₂ O ₃ ), lithium gallate (LiGaO ₂ ), lithium aluminate (LiAlO ₂ ), or magnesium aluminate (MgAl ₂ O ₄ ); semiconductor materials may include, but are not limited to, Group IV semiconductors or Group III-V semiconductors, such as silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), gallium phosphide (GaP), gallium arsenide (GaAs), gallium arsenide phosphide (AsGaP), zinc selenide (ZnSe), zinc selenide (ZnSe), or indium phosphide (InP); carbon-containing materials may include, but are not limited to, diamond-like carbon (DLC) or graphene.

The reflective structure 5 includes a first insulating layer 51 and a first conductive oxide layer 52 disposed beneath and covering the first insulating layer 51. The first insulating layer 51 conformally covers the first protrusion 111, the recess 113, and the second protrusion 112. In this embodiment, the first insulating layer 51 contacts the first bottom surface S1, the second bottom surface S2, the third bottom surface S3, the first side surface S4, and the second side surface S5. In this embodiment, the first insulating layer 51 includes a plurality of openings 511 to expose the plurality of contact portions 21, with each opening 511 exposing a respective contact portion 21. The first insulating layer 51 physically contacts the sides of the plurality of contact portions 21. Each of the plurality of contact portions 21 has a thickness greater than that of the first insulating layer 51, such that the plurality of contact portions 21 protrude beyond the first insulating layer 51. In this embodiment, the thickness of the plurality of contact portions 21 is 0.05 μm to 0.5 μm, for example, 0.08 μm, 0.12 μm, 0.15 μm, 0.18 μm, 0.2 μm, 0.22 μm, 0.25 μm, 0.28 μm, 0.3 μm, 0.4 μm, or 0.5 μm. In one embodiment, each of the plurality of contact portions 21 has a thickness less than that of the first insulating layer 51. The thickness of the plurality of contacts 21 can be designed based on the peak wavelength of the optoelectronic semiconductor device 100. For example, when the optoelectronic semiconductor device 100 is exposed to red light with a peak wavelength between 610 nm and 700 nm, the thickness of the contacts 21 is 0.2 μm to 0.4 μm. When the optoelectronic semiconductor device 100 is exposed to infrared light with a peak wavelength between 700 nm and 1700 nm, the thickness of the contacts 21 is 0.05 μm to 0.08 μm.

In this embodiment, the reflective structure 5 may further include a second conductive oxide layer 53 covering the first conductive oxide layer 52. The material of the second conductive oxide layer 53 is different from that of the first conductive oxide layer 52. Specifically, in this embodiment, the material of the first conductive oxide layer 52 is indium tin oxide, and the material of the second conductive oxide layer 52 is indium zinc oxide. The second conductive oxide layer 53 and the first conductive oxide layer 52 have different thicknesses. For example, in one embodiment, the thickness of the first conductive oxide layer 52 is much smaller than the thickness of the second conductive oxide layer 53. In another embodiment, the first conductive oxide layer 52 is discontinuously distributed below the first-type semiconductor structure 11.

The first conductive oxide layer 52 conformally covers the first insulating layer 51 and the plurality of contacts 21 exposed by the plurality of openings 511. The first conductive oxide layer 52 and the plurality of contacts 21 are in contact with each other. More specifically, each contact 21 has a surface S6 remote from the first-type semiconductor structure 11 and a sidewall S7 connected to the surface S6. The first conductive oxide layer 52 covers the surface S6 and/or a portion of the sidewall S7 of the contact 21. In another embodiment, the reflective structure 5 optionally does not include the first conductive oxide layer 52, and the second conductive oxide layer 53 covers the first insulating layer 51 and conformally covers the first protrusion 111, the recess 113 and the second protrusion 112, and the second conductive oxide layer 53 covers the surface S6 and/or part of the sidewall S7 of the contact portion 21.

The reflective structure 5 further includes a metal layer 54 located below and covering the second conductive oxide layer 53. The metal layer 54 has a first plane 541 away from the upper electrode 3. The first plane 541 is a flat surface, that is, the distance from the first plane 541 to the first bottom surface S1 is smaller than the distance from the first plane 541 to the second bottom surface S2.

The optoelectronic semiconductor device 100 disclosed herein further includes a lower electrode 7 disposed below the substrate 4, and an upper electrode 3 and a lower electrode 7 disposed on opposite sides of the semiconductor stack 1, respectively, to form a vertical optoelectronic semiconductor device 100. The materials of the upper electrode 3 and the lower electrode 7 may include metal materials or metal alloy materials. For example, the metal materials may include, but are not limited to, aluminum (Al), chromium (Cr), copper (Cu), tin (Sn), gold (Au), nickel (Ni), titanium (Ti), platinum (Pt), lead (Pb), zinc (Zn), cadmium (Cd), antimony (Sb), or cobalt (Co). The metal alloy materials include alloys of combinations of the above metals. In addition, the optoelectronic semiconductor device 100 may optionally include a protective layer 8 covering the light-emitting surface 141 to prevent external moisture or pollutants from entering the semiconductor stack 1 and changing the optoelectronic properties of the optoelectronic semiconductor device 100. For subsequent electrical connections, the protective layer 8 may selectively expose the electrode pad 31 and/or the extended electrodes 32 and 33.

The material of the first insulating layer 51 includes a non-conductive material. The non-conductive material includes an organic material or an inorganic material. Organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cycloolefin copolymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, or fluorocarbon polymer. Inorganic materials include silicone or glass, aluminum oxide ( _Al2O3 ), silicon nitride ( _SiNx ), silicon oxide ( _SiOx ), _titanium oxide ( _TiOx ), or magnesium fluoride ( _MgFx ). In one embodiment, the first insulating layer 51 includes one or more layers (e.g., a Bragg reflector (DBR) structure formed by alternately stacking two sublayers, such as a SiO _x sublayer, a TiO _x sublayer, or a MgF ₂ sublayer).

The first conductive oxide layer 52 and the second conductive oxide layer 53 are transparent to the light emitted by the semiconductor stack 1, and their materials may include metal oxide materials, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), magnesium oxide (MgO), or indium zinc oxide (IZO).

The material of the metal layer 54 may include, but is not limited to, metal materials or metal alloy materials, such as copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), and tungsten (W); the metal alloy material is an alloy containing the above materials.

The conductive bonding layer 6 may be made of a conductive material, such as a metal oxide material, a semiconductor material, a metal material, a metal alloy material, or a carbon-containing material. For example, metal oxide materials may include, but are not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), and gallium and aluminum codoped zinc oxide (GAZO). Semiconductor materials may include, but are not limited to, gallium phosphide (GaP). Metal materials may include, but are not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), indium (In), platinum (Pt), or tungsten (W). Metal alloy materials are alloys containing the aforementioned metal materials. Carbon-containing materials may include, but are not limited to, graphene. The conductive adhesive layer 6 connects the substrate 4 to the reflective structure 5 and may include multiple subordinate layers (not shown).

Figures 3 and 4 are schematic bottom views of a step in manufacturing the optoelectronic semiconductor device 100 of Figure 1. When manufacturing the optoelectronic semiconductor device 100, a semiconductor stack and a first contact structure 2 are first formed in sequence on a growth substrate (not shown). As shown in Figure 3, the first contact structure 2 includes a plurality of contact groups 22 separated from each other (such as the structure within the rectangular dotted line in Figure 3), and each contact group 22 includes a plurality of contact portions 21 separated from each other. A walkway P is provided between two adjacent contact groups 22, corresponding to the location where the second extended electrode 33 is to be formed, and the width Wp of the walkway P is greater than the third width W3 of the upper electrode 3. Any two of the plurality of contact groups 22 can have the same or different numbers and arrangements of contact portions 21. In this embodiment, the plurality of contact portions 21 are formed in a two-dimensional arrangement on the semiconductor stack, and the plurality of contact groups 22 are parallel to each other. The first contact structure 2 can be formed by yellow light development and etching.

Following the step in FIG. 3 , as shown in FIG. 4 , a plurality of grooves 116 can be formed in the first-type semiconductor structure 11 by dry etching or wet etching, thereby defining a plurality of protrusions 114 and a plurality of recesses 113 (also see FIG. 1 ). Each recess 113 is located between two adjacent protrusions 114 and corresponds to the position of a groove 116 . The plurality of protrusions 114 include a first protrusion 111, a second protrusion 112, two third protrusions 117, and two fourth protrusions 118. One of the plurality of recesses 113 is located between the first protrusion 111 and the second protrusion 112, with the first protrusion 111 corresponding to the position where the walkway P is formed. The second protrusion 112 is offset from the walkway P. From a top view, the semiconductor stack 1 has a first side 1a, a second side 1b opposite the first side 1a, a third side 1c connecting the first and second sides 1a and 1b, and a fourth side 1d opposite the third side 1c. Two third protrusions 117 are located near the first and second sides 1a and 1b, and the first extended electrodes 32 are subsequently formed on the two third protrusions 117. Two fourth protrusions 118 are located near the third and fourth sides 1c and 1d, and are parallel to the first and second protrusions 111 and 112. The two third protrusions 117 are perpendicular to the two fourth protrusions 118. The third protrusions 117 are connected to the first and fourth protrusions 111 and 118.

In this embodiment, when viewed from above, some of the plurality of recesses 113 may be closed (e.g., in the shape of a square), while others may be open (e.g., in the shape of a square or a straight line). When a recess 113 is closed, it surrounds the second protrusion 112. The two third protrusions 117 and the two fourth protrusions 118 surround the plurality of recesses 113, the first protrusion 111, and the second protrusion 112.

Referring to Figures 1 and 4 , the first protrusion 111 has a fourth width W4, and the third bottom surface S3 of the second protrusion 112 has a fifth width W5 that is greater than the fourth width W4. Preferably, the ratio of the fifth width W5 to the fourth width W4 is greater than 2 and less than 15, for example, 2.5, 3, 3.25, 3.5, 3.75, 4, 4.5, 5, 7, 9, 11, 13, or 15. Each third protrusion 117 has a sixth width W6 (along the Z-axis of the drawing) between the fourth width W4 and the fifth width W5. Each fourth protrusion 118 has a seventh width W7 (along the X-axis of the drawing). In this embodiment, the seventh width W7 is not equal to the sixth width W6. For example, the seventh width W7 is between the sixth width W6 and the fourth width W4. In other embodiments, the seventh width W7 is equal to the sixth width W6. The plurality of recesses 113 have a first total surface area (i.e., the sum of the areas of the second bottom surfaces S2 of the recesses). The first-type semiconductor structure 11 has a surface facing the lower surface S of the active structure 12, and this surface has a surface area. The first total surface area accounts for 15% to 40% of the total surface area, for example, 15%, 20%, 25%, 30%, 35%, or 40%. The plurality of protrusions 114 have a second total surface area (i.e., the sum of the areas of the bottom surfaces of the protrusions, for example, the area of the first bottom surface S1 + the area of the third bottom surface S3 + ...). The plurality of contacts 21 have a third total surface area, accounting for 15% to 30% of the second total surface area, for example, 15%, 18%, 21%, 24%, 27%, or 30%. In the embodiment shown in FIG. 1 , the first total surface area accounts for 18.6% of the surface area, and the third total surface area accounts for 17.2% of the second total surface area.

Next, as shown in Figures 1 and 4 , a first insulating layer 51 having a plurality of openings 511 is formed. The plurality of openings 511 are located on the second protrusion 112 and expose a plurality of contact portions 21, respectively. The width of each opening 511 is approximately equal to the width of each contact portion 21. Because the width of each opening 511 is approximately equal to the width of each contact portion 21, the first conductive oxide layer 52 covers the contact portions 21 and the first insulating layer 51 but does not directly cover the first-type semiconductor structure 11 (i.e., the first conductive oxide layer 52 does not physically contact the third bottom surface S3).

Following the steps in Figure 4 , a first conductive oxide layer 52, a second conductive oxide layer 53, and a metal layer 54 are sequentially formed on the first insulating layer 51. The substrate 4 and the metal layer 54 are bonded together via a conductive adhesive layer 6. The growth substrate is then removed, and a lower electrode 7 is formed on the substrate 4, and an upper electrode 3 is formed on the window layer 14, completing the fabrication of the optoelectronic semiconductor device 100 shown in Figure 1 .

FIG5 is a partial cross-sectional schematic diagram of another embodiment of the present disclosure. The optoelectronic semiconductor device 200 of this embodiment has substantially the same components and component connections as the optoelectronic semiconductor device 100 shown in FIG1 , except that the distribution of the first insulating layer 51 is different from that of the aforementioned optoelectronic semiconductor device 100. Specifically, the first insulating layer 51 conformally covers the first protrusion 111, the recess 113, and a portion of the second protrusion 112, and has an opening 511 to expose the plurality of contacts 21 below the second protrusion 112 and the first-type semiconductor structure 11 between the plurality of contacts 21. Furthermore, the first insulating layer 51 and the plurality of contacts 21 are separated from each other and do not physically contact each other. The first conductive oxide layer 52 conformally covers the first insulating layer 51, the plurality of contacts 21, and the third bottom surface S3 of the second protrusion 112. The first conductive oxide layer 52 fills the space between the contact 21 and the opening 511, and between the plurality of contacts 21, allowing the first conductive oxide layer 52 to physically contact the third bottom surface S3 of the second protrusion 112. Alternatively, in an embodiment without the first conductive oxide layer 52, the second conductive oxide layer 53 fills the space between the contact 21 and the opening 511, and between the plurality of contacts 21, allowing the second conductive oxide layer 53 to physically contact the third bottom surface S3.

FIG6 is a partial cross-sectional schematic diagram of a photovoltaic device 300 according to another embodiment of the present disclosure. The photovoltaic device 300 of this embodiment substantially shares the same components and component connections as the photovoltaic device 100 shown in FIG1 , with the difference being that the reflective structure 5 of the photovoltaic device 300 of this embodiment further includes a second insulating layer 55 disposed between the first insulating layer 51 and the first conductive oxide layer 52. The first insulating layer 51 and the second insulating layer 55 help enhance the coverage of the first protrusion 111 and the recess 113. For example, when the first insulating layer 51 does not provide sufficient coverage over the first side surface S4 and the second side surface S5, the second insulating layer 55 can cover the side surfaces S4 and S5, allowing light emitted from the active structure 12 to be reflected at the interface between the side surfaces S4 and S5 and the reflective structure 5, thereby increasing light extraction efficiency. The material of the second insulating layer 55 can refer to the material of the first insulating layer 51. The material of the second insulating layer 55 can be the same as or different from the material of the first insulating layer 51. In one embodiment, the refractive index of the first insulating layer 51 is less than the refractive index of the second insulating layer 55. The refractive index of the first insulating layer 51 is between 1 and 1.5, while the refractive index of the second insulating layer 55 is between 1.4 and 2.2. For example, the material of the first insulating layer 51 is magnesium fluoride ( _MgF2 ), and the material of the second insulating layer 55 is silicon dioxide ( _SiO2 ). The second insulating layer 55 includes a second opening 551 that is larger than the opening 511 of the first insulating layer 51. The second insulating layer 55 is separated from the plurality of contact portions 21 and does not physically contact them.

Furthermore, as shown in FIG6 , the thickness of the second conductive oxide layer 53 below the recess 113 (i.e., along the Y-axis of the drawing) is greater than the height H of the recess 116. In other words, the second conductive oxide layer 53 has a second plane 531 that is distal from the top electrode 3. The second plane 531 is a flat surface, meaning that the distance from the second plane 531 to the first bottom surface S1 is shorter than the distance from the second plane 531 to the second bottom surface S2. The second conductive oxide layer 53 is connected to the metal layer 54 via the second plane 531, thereby improving the yield of the subsequent process for forming the metal layer 54.

Figures 7A and 7B are schematic top views of portions of an optoelectronic semiconductor device according to another embodiment of the present disclosure. For clarity, Figures 7A and 7B illustrate the relative relationships of some structures. However, some structures are not directly visible from top views, either with the naked eye or under a microscope. The components and interconnections of optoelectronic semiconductor device 400 in Figure 7A are similar to those of optoelectronic semiconductor device 100 shown in Figure 1 , differing in the distribution of first protrusion 111, second protrusion 112, and recess 113, as well as the shape of opening 511. In this embodiment, the first-type semiconductor structure 11 has a plurality of mutually separated second protrusions 112, and the recess 113 surrounds the plurality of second protrusions 112. Furthermore, the first insulating layer 51 has a plurality of openings. Unlike the optoelectronic semiconductor device 100, where each opening 511 exposes a single contact 21, each opening 511 in this embodiment exposes multiple contacts 21 simultaneously. The openings 511 and the second protrusions 112 are pentagonal in shape. Furthermore, the first total surface area of this embodiment accounts for 38.9% of the total surface area, and the third total surface area accounts for 22.3% of the second total surface area.

The components and connections between components of the optoelectronic semiconductor device 500 of FIG. 7B are similar to those of the optoelectronic semiconductor device 400 shown in FIG. 7A , with the difference being the distribution of the first protrusions 111, the second protrusions 112, and the recesses 113, as well as the shape of the openings 511, which differ from that shown in FIG. 7A . In this embodiment, the first-type semiconductor structure 11 includes a plurality of second protrusions 112 of different and separate shapes, such as triangular and rhombus-shaped, and the recesses 113 surround the plurality of second protrusions 112. Furthermore, the first insulating layer 51 has a plurality of openings 511, each of which simultaneously exposes a plurality of contacts 21. The plurality of openings 511 and the second protrusions 112 are triangular or rhombus-shaped. Furthermore, the first total surface area accounts for 32.7% of the surface area, and the third total surface area accounts for 25.8% of the second total surface area.

Please refer to Table 1, which is a comparison table of the luminous brightness of the experimental examples and comparative examples of the present disclosure. Experimental Example 1 is the optoelectronic semiconductor device 100 of Figure 1 above, Experimental Example 2 is the optoelectronic semiconductor device 400 of Figure 7A above, Experimental Example 3 is the optoelectronic semiconductor device 500 of Figure 7B above, and the comparative example is mainly a optoelectronic semiconductor device of a first type semiconductor structure that does not have multiple protrusions and multiple recesses. In other words, the first type semiconductor structure of the comparative example does not have grooves, and the surface of the first type semiconductor structure away from the upper electrode is a plane. As can be seen from Table 1, Experimental Examples 1 to 3 of the optoelectronic semiconductor device of the present disclosure all have higher luminous intensity than the optoelectronic semiconductor device of the comparative example. Furthermore, compared to the comparative example, the brightness of the photovoltaic semiconductor devices in Experimental Examples 1 to 3 increased by 1.53% to 5.7%. The brightness increase ratio is calculated as follows: for example, if the luminous intensity of the photovoltaic semiconductor device in the comparative example is P0 and the luminous intensity of the photovoltaic semiconductor device in Experimental Example 1 is P1, the brightness increase ratio of Experimental Example 1 is [(P1-P0)/P0] = 100%.

FIG8 is a schematic diagram of a packaging structure of a photoelectric semiconductor device according to an embodiment of the present disclosure. The packaging structure 900 includes a photoelectric semiconductor device 100, a packaging substrate 91, a carrier 93, bonding wires 95, a contact structure 96, and a packaging material 98. The packaging substrate 91 may include a ceramic or glass material. The packaging substrate 91 has a plurality of through holes 92. The through holes 92 may be filled with a conductive material such as metal to facilitate electrical conduction and/or heat dissipation. The carrier 93 is located on the surface of one side of the packaging substrate 91 and also includes a conductive material such as metal. The contact structure 96 is located on the surface of the other side of the packaging substrate 91. In this embodiment, the contact structure 96 includes contact pads 96a and 96b, and the contact pads 96a and 96b can be electrically connected to the carrier 93 via the through hole 92. In one embodiment, the contact structure 96 can further include a thermal pad (not shown), for example, located between the contact pads 96a and 96b. The optoelectronic semiconductor device 100 is located on the carrier 93 and can be the optoelectronic semiconductor device described in any embodiment of the present disclosure. In this embodiment, the carrier 93 includes a first portion 93a and a second portion 93b. The optoelectronic semiconductor device 100 is electrically connected to the second portion 93b of the carrier 93 via a bonding wire 95. The material of the bonding wire 95 may include a metal, such as gold, silver, copper, aluminum, or an alloy containing at least one of the aforementioned elements. The encapsulation material 98 covers the optoelectronic semiconductor device 100 and has the effect of protecting the optoelectronic semiconductor device 100. Specifically, the encapsulation material 98 may include a resin material such as epoxy or silicone. The encapsulation material 98 may further include a plurality of wavelength conversion particles (not shown) to convert the first light emitted by the optoelectronic semiconductor device 100 into a second light. The wavelength of the second light is greater than that of the first light. In other embodiments, the optoelectronic semiconductor device 100 in the package structure 900 may be the optoelectronic semiconductor device 200, 300, 400, or 500. Alternatively, in some embodiments, the package structure 900 includes multiple optoelectronic semiconductor devices 100, 200, 300, 400, and/or 500, and these multiple optoelectronic semiconductor devices 100, 200, 300, 400, and/or 500 may be connected in series, in parallel, or in series and parallel. The optoelectronic semiconductor devices 100, 200, 300, 400, 500 or the package structure 900 may be applied to lighting devices, backlight devices, automotive lighting devices, display modules, and/or plant lighting devices, among other applications.

In summary, although the present invention has been disclosed above through the use of exemplary embodiments, these are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and enhancements are possible without departing from the spirit and scope of the present invention. Therefore, the scope of protection for the present invention shall be determined by the appended patent application.

100, 200, 300, 400, 500: Optoelectronic semiconductor device 1: Semiconductor stack 11: First type semiconductor structure 111: First protrusion 112: Second protrusion 113: Recess 114: Protrusion 116: Recess 117: Third protrusion 118: Fourth protrusion 1a: First side 1b: Second side 1c: Third side 1d: Fourth side 12: Active structure 13: Type II semiconductor structure 14: Window layer 141: Light-emitting surface 15: Second contact structure 2: First contact structure 21: Contact portion 3: Top electrode 31: Electrode pad 32: First extended electrode 33: Second extended electrode 4: Substrate 5: Reflective structure 51: First insulating layer 511: Opening 52: First conductive oxide layer 53: Second conductive oxide layer 531: Second plane 5 4: Metal layer 541: First plane 55: Second insulating layer 6: Conductive adhesive layer 7: Lower electrode 8: Protective layer 900: Package structure 91: Package substrate 92: Through hole 93: Carrier 93a: First section 93b: Second section 95: Bonding wire 96: Contact structure 96a, 96b: Contact pads 98: Package material T1: First thickness T2: Second thickness T3 : Third thickness S: Bottom surface S1: First bottom surface S2: Second bottom surface S3: Third bottom surface S4: First side surface S5: Second side surface S6: Surface S7: Sidewall H: Height θ1: First angle θ2: Second angle W1: First width W2: Second width W3: Third width W4: Fourth width W5: Fifth width D1: First distance D2: Second distance

FIG1 is a partial cross-sectional view of a photovoltaic semiconductor device according to an embodiment.

FIG2 is a top view schematically showing a photovoltaic semiconductor device according to an embodiment.

3 and 4 are bottom views of a structure completed in steps of a process flow for fabricating an optoelectronic semiconductor device according to one embodiment.

FIG5 is a partial cross-sectional view of a photovoltaic semiconductor device according to an embodiment.

FIG6 is a partial cross-sectional view of a photovoltaic semiconductor device according to an embodiment.

FIG7A is a partial top view schematically showing an optoelectronic semiconductor device according to one embodiment.

FIG7B is a partial top view schematically showing an optoelectronic semiconductor device according to one embodiment.

Table 1 is a comparison table of the luminous brightness of the experimental examples and comparative examples of this disclosure.

FIG8 is a schematic diagram showing a package structure of a photoelectric semiconductor device according to an embodiment.

100: Optoelectronic semiconductor devices

1: Semiconductor stacking

11: Type I semiconductor structure

111: First convex part

112:Second convex part

113: concave part

116: Groove

12: Active structure

13: Type II semiconductor structure

14: Window level

141:Light-emitting surface

15: Second contact structure

2: First contact structure

21: Contact area

3: Upper electrode

33: Second extension electrode

4:Substrate

5: Reflective structure

51: First insulating layer

511: Opening

52: First oxide conductive layer

53: Second oxide conductive layer

54: Metal layer

541: First Plane

6: Conductive adhesive layer

7: Lower electrode

8: Protective layer

T1: First thickness

T2: Second thickness

T3: Third thickness

S: Lower surface

S1: First bottom surface

S2: Second bottom surface

S3: Third bottom surface

S4: First side surface

S5: Second side surface

S6: Surface

S7: Sidewall

H: Height

θ1: First angle

θ2: Second angle

W1: First Width

W2: Second Width

W3: Third Width

W4: Fourth Width

W5: Fifth Width

D1: First Distance

D2: Second distance

Claims (10)

A photoelectric semiconductor device comprises: a conductive substrate; a first-type semiconductor structure having a first side facing the conductive substrate and a protrusion and a recess formed on the first side, the protrusion and the recess having a first thickness and a second thickness, respectively; a second-type semiconductor structure located on the first-type semiconductor structure; an active structure located between the first-type semiconductor structure and the second-type semiconductor structure; an insulating layer located between the first-type semiconductor structure and the conductive substrate; a first contact structure located between the first-type semiconductor structure and the conductive substrate; and a lower electrode located on a side of the conductive substrate remote from the first-type semiconductor structure and directly contacting the conductive substrate; The second thickness is between 0.01 μm and 1 μm, and the thickness of the conductive substrate is greater than the thickness of the bottom electrode. The optoelectronic semiconductor device as described in claim 1, wherein the protrusion has a first bottom surface, the recess has a second bottom surface, and the distance between the first bottom surface and the second bottom surface in a vertical direction is between 0.5 μm and 1.5 μm. The optoelectronic semiconductor device as described in claim 1 further includes an upper electrode located on the second-type semiconductor structure, and the upper electrode does not overlap with the first contact structure in a vertical direction. The optoelectronic semiconductor device as described in claim 3 further includes a second contact structure disposed between the second-type semiconductor structure and the upper electrode. The optoelectronic semiconductor device of claim 1, wherein a thickness of the first contact structure is smaller than a thickness of the insulating layer. The optoelectronic semiconductor device of claim 1, wherein the insulating layer has an opening corresponding to the first contact structure. The optoelectronic semiconductor device as described in claim 6 further includes an oxide conductive layer located between the first contact structure and the conductive substrate, and the oxide conductive layer fills the opening. The optoelectronic semiconductor device of claim 7, wherein the protrusion has a first bottom surface, and the oxidized conductive layer has a first side, and the first side is not perpendicular to the first bottom surface. The optoelectronic semiconductor device as claimed in claim 7 further comprises an adhesive layer located between the oxide conductive layer and the conductive substrate. The optoelectronic semiconductor device of claim 1, wherein the insulating layer further comprises a Bragg reflector.