TWI895021B - Three-dimensional memory device - Google Patents

Abstract

Provided is a three-dimensional (3D) memory device including: a dielectric substrate, a stack structure, and a protective layer. The stack structure is disposed on the dielectric substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The protective layer covers a top surface, a first side wall and a bottom surface of the uppermost conductive layer among the plurality of conductive layers. A material of the protective layer includes silicon nitride.

Description

Three-dimensional memory device

The present invention relates to a semiconductor device, and in particular to a three-dimensional memory device.

Non-volatile memory (such as flash memory) has the advantage of maintaining the data stored even after power failure. Therefore, it has become a widely used type of memory in personal computers and other electronic devices.

Currently, the most commonly used 3D flash memories in the industry include NOR flash memory and NAND flash memory. Another type of 3D flash memory is AND flash memory, which can be used in multi-dimensional flash memory arrays and offers high density, high area utilization, and fast operation speeds. Therefore, the development of 3D flash memory has gradually become a trend.

The present invention provides a three-dimensional memory device that utilizes a protective structure to surround the surface and sidewalls of the top conductor layer to avoid bridging problems and thereby improve the reliability of the device.

The present invention provides a three-dimensional memory device comprising a dielectric substrate, a stacked structure, and a protective layer. The stacked structure is disposed on the dielectric substrate and comprises a plurality of alternating dielectric layers and a plurality of conductive layers. The protective layer continuously covers the top surface, first sidewall, and bottom surface of the topmost conductive layer among the plurality of conductive layers. The protective layer is made of silicon nitride.

In one embodiment of the present invention, the three-dimensional memory device further includes a buffer layer that continuously covers the top surface, first sidewall, and bottom surface of the plurality of conductive layers except the uppermost conductive layer.

In one embodiment of the present invention, the buffer layer is disposed on a portion of the top surface and a portion of the bottom surface of the uppermost conductive layer and is connected to the protective layer.

In one embodiment of the present invention, the three-dimensional memory device further includes a vertical channel pillar. The vertical channel pillar penetrates the stacked structure and is adjacent to the first sidewall of the uppermost conductive layer, and the protective layer contacts the vertical channel pillar.

In one embodiment of the present invention, the vertical channel pillar includes a first source/drain pillar, a second source/drain pillar, a dielectric material, a channel layer, and a charge storage structure. The first source/drain pillar and the second source/drain pillar extend through the stacked structure and into the dielectric substrate. The dielectric material is disposed between the first source/drain pillar and the second source/drain pillar to separate the first source/drain pillar from the second source/drain pillar. The channel layer surrounds the dielectric material, the first source/drain pillar, and the second source/drain pillar, and the channel layer contacts the first source/drain pillar and the second source/drain pillar. The charge storage structure surrounds the channel layer.

In one embodiment of the present invention, at least one of the first source/drain pillar and the second source/drain pillar is in contact with the protective layer.

In one embodiment of the present invention, the uppermost conductive layer is used as a dummy word line.

In one embodiment of the present invention, the three-dimensional memory device includes a three-dimensional AND flash memory, a three-dimensional NAND flash memory, a three-dimensional NOR flash memory, or a combination thereof.

In one embodiment of the present invention, the thickness of the protective layer is between 10Å and 100Å.

In one embodiment of the present invention, the thickness of the buffer layer is smaller than the thickness of the protective layer.

Based on the above, the present invention utilizes an additional high-dielectric protective layer to cover the surface and sidewalls of the topmost conductive layer, effectively preventing bridging between the source/drain pillars (or conductive plugs) and the word lines, thereby improving the reliability of the 3D memory device. Furthermore, the steps for forming the protective structure of the present invention are compatible with existing 3D memory device manufacturing processes, making it applicable to a variety of 3D memory devices.

The present invention will be more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in a variety of forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are exaggerated for clarity. Identical or similar element numbers represent identical or similar elements, and will not be detailed in the following paragraphs.

It should be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or intervening elements may be present. When an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected" can refer to physical and/or electrical connections, and "electrically connected" or "coupled" can mean the presence of other elements between two elements. As used herein, "electrically connected" can include physical connections (e.g., wired connections) and physical disconnections (e.g., wireless connections).

As used herein, "about," "approximately," or "substantially" includes the stated value and the average within an acceptable range of deviation from the specified value that can be determined by one of ordinary skill in the art, taking into account the measurement in question and the specific amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, or ±5%. Furthermore, as used herein, "about," "approximately," or "substantially" can be used to select a more acceptable range of deviation or standard deviation depending on the optical property, etching property, or other property, and may not apply to all properties without using a single standard deviation.

The terms used herein are for describing exemplary embodiments only and are not intended to limit the present disclosure. In this context, unless otherwise indicated in the context, the singular includes the plural.

FIG1 is a schematic cross-sectional view of a three-dimensional memory device according to an embodiment of the present invention.

Referring to FIG. 1 , a three-dimensional memory device according to an embodiment of the present invention may include a dielectric substrate 100, a stop layer 102, a stacked structure 110, a capping layer 116, and vertical channel pillars 130. In some embodiments, the dielectric substrate 100 may be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate on an insulating layer (SOI). The semiconductor may be, for example, an atom of Group IVA, such as silicon or germanium. The semiconductor compound may be, for example, a semiconductor compound formed by atoms of Group IVA, such as silicon carbide or germanium silicide, or a semiconductor compound formed by atoms of Group IIIA and Group VA, such as gallium arsenide. The dielectric substrate may include a dielectric layer formed on a silicon substrate, such as a silicon oxide layer. In other words, peripheral circuitry may be disposed beneath the dielectric substrate 100. Furthermore, the dielectric substrate 100 may include an array region R, which may include a first region R1 and a second region R2. In one embodiment, the first region R1 may be a channel pillar region, and the second region R2 may be a slit region. In other words, one or more slits may be disposed adjacent to the channel pillar region R1.

The stop layer 102 can be formed on the dielectric substrate 100. In one embodiment, the material of the stop layer 102 includes a conductive material, such as polysilicon, a III-V compound semiconductor, or a combination thereof. When the three-dimensional memory device is an embodiment of a three-dimensional NAND flash memory, the stop layer 102 can be used as a source line. When the three-dimensional memory device is an embodiment of a three-dimensional NOR flash memory, the stop layer 102 can be used as a dummy word line. Although the stop layer 102 shown in Figure 1 is a single-layer structure, the present invention is not limited thereto. In an alternative embodiment, the stop layer 102 can also be a multi-layer structure. The multi-layer structure may include a plurality of dielectric layers (such as silicon oxide layers) and a plurality of conductive layers (such as polysilicon layers) stacked alternately.

The stacked structure 110 may be formed on the stop layer 102 such that the stop layer 102 is disposed between the dielectric substrate 100 and the stacked structure 110. In one embodiment, the stacked structure 110 may include a plurality of dielectric layers 112 and a plurality of sacrificial layers 114 alternately stacked. In one embodiment, the dielectric layers 112 and the sacrificial layers 114 may be made of different materials or materials having different etching rates. For example, the dielectric layer 112 may be a silicon oxide layer, and the sacrificial layer 114 may be a silicon nitride layer, a polysilicon layer, or a metal tungsten layer. The number of dielectric layers 112 and sacrificial layers 114 may be adjusted as needed, and the present invention is not limited thereto.

A capping layer 116 may be formed on the stacked structure 110 and the vertical channel pillars 130, such that the stacked structure 110 is disposed between the stop layer 102 and the capping layer 116. In one embodiment, the material of the capping layer 116 may include a dielectric material, such as silicon oxide.

Vertical channel pillars 130 can be formed within the stacked structure 110 and stop layer 102 in the first region R1. As shown in FIG1 , vertical channel pillars 130 can penetrate the stacked structure 110 and stop layer 102 and extend partially into the dielectric substrate 100. It is noteworthy that when forming the opening 115 to accommodate the vertical channel pillars 130, the stop layer 102 not only serves as an etch stop layer but also prevents arcing during plasma etching, thereby improving device reliability. In this embodiment, the stop layer 102 can be considered a discharging layer, which is typically grounded to the silicon substrate to reduce the charge accumulated by the plasma etching, thereby preventing device damage. Therefore, when performing a high aspect ratio etching process, the stop layer 102 is usually grounded to the silicon substrate to prevent arc discharge.

Basically, according to different forms of three-dimensional memory devices, the vertical channel pillars 130 can have different aspects, which are described in detail below.

Figures 2A, 3A, and 4A illustrate cross-sectional schematic views of vertical channel pillars according to various embodiments of the present invention. Figures 2B, 3B, and 4B are plan schematic views of Figures 2A, 3A, and 4A, respectively.

2A and 2B , when the three-dimensional memory device is a three-dimensional AND flash memory, the vertical channel pillar 130A may include a charge storage structure 132, a channel layer 134, a dielectric pillar 136, a first source/drain pillar 133, and a second source/drain pillar 135. As shown in FIG2A , the first source/drain pillar 133 and the second source/drain pillar 135 may penetrate the stacked structure 110 and the stop layer 102 and partially extend into the dielectric substrate 100. In one embodiment, the first source/drain pillar 133 and the second source/drain pillar 135 may have the same conductive material, such as N-type doped (N+) polysilicon material. A dielectric pillar 136 may be disposed between the first source/drain pillar 133 and the second source/drain pillar 135 to separate the first source/drain pillar 133 from the second source/drain pillar 135. Furthermore, as shown in FIG2B , the channel layer 134 may laterally surround the dielectric pillar 136, the first source/drain pillar 133, and the second source/drain pillar 135. The first source/drain pillar 133 and the second source/drain pillar 135 each physically contact a portion of the channel layer 134. The charge storage structure 132 may laterally surround the channel layer 134. In one embodiment, the charge storage structure 132 may be a composite layer consisting of a tunneling layer, a charge storage layer, and a blocking layer. The tunneling layer, the charge storage layer, and the blocking layer may each be considered an oxide/nitride/oxide (ONO) composite layer. In another embodiment, the tunneling layer may be an oxide/nitride/oxide (ONO) composite layer or other suitable materials. In alternative embodiments, the charge storage layer may be an oxide/nitride/oxide (ONO) composite layer or other suitable materials. In other embodiments, the blocking layer may be an oxide/nitride/oxide (ONO) composite layer or other suitable materials. The channel layer 134 may include a doped polysilicon layer or an undoped polysilicon layer. The dielectric pillar 136 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

Referring to Figures 3A and 3B , when the three-dimensional memory device is a first-type three-dimensional NAND flash memory, the vertical channel pillar 130B may include a charge storage structure 132, a channel structure 234, and a dielectric pillar 236. As shown in Figure 3A , the dielectric pillar 236 may penetrate the stacked structure 110 and the stop layer 102. The channel structure 234 may include a liner 234A and a plug 234B. The liner 234A may cover the sidewalls and bottom surface of the dielectric pillar 236, while the plug 234B may seal the top surface of the dielectric pillar 236. In this case, the channel structure 234 may completely cover all surfaces of the dielectric pillar 236. The charge storage structure 132 may be disposed between the channel structure 234 and the stack structure 110. The portion of the charge storage structure 132 between the channel structure 234 and the stop layer 102 is removed so that the channel structure 234 directly contacts the stop layer 102. From the perspective of the plan view of FIG. 3B , the charge storage structure 132 may laterally surround the channel structure 234 and the dielectric pillar 236. The materials of the charge storage structure 132, the channel structure 234, and the dielectric pillar 236 are the same as those of the charge storage structure 132, the channel layer 134, and the dielectric pillar 136, respectively, and have been described in detail in the preceding paragraphs and will not be repeated here.

4A and 4B , when the three-dimensional memory device is a second-type three-dimensional NAND flash memory, the vertical channel pillar 130C may include a charge storage structure 132 and a channel pillar 334. As shown in FIG4A , the channel pillar 334 may penetrate the stacked structure 110 and the stop layer 102. The charge storage structure 132 may be disposed between the channel pillar 334 and the stacked structure 110. The portion of the charge storage structure 132 between the channel pillar 334 and the stop layer 102 is removed so that the channel pillar 334 directly contacts the stop layer 102. From the perspective of FIG4B , the charge storage structure 132 may laterally surround the channel pillar 334. The materials of the charge storage structure 132 and the channel pillar 334 are the same as those of the charge storage structure 132 and the channel layer 134, respectively, and have been described in detail in the above paragraphs, which will not be repeated here.

Referring again to FIG. 2A , after forming the vertical channel pillar 130A, a gate replacement process may be performed to replace the sacrificial layer 114 in the stacked structure 110 with a conductive layer 154, as shown in FIG. 5 to FIG. 12 .

5 to 12 are schematic cross-sectional views of a manufacturing process of a three-dimensional memory device according to an embodiment of the present invention, wherein FIG. 5 to FIG. 12 are enlarged views of the area 10 of FIG. 2A .

First, as shown in FIG5 , a first etching process is performed to form a first opening 15 in the stacked structure 110 in the second region R2. The first opening 15 penetrates the top cap layer 116 and the uppermost sacrificial layer 114T, exposing the top surface of the dielectric layer 112 beneath the uppermost sacrificial layer 114T. In one embodiment, the first etching process can be an anisotropic etching process.

Next, referring to FIG6 , a second etching process is performed through the first opening 15 to remove the top sacrificial layer 114T, thereby forming a first horizontal opening 14 between the dielectric layers 112. The first horizontal opening 14 laterally exposes the sidewalls of the vertical channel pillars 130A. In other words, the first horizontal opening 14 is defined by the dielectric layer 112 and the vertical channel pillars 130A. In one embodiment, the second etching process can be a wet etching process. For example, when the sacrificial layer is silicon nitride, the second etching process can use an etchant containing phosphoric acid, which is poured into the first opening 15 to remove the top sacrificial layer 114T. Since the etchant has a high etching selectivity for the uppermost sacrificial layer 114T, the uppermost sacrificial layer 114T can be completely removed while the dielectric layer 112 is not removed or only slightly removed.

6 and 7 , a protective material layer 118 a is formed in the first horizontal opening 14. Specifically, the protective material layer 118 a conformally covers the top surface and sidewalls of the cap layer 116, the sidewalls of the vertical channel pillars 130A, and the exposed surface and sidewalls of the dielectric layer 112. In one embodiment, the material of the protective material layer 118 a includes silicon nitride.

7 and 8 , an etch-back process is performed to remove the protective material layer 118a on the top surface and sidewalls of the top cap layer 116, on the sidewalls of the dielectric layer 112, and on a portion of the top surface of the dielectric layer, thereby forming a protective layer 118 in the first horizontal opening 14. In one embodiment, the etch-back process can remove the protective material layer 118a on the top surface of the dielectric layer 112 aligned with the first opening 15, thereby exposing the top surface of the dielectric layer 112. In this embodiment, since the etching resistance of the protective material layer 118a (i.e., nitride) is different from the etching resistance of the top cap layer 116 and the dielectric layer 112 (i.e., oxide), the excess protective material layer can be removed during the etch-back process without damaging the surfaces of the top cap layer 116 and the dielectric layer 112.

Referring to Figures 8 and 9 , a first conductive layer 124A is filled into the first horizontal opening 14. In some embodiments, the material of the first conductive layer 124A may include polycrystalline silicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide ( _WSix ), or cobalt silicide ( _CoSix ). In one embodiment, the material of the first conductive layer 124A is polycrystalline silicon. The first conductive layer 124A is formed, for example, by forming a first conductive material layer on the stacked structure 110, in the first opening 15, and in the first horizontal opening 14. Etching back is then performed to remove the first conductive material layer above the stacked structure 110 and in the first opening 15.

As shown in FIG9 , the protective layer 118 continuously covers the top surface, first sidewall 124As1, and bottom surface of the first conductive layer 124A. In one embodiment, the thickness of the protective layer 118 is between 10Å and 100Å. The thickness of the protective layer 118 can be adjusted depending on the type of memory device. The first opening 15 exposes the second sidewall 124As2 of the first conductive layer 124A, which is opposite to the first sidewall 124As1. In other words, the first opening 15 is adjacent to the second sidewall 124As2 of the first conductive layer 124A, which is opposite to the first sidewall 124As1. In one embodiment, the first conductive layer 124A can function as a virtual word line. In this embodiment, the topmost conductive layer (i.e., first conductive layer 124A) can be used as a dummy word line, which is not related to the operation of the device. By applying a bias to this dummy word line, the upper gate region can be controlled, thereby suppressing channel leakage current.

After forming the first conductive layer 124A, a gate replacement process can be performed to replace the plurality of sacrificial layers 114 with a plurality of second conductive layers 124B (as shown in FIG. 12 ). Referring to FIG. 9 and FIG. 10 , a third etching process is performed through the first opening 15 to form a second opening 17 in the stacked structure 110 . The second opening 17 penetrates the stacked structure 110 and the stop layer 102 . In this embodiment, although FIG. 10 shows the second opening 17 penetrating the stop layer 102 , the present invention is not limited thereto. In other embodiments, the second opening 17 may expose a portion of the stop layer 102 .

Referring to Figures 10 and 11 , a fourth etching process is performed through the second openings 17 to remove the plurality of sacrificial layers 114, thereby forming a plurality of second horizontal openings 18 between the plurality of dielectric layers 112. The second horizontal openings 18 laterally expose the sidewalls of the vertical channel pillars 130A. In other words, the second horizontal openings 18 are defined by the dielectric layer 112 and the vertical channel pillars 130A. In one embodiment, the fourth etching process can be a wet etching process. For example, when the sacrificial layer 114 is silicon nitride, the fourth etching process can be performed using an etchant containing phosphoric acid, which is poured into the second openings 17 to remove the sacrificial layer 114. Since the etchant has a high etching selectivity to the sacrificial layer 114, the sacrificial layer 114 can be completely removed while the dielectric layer 112 is not removed or is only slightly removed.

In one embodiment, the fourth etching process also etches a portion of the protective layer 118. Specifically, after the fourth etching process, the sidewalls of the protective layer 118 are recessed relative to the sidewalls of the dielectric layer 112 and the second sidewall 124As2 of the first conductive layer 124A, forming a gap 19. In other words, the gap 19 is defined by the dielectric layer 112, the protective layer 118, and the first conductive layer 124A.

11 and 12 , a buffer layer 120 and a second conductive layer 124B are sequentially formed in the second horizontal opening 18 . Specifically, a buffer material layer and a second conductive material layer are sequentially filled in the second horizontal opening 18 . The buffer material layer can conformally cover the surface of the structure shown in FIG. 11 and fill the second horizontal opening 18 and the gap 19 . Specifically, the buffer material layer conformally covers the top surface and sidewalls of the cap layer 116 , the sidewalls of the vertical channel pillars 130A, and the exposed surface and sidewalls of the dielectric layer 112 , and fills the gap 19 . The second conductive material layer can then fill the second horizontal opening 18 and extend laterally into the second opening 17 . In one embodiment, the buffer material layer may include a high-k material with _a dielectric constant greater than 7, such as aluminum oxide ( _Al2O3 ), helium oxide ( _HfO2 ), lutetium oxide ( _La2O5 ), transition metal oxides, lanthanide oxides, or combinations _thereof . The second conductive material layer may include polycrystalline silicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide ( _WSix ), or cobalt silicide ( _CoSix ). In one embodiment, the second conductive material layer is made of the same material as the first conductive material layer. In another embodiment, the second conductive material layer is made of a different material than the first conductive material layer.

Next, an etch-back process is performed to remove the buffer material layer and the second conductive material layer above the stack structure 110 and in the second opening 17, thereby forming a buffer layer 120 and a second conductive layer 124B in the second horizontal opening 18, and forming the buffer layer 120 in the gap 19. In one embodiment, the thickness of the buffer layer 120 is less than 45 Å. In one embodiment, the thickness of the buffer layer 120 formed on the second conductive layer 124B is less than the thickness of the buffer layer 120 in the gap 19. More specifically, the thickness of the protection layer 118 and the buffer layer 120 covering the first conductive layer 124A is greater than the thickness of the buffer layer 120 covering the second conductive layer 124B.

Thereafter, subsequent related processes (such as further forming a slit filling structure in the second opening 17) can be performed to complete the fabrication of the three-dimensional memory device.

FIG13 is a partially enlarged view of an embodiment of FIG12.

Referring to FIG. 13 , the three-dimensional memory device includes a protective layer 118 disposed on the topmost conductive layer (i.e., first conductive layer 124A) among the multiple conductive layers in the stacked structure 110. Protective layer 118 continuously covers the top surface, first sidewall 124As1, and bottom surface of first conductive layer 124A. A buffer layer 120 continuously covers the top surface, first sidewall 124Bs1, and bottom surface of second conductive layer 124B. In this embodiment, buffer layer 120 is also disposed on portions of the top and bottom surfaces of first conductive layer 124A and is connected to protective layer 118. Specifically, buffer layer 120 is disposed in gap 19 defined by dielectric layer 112, protective layer 118, and first conductive layer 124A. In this embodiment, the material of protective layer 118 is different from that of buffer layer 120. Protective layer 118 comprises silicon nitride. Vertical channel pillars 130A penetrate stacked structure 110 and abut first sidewalls 124As1 and 124Bs1 of first conductive layer 124A and second conductive layer 124B. Protective layer 118 contacts charge storage structure 132 of vertical channel pillars 130A.

FIG14 is a partially enlarged view of another embodiment of FIG12.

The 3D memory device of Figure 14 is similar to the 3D memory device of Figure 13 . Identical or similar components are denoted by identical or similar reference numerals and will not be further described here. The primary difference between the two is that the second source/drain pillar 135 of the 3D memory device of Figure 14 contacts the protective layer 118 .

During the process of forming the vertical channel pillars, the source/drain pillars (or conductive plugs) may encounter displacement issues due to uneven stress and may be etched outside the original vertical channel pillar area. As a result, the source/drain pillars (or conductive plugs) may be displaced outside the original vertical channel pillar area and contact the protective layer 118.

In conventional methods of fabricating three-dimensional memory devices, if the source/drain pillars (or conductive plugs) are displaced beyond the original vertical channel pillar area, they will contact the buffer layer. Memory cells are controlled by the topmost conductive layer (i.e., word lines), so the buffer layer must be very thin. A thin dielectric buffer layer (e.g., aluminum oxide) exists between the source/drain pillars (or conductive plugs) and the topmost conductive layer (i.e., word lines). This buffer layer cannot withstand the operating voltage bias and is therefore susceptible to dielectric breakdown at the interface, leading to bridging between the source/drain pillars (or conductive plugs) and the word lines. In other words, a buffer layer formed on the topmost conductive layer (i.e., word lines) is not sufficient to overcome the bridging problem.

However, in this embodiment, a double-gate replacement process is employed to replace the buffer layer on the topmost conductive layer with a silicon nitride layer with a high dielectric constant and protective function. Specifically, a thin silicon nitride layer (i.e., a protective layer) is formed on the surface and sidewalls of the topmost conductive layer. Silicon nitride has a much higher dielectric constant than oxide, so the protective layer helps withstand the operating voltage bias between the displaced source/drain pillars (or conductive plugs) and the word lines, thereby preventing bridging issues. In this embodiment, the topmost conductive layer can serve as a dummy word line, whose purpose is to control the gate to prevent leakage current.

15A, 15B, and 15C are respectively a three-dimensional schematic diagram, a planar schematic diagram, and a circuit schematic diagram of a three-dimensional AND flash memory 1 according to an embodiment of the present invention.

Referring to FIG. 15A , the 3D AND flash memory 1 of this embodiment has a plurality of memory cells 150. Specifically, as shown in FIG. 15A , a plurality of gate layers 154 are alternately arranged along the vertical direction and respectively surround the vertical channel pillars 130. A portion of the vertical channel pillar 130 surrounded by the gate layer 154 may constitute a memory cell 150. In this embodiment, a single vertical channel pillar 130 may define three stacked memory cells 150. However, the present invention is not limited thereto. In other embodiments, the number of memory cells 150 may be adjusted according to the number of gate layers 154 in the stacked structure 210. Specifically, memory cells 150 are formed at the intersections of gate layers 154 and vertical channel pillars 130. Therefore, the more vertically stacked gate layers 154 there are, the greater the number of memory cells 150 in a memory string. Furthermore, while FIG. 15A illustrates only two vertical channel pillars 130, the present invention is not limited thereto. In alternative embodiments, the 3D AND flash memory 1 may include multiple vertical channel pillars 130, and these vertical channel pillars 130 may be arranged in an array when viewed from above.

To operate the 3D AND flash memory 1, after manufacturing the 3D AND flash memory 1, conductive lines are formed over the 3D AND flash memory 1 to electrically connect to the 3D AND flash memory 1. In this embodiment, as shown in FIG15A , some conductive lines are formed over the first source/drain pillars 133, which serve as sources, to serve as source lines SL, and other conductive lines are formed over the second source/drain pillars 135, which serve as drains, to serve as bit lines BL. These source lines SL and bit lines BL are arranged parallel to each other and do not contact each other.

The operation of the memory cell 150 in the 3D AND flash memory 1 is described below.

As shown in FIG15B , for a 3D AND flash memory 1, each memory cell 150 can be operated individually. An operating voltage can be applied to the first source/drain pillar 133, the second source/drain pillar 135, and the corresponding gate layer 154 (which can be considered a gate or word line) of each memory cell 150 to perform a write (program), read, or erase operation. When a write voltage is applied to the first source/drain pillar 133 and the second source/drain pillar 135 , electrons can be transferred along the first and second electrical paths E1 and E2 (e.g., double-sided paths) and stored in the charge storage structure 132 because the first and second source/drain pillars 133 and 135 are connected to the channel layer 134 .

15C , the memory cells 150 of this embodiment can be arranged into multiple rows and columns to form a 3D AND flash memory array. Each memory cell 150 can include a gate G electrically connected to a word line WL (i.e., WLm, WLm+1), a source S electrically connected to a source line SL (i.e., SLn, SLn+1), and a drain D electrically connected to a bit line BL (i.e., BLn, BLn+1). It is worth noting that in the 3D AND flash memory array of this embodiment, multiple memory cells 150 can be connected in parallel along the extension direction D1 of the source/drain pillars 133, 135. Specifically, as shown in FIG15C , upper memory cell 150a and lower memory cell 150b share the same source line SLn+1 and the same bit line BLn+1 via common source/drain pillars 133 and 135. The gate of upper memory cell 150a is electrically connected to upper word line WLm+1, while the gate of lower memory cell 150b is electrically connected to lower word line WLm. In this case, the architecture and operation method of the 3D AND flash memory array of this embodiment differ from those of conventional three-dimensional NAND (3D NAND) flash memory arrays, which include multiple memory cells connected in series.

In summary, the present invention utilizes an additional high-dielectric protective layer to cover the surface and sidewalls of the topmost conductive layer, effectively preventing bridging between the source/drain pillars (or conductive plugs) and the word lines, thereby improving the reliability of the 3D memory device. Furthermore, the steps for forming the protective structure of the present invention are compatible with existing 3D memory device manufacturing processes, making it applicable to a variety of 3D memory devices.

1: Three-dimensional AND flash memory 10: Region 14: First horizontal opening 15: First opening 17: Second opening 18: Second horizontal opening 19: Gap 100: Dielectric substrate 102: Stop layer 110, 210: Stacked structure 112: Dielectric layer 114: Sacrificial layer 114T: Top sacrificial layer 115: Opening 116: Top capping layer 118: Protective layer 118a: Protective material layer 120: Buffer layer 124A: First conductive layer 124B: Second conductive layer 124As1, 124Bs1: First sidewall 124As2: Second sidewall 130, 130A, 130B, 130C: Vertical channel pillar 132: Charge storage structure 133: First source/drain pillar 134: Channel layer 135: Second source/drain pillar 136: Dielectric material 150, 150a, 150b: Memory cell 154: Conductive layer 234: Channel structure 234A: Liner 234B: Plug 236: Dielectric pillar 334: Channel pillar BL, BLn, BLn+1: Bit line D: Drain E1: First path E2: Second path G: Gate S: Source SL, SLn, SLn+1: Source lines WL, WLm, WLm+1: Word lines R: Array region R1: First region R2: Second region

Figure 1 is a schematic cross-sectional view of a three-dimensional memory device according to an embodiment of the present invention. Figures 2A, 3A, and 4A illustrate schematic cross-sectional views of vertical channel pillars according to various embodiments of the present invention. Figures 2B, 3B, and 4B are schematic plan views of Figures 2A, 3A, and 4A, respectively. Figures 5 to 12 are schematic cross-sectional views of a fabrication process for a three-dimensional memory device according to an embodiment of the present invention. Figure 13 is an enlarged partial view of one embodiment of Figure 12. Figure 14 is an enlarged partial view of another embodiment of Figure 12. Figures 15A, 15B, and 15C are, respectively, a schematic three-dimensional view, a schematic plan view, and a schematic circuit diagram of a three-dimensional AND flash memory device 1 according to an embodiment of the present invention.

112: Dielectric layer

116: Top floor

118: Protective layer

120: Buffer layer

124A: First conductor layer

124B: Second conductive layer

124As1, 124Bs1: First side wall

130A: Vertical channel column

132: Charge storage structure

133: First source/drain column

134: Channel Layer

135: Second source/drain column

136: Dielectric Materials

Claims (8)

A three-dimensional memory device comprises: a dielectric substrate; a stacked structure disposed on the dielectric substrate, wherein the stacked structure comprises a plurality of dielectric layers and a plurality of conductive layers stacked alternately; a protective layer continuously covering the top surface, the first sidewall, and the bottom surface of the uppermost conductive layer among the plurality of conductive layers, wherein the material of the protective layer comprises silicon nitride; a vertical channel column penetrating the stacked structure and adjacent to the first sidewall of the uppermost conductive layer, wherein the protective layer contacts the vertical channel column, wherein the vertical channel column comprises: a first A source/drain column and a second source/drain column penetrate the stack structure and extend into the dielectric substrate; a dielectric material is disposed between the first source/drain column and the second source/drain column to separate the first source/drain column and the second source/drain column; a channel layer surrounds the dielectric material, the first source/drain column and the second source/drain column, and the channel layer contacts the first source/drain column and the second source/drain column; and a charge storage structure surrounds the channel layer. The three-dimensional memory device of claim 1 further comprises a buffer layer continuously covering the top surface, the first side wall, and the bottom surface of the conductive layers except the uppermost conductive layer among the plurality of conductive layers. The three-dimensional memory device as described in claim 2, wherein the buffer layer is further disposed on a portion of the top surface and a portion of the bottom surface of the uppermost conductive layer and is connected to the protective layer. The three-dimensional memory device of claim 1, wherein at least one of the first source/drain pillar and the second source/drain pillar is in contact with the protective layer. The three-dimensional memory device of claim 4, wherein the uppermost conductive layer serves as a virtual word line. The three-dimensional memory device of claim 1, wherein the three-dimensional memory device comprises a three-dimensional AND flash memory, a three-dimensional NAND flash memory, a three-dimensional NOR flash memory, or a combination thereof. The three-dimensional memory device of claim 1, wherein the thickness of the protective layer is between 10Å and 100Å. The three-dimensional memory device of claim 2, wherein the thickness of the buffer layer is smaller than the thickness of the protective layer.