TWI894647B - System and method for signal optimization adjustment based on different heat source information - Google Patents

Abstract

The present disclosure provides a system for signal optimization adjustment based on different heat source information. The system includes a plurality of heat source measurers, a first system chip, a second system chip, an electrical interconnection, and a bit error risk evaluator. The first system chip includes a signal transmitter, and the second system chip includes a signal receiver. The second system chip provides an electrical characteristic state of the signal receiver, and a signal adjustment information of the signal transmitter and/or the signal receiver. The bit error risk evaluator executes signal optimization adjustment for an electrical characteristic of the signal receiver according to the electrical characteristic state. The present disclosure further provides a method for signal optimization adjustment.

Description

System and method for signal optimization adjustment based on different heat source information

The present invention relates to a system and method for signal optimization adjustment, and more particularly to a system and method for signal optimization adjustment based on different heat source information.

As people's demands for digital life continue to grow, many new wired and wireless technologies continue to develop. For example, everything from personal handheld devices to data center servers is undergoing rapid upgrades and changes to accommodate the massive, high-speed, and high-quality transmission of information.

Digital communication is nothing more than the transmission of codes representing specific meanings by chips. These codes are transmitted from a transmitter to a receiver. The higher the accuracy of the signal reception, the higher the transmission quality. Conversely, if the signal received by the receiver is inconsistent with the signal sent by the transmitter, resulting in the receiver mis-coding the chip, the signal quality is low. However, low-quality transmission equipment or devices cannot meet the rapidly changing trends in digital communications.

However, the transmission of signals—especially high-speed signals—between the transmitter and receiver chips presents numerous physical and design factors. These factors, such as noise and inter-signal interference, can cause signal inconsistencies between the transmitter and receiver. Furthermore, it's worth noting that high temperatures cause physical changes in materials, which can affect electrical transmission quality. However, existing technologies haven't yet adequately researched and explored this aspect. Therefore, systems and design methods that overcome or eliminate the impact of thermal effects on electrical components to provide high-quality digital transmission still require technological breakthroughs.

In light of this, the present invention proposes a system and method for signal optimization and adjustment, specifically a novel technology for optimizing signal adjustment based on different heat source information. This technology focuses on addressing the impact of thermal effects on electrical circuits, accurately assessing the state of heat sources in the system environment and the changes in the heat-related characteristics of signal channels, and then adopting technical means for signal optimization and adjustment.

One purpose of the present invention is to provide a system for optimizing and adjusting signals based on different heat source information. The system includes a plurality of heat source meters, a first system chip, a second system chip, electrical circuits, and an error risk evaluator. The plurality of heat source meters obtain heat source information of each component. The first system chip includes a signal transmitter. The second system chip includes a signal receiver. The electrical circuit is internally connected to the first system chip and the second system chip, and includes at least a circuit board. The second system chip provides the electrical characteristic status of the signal receiver, and signal adjustment information of the signal transmitter and/or signal receiver. The error risk evaluator optimizes the signal based on the electrical characteristic status of the signal receiver.

Another object of the present invention is to provide a method for optimizing and adjusting signals based on different heat source information. The method includes obtaining heat source information of a first system chip including a signal transmitter and heat source information of a second system chip including a signal receiver from a plurality of heat source meters within the system. Heat source information of at least a circuit board is obtained from electrical circuits internally connected to the first system chip and the second system chip. The electrical characteristic state of the signal receiver end and signal adjustment information of the signal transmitter and the signal receiver end provided by the second system chip are obtained. At least one error risk assessment is calculated. Signals are optimized and adjusted based on the electrical characteristics of the signal receiver end according to the error risk assessment.

Thus, the system and method proposed by this invention for optimizing signals based on different heat source information can focus on addressing the impact of thermal effects on electrical circuits through a new technology for optimizing signals based on different heat source information. This technology can then accurately assess the status of the heat source in the system environment and the changes in the heat characteristics of the signal channel, thereby optimizing the signal. In other words, the system and method proposed by this invention further considers the signal attenuation effects caused by thermal factors. By evaluating the thermoelectric characteristics of the entire channel, it can more accurately determine the impact of temperature on signal integrity. This allows for the adjustment and design of signal conditioning information (equalizer, pre-emphasis, de-emphasis, equalizer and/or retimer, repeater), or redesign of wiring, to achieve optimal signal adjustment to ensure signal integrity and high-quality signal transmission.

To further understand the techniques, means, and effects employed by the present invention to achieve its intended purpose, please refer to the following detailed description and accompanying drawings of the present invention. It is believed that this will provide a deeper and more detailed understanding of the purposes, features, and characteristics of the present invention. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the present invention.

The technical content and detailed description of the present invention are as follows, along with the accompanying drawings.

The following describes the implementation of this invention through specific embodiments. Those skilled in the art will readily understand its other advantages and benefits from the information provided in this specification. This invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified and altered based on different perspectives and applications without departing from the spirit of this invention.

It should be noted that the structures, proportions, sizes, and number of components illustrated in the figures included in this manual are intended solely to facilitate understanding and reading by those familiar with the art, in conjunction with the contents disclosed herein. They are not intended to limit the conditions under which this invention may be implemented, and therefore have no substantive technical significance. Any structural modifications, changes in proportions, or adjustments in size, without affecting the efficacy and objectives of this invention, shall be within the scope of the technical content disclosed herein.

Please refer to FIG1 , which is a schematic diagram of a system for optimizing signals based on different heat source information according to the present invention. FIG1 shows a high-speed serial digital signal transmission bus. The entire signal bus includes three parts: a transmitter Tx where a signal transmitter 10 is located, a signal channel CH, and a receiver Rx where a signal receiver 20 is located. In conjunction with FIG2 , which is a block diagram of a system for optimizing signals based on different heat source information according to the present invention. As shown in FIG2 , the system of the present invention includes a first system chip 1, a second system chip 2, and an electrical circuit 3 internally connected to the first and second system chips 1 and 2. The first system chip 1 includes a signal transmitter 10, the second system chip 2 includes a signal receiver 20, and the electrical circuit 3 includes at least a circuit board 30. The so-called serial signal here refers to the serial deserialization (SerDes) technology that is commonly used in current high-speed signal protocols. However, the present invention is not limited to serial signals; parallel signals are also applicable to the technical content of the present invention.

See Figure 3 for a hardware diagram of the present invention's system for optimizing signals based on different heat source information. The system's hardware (components, elements, modules, devices, equipment, etc.), such as system chips 1 and 2, signal transmitters and receivers 10 and 20, circuit board 30, and heat source sensors 11, 21, and 31, can communicate, transmit, and exchange information with each other via bus 100.

As shown in Figure 1, a signal transmitter 10 transmits a signal through an electrical line 3 (or generally referred to as a signal channel CH), ultimately being received by a signal receiver 20. The bit pattern BP transmitted by the signal transmitter 10 is represented by a digital signal, where logical 0s and 1s represent voltage variations. The signal received by the signal receiver 20 can be analyzed for electrical characteristics such as slow rise time, intersymbol interference, and attenuation loss. For example, by analyzing its eye diagram (ED), the quality of the received signal can be quickly assessed. However, the eye diagram (ED) is only one method of evaluating signal quality. Other evaluation methods based on the eye diagram ED principle, such as crosshairs and the area method, or converting voltage, current, resistance, etc. into a range score and creating various types of benchmark software tools, are also feasible.

In addition, the system disclosed in the present invention further includes a plurality of heat source meters for obtaining heat source information of the aforementioned components. Since different sections have different thermal effect conditions during digital signal transmission, as shown in Figures 1 and 2, the plurality of heat source meters include at least one heat source meter 11 located in the first system chip 1 and at least one heat source meter 21 located in the second system chip 2, wherein the heat source meter 11 obtains heat source information H1 of the first system chip 1, and the heat source meter 21 obtains heat source information H2 of the second system chip 2. In addition, the heat source meter 31 obtains heat source information H3 of the circuit board 30. The heat source meter can be, but is not limited to, a thermal sensing element, a thermometer, a thermal imager, etc., which is a meter for obtaining the temperature of the component or the thermal imaging information of the component. Thermal sensing elements are not limited to a single means of sensing temperature. Equivalent methods of obtaining thermal information, such as impedance information, voltage-current conversion, or the time-dependent variation of a specific material parameter, can all serve as temperature observation methods. Therefore, the heat source measurement defined in this invention is not limited to general sensor technology but encompasses any method that can provide physical thermal information.

For digital signal transmission, measuring electrical characteristics is a fundamental requirement in circuit design. Common electrical characteristic measurements include impedance and S-parameter measurements. Characteristic impedance is the most fundamental electrical parameter in circuit design. Impedance is typically measured using a time domain reflectometer (TDR) or vector network analyzer (VNA) with appropriate probes, primarily for single-ended and differential impedance testing. The so-called measurement in this invention does not simply refer to measurement performed using instruments. In fact, during chip-to-chip signal transmission, the changes in the electrical characteristics of the signal from the transmitter to the receiver can be measured or calculated even within the hardware system. Real-time measurement or calculation can provide the hardware system with information to adjust the signal in real time. The inclusion of such observation or adjustment mechanisms in system chips is an indispensable and important function in current advanced chips.

The aforementioned S-parameters are observations of frequency-domain characteristics and are fundamental electrical parameters in circuit design. They are typically presented in a two-port or four-port format. The most commonly used are insertion loss, dielectric constant (Dk), loss tangent (Df), return loss, voltage-to-wave ratio (VSWR), far-end crosstalk (FEXT), near-end crosstalk (NEXT), signal-to-noise ratio (SNR), attenuation-to-noise ratio (ICN), attenuation-to-crosstalk ratio (ICR), and so on. S-parameters are typically measured using a vector network analyzer (VNA) with appropriate probes, connectors, or fixtures. These parameters are not limited to direct information obtained from within the chip; by measuring impedance information, voltage and current changes, and other factors, these electrical parameters can be indirectly converted and calculated, providing a foundation for signal adjustments.

Furthermore, in digital signal transmission, equalization and balancing techniques are employed at the transmitter (Tx) and/or receiver (Rx) to compensate for signal loss and attenuation in the signal channel (CH), either actively or passively. The equalizer at the transmitter (Tx) is also commonly referred to as emphasis or emphasis. Common techniques include pre-emphasis, de-emphasis, and FFE (forward feedback equalizer). The signal to be transmitted is first encoded. Pre-emphasis and/or de-emphasis are then used to adjust the high- and low-frequency energy ratio. The signal is then boosted to a standard voltage level by a transmitter buffer before being sent to the signal channel (CH).

Common equalizer technologies at the receiver include CTLE (Continuous Time Linear Equalizer) and DFE (Decision Feedback Equalizer). When a signal enters the signal channel (CH), it may be affected by channel artifacts such as intersymbol interference (ISI), crosstalk, delay, and reflections, degrading signal quality. The degraded signal first enters the receiver buffer to be properly loaded. The signal then enters the CTLE, where the high- and low-frequency energy ratio of the degraded signal is adjusted. The DFE then uses convolution operations to restore the signal to optimal quality. It's worth noting that a fixed-amplitude equalizer isn't ideal; in practice, it's necessary to provide a design with adjustable equalization parameters to accommodate varying channel transmission environments.

Furthermore, to address the issue of increased signal attenuation and quality degradation with increased signal transmission distance, which in turn leads to data bit errors, a retimer and/or repeater are typically added between signal channels. A retimer primarily performs two functions: equalization and correction of data clock signals with deterministic or random jitter, outputting a clean signal for backend devices. Repeaters, on the other hand, use equalization or pre-emphasis techniques to compensate for and correct signal losses at the transmitter and restore signal integrity at the receiver.

In the present invention, the second system chip 2 provides the electrical characteristic status of the signal receiver 20 at the receiving end Rx, such as the impedance value, S parameter, voltage level of the received signal, or other electrical parameters of the signal receiver 20, as an evaluation of the signal received by the signal receiver 20.

Furthermore, the second system chip 2 provides signal conditioning information for the transmitter 10 and/or receiver 20, such as information for the transmitter Tx equalizer and/or receiver Rx equalizer, enabling signal conditioning. For example, the original Tx pre-emphasis value is -3.5dB, the Rx CTLE value is 8, and the DFE value is 0.035. At this point, the eye height (EH) and eye width (EW) of the eye diagram ED are 35.02mV and 0.36UI, respectively. Based on this information, the S-parameters of the signal channel CH can be calculated, and the adjustment direction can be determined.

Below, we use example values (as shown in Table 1 and Table 2) to illustrate the meaning of signal adjustment information. Room temperature P6 P7 P8 R_EW (UI) 0.435 0.362 0.388 R_EH (mV) 45.39 28.96 35.78 R_IL (dB) -25.45 -25.45 -25.45 R_CTLE 8 11 11 R_DFE1 0.03906 0.02539 0.03516 R_DFE2 0.00586 0.00000 0.00586 R_DFE3 0.00195 0.00195 0.00391 Table 2 High temperature P6 P7 P8 A_EW (UI) 0.387 0.290 0.341 A_EH (mV) 32.21 16.77 22.32 A_IL (dB) -28.45 -28.45 -28.45 A_CTLE 7 8 8 A_DFE1 0.03516 0.01953 0.02539 A_DFE2 0.00586 -0.00195 0.00195 A_DFE3 0.00195 0.00000 0.00195

The values presented in Table 1 (room temperature) and Table 2 (high temperature) clearly show that the performance of eye height and eye width at high temperature is worse than at room temperature. Furthermore, the overall channel attenuation is greater at high temperature than at room temperature. For further information, see Figure 11. Table 1 shows R_EW at room temperature, which represents the eye width value and the corresponding curve C21. R_EH represents the eye height value and the corresponding curve C11. R_IL represents the overall channel attenuation and the corresponding curve C31. Table 2 shows the eye width (A_EW) at high temperature, corresponding to curve C22, eye height (A_EH), overall channel attenuation (A_IL), and overall channel attenuation (C12). Furthermore, P6, P7, and P8 represent signal adjustment information, namely, EQ adjustment information. It is emphasized again that using eye width and height to measure signal quality is only one of many methods. Converting the voltage or current represented by the signal into a step-spacing fraction, or into a step response or pulse response, also falls within the technical scope of this invention.

For example, at power-up or at room temperature, the signal adjustment information for each chip may be initialized to a certain value. Later, during link training, the chip may select P7 as the basis for signal adjustment information. After the chip operates for a period of time, its eye height and eye width performance begin to decline due to temperature rise. At this point, if signal adjustment is desired after risk assessment and judgment, P6 or P8 can be used as the basis for signal adjustment information, as either one offers improved eye height and eye width performance. The choice of P6 or P8 as the basis for signal adjustment information is not simply based on the higher performance of eye height or eye width. For example, the P6 has higher performance in terms of eye height and eye width than the P8. However, this doesn't necessarily mean you should choose the P6 as the basis for signal adjustment information. Furthermore, it's necessary to consider the parameters of the equalizer (CTLE, DFE) as a whole. In other words, the P8 might be chosen due to its higher CTLE value (even though its eye height and eye width performance are lower). In summary, if you only base signal adjustment information on the performance of eye height and eye width while ignoring other considerations (such as EQ component parameters and the effectiveness of compensating for high- and low-frequency components), the signal adjustment information will lose its meaning. Therefore, the key to this technology is to select the most appropriate signal adjustment information to suit different channel environments.

Furthermore, the system disclosed in the present invention further includes an error risk estimator for evaluating whether to optimize the electrical characteristics of the signal receiver Rx. In other words, the present invention continues to evaluate whether the received signal is optimized. If it is determined that the received signal is error-free or has a very low error probability (extremely low error risk), the received signal is not optimized. Conversely, if the received signal has a very high error probability, the received signal is compensated according to the electrical characteristics of the signal receiver 20 to achieve signal optimization.

In one embodiment, the error risk assessment engine provides risk or no-risk feedback based on the heat source information H1, H2, H3 collected by the heat source sensors 11, 21, 31 and the limit or warning temperature of each component. For example, the warning temperature of a component is set to 85°C and the limit temperature is set to 95°C. When the heat source information H1, H2, H3 is below the warning temperature, no-risk feedback is provided, and the received signal is not optimized. Conversely, if the heat source information H1, H2, H3 is above the limit temperature, the received signal needs to be optimized. If the temperature is between the two limits, the actual conditions of the channel transmission environment can be used to evaluate whether to adjust the signal. The judgment mechanism described above is just one of many possible implementations. In reality, this judgment logic can be made more complex or simplified to meet the specific needs of different hardware systems. In current applications, this judgment mechanism is implemented as an algorithmic function, integrated into the system chip (SoC), memory, or baseboard management controller (BMC) via firmware, and executed on the hardware system. The size of this algorithm can also affect the hardware capacity of the SoC, so it can also be implemented independently in software.

FIG5 is another schematic diagram of a system for optimizing signals based on different heat source information according to the present invention. Corresponding to FIG2 , FIG5 illustrates a system comprising two independent system chips: a processor system chip 1′ and a device system chip 2′. Furthermore, each independent system chip has its own memory interface 11′, 21′, cores 12′, 22′, buses 13′, 23′, and I/O interfaces 14′, 24′. It is worth noting that the processor system chip 1′ can include both a transmitter 15′ and a receiver 16′; similarly, the device system chip 2′ can also include both a transmitter 25′ and a receiver 26′, enabling bidirectional signal transmission between the processor system chip 1′ and the device system chip 2′. Furthermore, at least one of the processor system chip 1’ and the device system chip 2’ can provide a link trainer, that is, the I/O interface 14’ of the processor system chip 1’ can provide a link trainer 17’ and/or the I/O interface 24’ of the device system chip 2’ can provide a link trainer 27’.

In one embodiment, the present invention further discloses an advanced implementation. Taking the second SoC 2, i.e., the device SoC 2', as an example, it includes a link trainer. Referring to FIG6 , the link trainer is presented in a logic tree format. It is responsible for link orientation and initialization, illustrating the initialization process from power-on or reset to the normal operating state (L0), as well as describing the low-power management states (L0s, L1, and L2). During the link training process, the two devices exchange information by sending Link Training Sequences (TSs) to configure link width, lane reversal, polarity inversion, rate negotiation, bit lock/symbol lock, speed switching, and balancing.

The aforementioned link trainer contains multiple states, each performing its own function. Specifically, the initial state upon reset is Detect, in which the device detects the presence of a device at the other end of the link. The Polling state implements bit and symbol locking to confirm the availability of the link. The Configuration state assigns link and channel numbers to valid channels. Next comes the normal operating state, L0, in which transaction layer packets (TLPs), data link layer packets (DLLPs), and physical layer ordered sets can be sent and received. L0s, L1, and L2 are all low-power states. Entering a low-power state when there are no packets to send reduces link power consumption. When a link error occurs, the device can enter the Recovery state from the normal operating state L0 to retrain the link. There is also the Loopback state, which puts both devices into a test state. There is also the Disabled state, which disables a configured link, and the Hot Reset state, which performs a hot reset of the device.

The link trainer of the second system chip 2 provides the electrical characteristic status of the signal receiver 20 and signal adjustment information for the signal transmitter 10 and the signal receiver 20. This link trainer can be implemented in a variety of ways. If a chip already has a standard or previous link trainer, it may be a module or a standalone function. In this case, one implementation method is to have the error risk estimator be a set of functions attached to the link trainer, including activation conditions or exclusion conditions for restarting link training between the signal transmitter 10 and the signal receiver 20, and used to transmit signal adjustment instructions to at least one equalizer within the first system chip 1 and/or the second system chip 2, or at least one signal adjuster in the electrical circuit 3.

In another embodiment, the second SoC 2 includes a link trainer that provides electrical characteristic status of the signal receiver 20 and signal adjustment information for the signal transmitter 10 and the signal receiver 20. The error risk estimator is a function executed on the system (not a function set attached to the link trainer) that transmits signal adjustment instructions to at least one equalizer or at least one signal adjuster of the electrical circuit 3 within the first SoC 1 and/or the second SoC 2.

In addition to pre-emphasis, de-emphasis, and FFE at the transmitter (Tx), and CTLE and DFE equalizers at the receiver (Rx), the system can also include at least one signal conditioner in electrical line 3, such as a retimer and/or redriver, which has functions such as signal amplification and reduction and contains signal conditioning information. This signal conditioner has a programmable adjustment port that can be controlled by the system chip or system hardware via commands. Therefore, by adjusting the electrical characteristics of the at least one signal conditioner, the electrical characteristics of the signal receiver (Rx) can be optimized. During the design phase, signal optimization can be achieved by adjusting pre-emphasis, de-emphasis, equalizers and/or retimers, repeaters, or by redesigning the traces. After the actual system is powered on, the primary method is to adjust pre-emphasis, de-emphasis, equalizers, and/or retimers and repeaters to achieve optimal signal adjustment. Furthermore, if the hardware system has an accelerator/card, the aforementioned thermal analysis can be used to train the AI model. Furthermore, the aforementioned thermal analysis can also be provided by a pre-loaded thermal database in the hardware system's storage device.

The aforementioned embodiments disclose technical means for achieving the present invention by means of firmware and hardware on a hardware system. In one embodiment, the electrical characteristics of the signal receiver Rx are optimized and adjusted by a control console on the system, which can be a software or operating system program. By restarting the system, the signal adjustment combination of the signal transmitter 10 and the signal receiver 20 is updated to achieve optimal signal adjustment. Restarting the system herein can refer to resetting the system by the operating system (OS). Another embodiment, such as controlling the hot reset function of the link trainer to achieve a retraining result, is also included in the embodiments of the present invention.

In addition, the system disclosed in the present invention further includes a network module 40. In one embodiment, the network module 40 is used to connect to an external database. The signal adjustment information training model is linked to the external database information, references the real-time updated training information, and transmits adjustment instructions for at least one equalizer or at least one signal conditioner in the system.

In another embodiment, the network module 40 is used to connect to the database of the external system architecture combination. The information of the heat source meters 11, 21, and 31 is used to adjust the training model of the database of the reference system architecture combination to generate heat source information H1, H2, and H3 for providing to the error risk estimator. According to the electrical characteristic state, the electrical characteristics of the signal receiver end Rx are optimized and adjusted.

Please refer to Figure 4, which is a flow chart of a method for signal adjustment based on different heat source information according to the present invention. The method can be executed by, for example, but not limited to, a computer-readable recording medium, and the method includes the following steps, which are combined with Figures 1 to 3 mentioned above. First, heat source information H1 of a first system chip 1 including a signal transmitter 10 and heat source information H2 of a second system chip 2 including a signal receiver 20 are obtained from a plurality of heat source measuring devices 11, 21, and 31 within a system (step S10).

Next, heat source information H3 is obtained for the electrical circuit 3 internally connected to the first SoC 1 and the second SoC 2, including at least the circuit board 30 (step S20). The electrical characteristics of the signal receiver Rx provided by the second SoC 2, as well as signal adjustment information for the signal transmitter 10 and/or the signal receiver 20, are obtained (step S30). At least one error risk assessment is then calculated (step S40). Finally, signal optimization is performed on the electrical characteristics of the signal receiver Rx based on the at least one error risk assessment (step S50).

For details on the method of optimizing the signal adjustment system based on different heat source information disclosed in Figures 1 to 3, please refer to the corresponding contents of the manual, so the repeated contents will not be elaborated on again.

The method of the present invention further includes obtaining signal adjustment information of at least one signal modulator, and optimizing the electrical characteristics of the signal receiver Rx by adjusting the electrical characteristics of the at least one signal modulator.

In one embodiment, calculating the error risk assessment includes collecting the heat source information H1, H2, H3 from the heat source sensors 11, 21, 31 and providing risk or no risk feedback based on the limit or warning temperature of each component.

In one embodiment, the second SoC 2 includes a link trainer. The method further includes obtaining electrical characteristic status of the signal receiver 20 and signal adjustment information of the signal transmitter 10 and/or the signal receiver 20 from the link trainer, and transmitting a signal adjustment instruction to at least one equalizer or at least one signal adjuster of the electrical circuit 3 within the first SoC 1 and/or the second SoC 2, or initiating link training between the signal transmitter 10 and the signal receiver 20.

Furthermore, please refer to Figure 12, which is another flow chart of the present invention's method for optimizing signals based on different heat source information, which is an independent method related to simulation and design methods. The method includes the following steps: First, a thermal simulation is performed to obtain heat distribution data (step S100). Then, a temperature-dependent electrical simulation is performed, and insertion loss data of the wiring is obtained using the current BRD file (step S110). Then, a temperature-dependent electrical simulation is performed to obtain insertion loss data for the chip package, connector, and cable (step S120). All elements of the channel with temperature measurement data are then created in the channel analysis tool to obtain electrical characteristics (step S130). A determination is then made as to whether a risk exists (step S140). If the determination in step S140 indicates no risk exists, the method ends. Otherwise, if the determination in step S140 indicates a risk exists, the equalizer is adjusted, the BRD file is modified, and/or the configuration design is changed (step S140). The method then returns to step S110 and repeats step S110 and subsequent steps.

As described above with respect to the independent method related to simulation and design, the method disclosed in the present invention further includes defining the system architecture and component information from the geometry and material files, including the component information of the first system chip 1, the second system chip 2 and the circuit board 30, as well as the system architecture information constituted thereby, or further including one or more cables in the electrical circuit 30. These geometry and material files can be a computer-aided design drawing file (Computer Aided Design, CAD) or an industrial drawing file format ASCII. Then, the thermal conditions of each component and the thermal flow conditions of the system chassis are initialized. These thermal flow conditions include boundary conditions, and an independent setting file can be formed. A grid file or an equivalent node matrix data file is generated by the aforementioned geometry file and/or thermal flow condition file. The grid file constructs a custom heat distribution in three-dimensional space. It also allows for finer grid division in areas with high temperature gradients, thus helping to refine and deepen thermal analysis. Furthermore, the node matrix data file constructs heat distribution using row and column node information and provides heat vectors as heat source input.

As technology evolves, the grid file or equivalent node matrix data file has evolved into other formats to reduce the need to create a grid for the geometric structure, which would otherwise result in an overly complex and large grid file. Energy matrix algorithms can also be used to completely eliminate the need for mesh creation (mesh-less). This is merely an example of a currently mainstream and reliable implementation. Therefore, a heat source analysis data file can be generated using a grid file or equivalent node matrix data file, including heat source information H1, H2, and H3 for the first system chip 1, the second system chip 2, and the circuit board 30, or further including heat source information for one or more cables. The heat source analysis data file can be generated using a finite volume method or a finite element method, enabling error risk assessment and signal optimization adjustment of the electrical characteristics of the signal receiver Rx. In one embodiment, the signal optimization adjustment involves adjusting one or more impedance matching parameters in the geometry and material file. In another embodiment, the signal optimization adjustment involves adjusting one or more trace length parameters in the geometry and material file.

Furthermore, an electrical simulation engine for thermoelectric analysis is executed. This electrical simulation engine includes the electrical characteristic states of thermoelectric coupling of one or more chip package segments, thereby generating electrical characteristic states of thermoelectric coupling in individual segments, including the transmitter segment, the channel segment, and the receiver segment (or the aforementioned segments can be further divided into multiple smaller segments), based on different heat sources. This is used to calculate the electrical characteristic states of the signal receiver Rx provided by the second system chip 2, as well as signal conditioning information for the signal transmitter 10 and/or signal receiver 20. As shown in Figure 10, a block diagram is shown, which illustrates a multi-segment signal channel composed of a processor system chip 1' (corresponding to the first system chip 1 in Figure 2), a device system chip 2' (corresponding to the second system chip 2 in Figure 2), and an electrical circuit 3'. In the processor system chip 1’, it includes a transmitter 15’ and a package structure 18’, wherein the package structure 18’ generally includes bonding wires 181’, a carrier 182’, and a sealing material 183’. Similarly, in the device system chip 2’, it includes a receiver 26’ and a package structure 28’, wherein the package structure 28’ generally includes bonding wires 281’, a carrier 282’, and a sealing material 283’. In the electrical circuit 3’, it includes, but is not limited to, a carrier 31’, a circuit board 32’, a signal line 33’, a connector 34’, an electronic component 35’, or a combination thereof. The electronic component 35’ is, for example, but not limited to, a retimer and/or a repeater, or a signal switch IC. Broadly speaking, the path a signal traverses from transmitter 15' to receiver 26' can be called a channel. Because signal paths vary in characteristics (e.g., material properties, impedance characteristics, etc.), as previously mentioned, a signal transmitted from transmitter 15' passes through package 18' of processor system chip 1', then through carrier 31' of electrical circuit 3', circuit board 32', signal line 33', connector 34', electronic component 35', and finally through package 28' of device system chip 2' until it is received by receiver 26'. During the signal transmission process, the package structure 18', carrier board 31', circuit board 32', signal line 33', connector 34', electronic component 35', and package structure 28' have different characteristics and can therefore be considered as channels through which the signal passes through different segments.

The segment information described above is not limited to being obtained through the same analysis process. In practice, information within the chip, including chip packaging, can be obtained by providing electrical parameters, thermal parameters, or electrical characteristic tables from the chip supplier. Furthermore, if the electrical circuit includes cables (copper or optical), the cable portion can also be obtained by providing corresponding electrical parameters, thermal parameters, or electrical characteristic tables from the cable supplier. This information can be stored in the system hardware's memory or storage device, as described above, or by connecting the network module 40 to an external database.

Further, please refer to Figure 7, which is a perspective diagram illustrating a system for optimizing signals based on different heat source information, according to the present invention. See also Figure 10. A processor system chip 1' (i.e., CPU) and a device system chip 2' are disposed within a system housing. Furthermore, a cable 10' (i.e., a cable within an electrical circuit 3') is disposed within the housing. Processor SoC 1' is connected to cable 10' via first trace 110', and device SoC 2' is connected to cable 10' via second trace 210'. Therefore, when a signal is transmitted from processor SoC 1' (transmitter 15') to device SoC 2' (receiver 26'), it not only passes through processor SoC 1''s package 18' and device SoC 2''s package 28', but also through cable 10'. Because the signal passes through multiple segments, distortion and attenuation occur during transmission. See Figure 8 for a top view corresponding to Figure 7. By introducing external airflow AF (e.g., from the left side of the figure), the flowing airflow directs heat generated by the heat source to the heat source measurement device, thereby obtaining heat source information for the processor system chip 1', the device system chip 2', and/or the cable 10' (i.e., the electrical line 3'). Similarly, referring to FIG. 9 , the biggest difference from FIG. 8 is that the processor system chip 1' and the device system chip 2' are directly connected via a trace 120'. When a signal is transmitted from processor SoC 1′ (transmitter 15′) to device SoC 2′ (receiver 26′), it passes through the multi-segment signal paths of processor SoC 1′'s package structure 18′ and device SoC 2′'s package structure 28′. This can cause distortion and attenuation during signal transmission, degrading signal quality. Similarly, by introducing external airflow AF (e.g., on the left side of the figure), the flowing airflow directs heat generated by the heat source to the heat source sensor, thereby obtaining heat source information for processor SoC 1′ and/or device SoC 2′.

In summary, the system and method proposed by the present invention further considers the signal attenuation effects caused by thermal factors. By evaluating the thermoelectric characteristics of the entire channel, it can more accurately determine the impact of temperature on signal integrity. This allows for adjustments and design of signal conditioning (equalizers, pre-emphasis, de-emphasis, equalizers and/or retimers, repeaters), or redesign of wiring, to achieve optimal signal conditioning to ensure signal integrity and high-quality signal transmission.

1: SoC (System on Chip) 2: SoC (System on Chip) 3: Electrical wiring 10: Signal transmitter 20: Signal receiver 30: Circuit board 40: Network module 100: Bus 11, 21, 31: Heat source measurement H1, H2, H3: Heat source information Tx: Signal transmitter Rx: Signal receiver CH: Signal channel BP: Bit stream ED: Eye diagram S10-S50: Steps 1': Processor SoC 2': Device SoC 3': Electrical wiring 11', 21': Memory interface 12', 22': Core 13': Processor bus 23': Device bus 14’, 24’: I/O interface 15’, 25’: Transmitter 16’, 26’: Receiver 17’, 27’: Link trainer 10’: Cable 110’, 210’, 120’: Tracing AF: Airflow 18’, 28’: Package 181’, 281’: Wire bonding 182’, 282’: Carrier 183’, 283’: Sealing material 31’: Carrier 32’: PCB 33’: Signal cable 34’: Connector 35’: Electronic components C11-C32: Curves S100-S150: Steps

Figure 1 is a schematic diagram of the system for optimizing signals based on different heat source information according to the present invention.

Figure 2 is a block diagram of the system for optimizing signals based on different heat source information according to the present invention.

Figure 3 is a system hardware diagram of the present invention's system for optimizing signals based on different heat source information.

Figure 4 is a flow chart of the method of the present invention for signal adjustment based on different heat source information.

FIG5 is another schematic diagram of the system of the present invention for performing signal optimization adjustment based on different heat source information.

FIG6 is a schematic diagram of a link training machine of the present invention for optimizing signal adjustment based on different heat source information.

FIG7 is a three-dimensional diagram showing a system for optimizing and adjusting signals based on different heat source information according to the present invention.

FIG8 is a top view schematically showing the system of the present invention for performing signal optimization adjustment based on different heat source information.

FIG9 is another top view illustrating the system for optimizing signals based on different heat source information according to the present invention.

Figure 10 is a channel block diagram of the system for optimizing signals based on different heat source information according to the present invention.

FIG11 is a table showing signal adjustment information for a system of the present invention that optimizes signal adjustment based on different heat source information.

FIG12 is another flow chart of the method for optimizing the signal adjustment according to different heat source information of the present invention.

1: First System on Chip

2: Second System Chip

3: Electrical wiring

10: Signal transmitter

20: Signal Receiver

11, 21, 31: Heat source measurement device

H1, H2, H3: Heat source information

Claims (21)

A system for optimizing signals based on different heat source information includes: a plurality of heat source sensors that obtain heat source information for various components; a first system-on-chip (SoC) including a signal transmitter; a second system-on-chip (SoC) including a signal receiver; an electrical circuit internally connected to the first and second SoCs, comprising at least one circuit board; the second SoC provides the signal receiver with an electrical characteristic state and signal adjustment information for the signal transmitter and/or the signal receiver; and an error risk estimator that, based on the heat source information collected by the heat source sensors and the limit or warning temperature of each component, provides feedback indicating risk or no risk. The system then optimizes the signal based on the electrical characteristic state to the electrical characteristics of the signal receiver. The system of claim 1, wherein the plurality of heat source sensors include a first heat source sensor located within the first system chip, a second heat source sensor located within the second system chip, and a third heat source sensor, respectively measuring heat source information of the first system chip, the second system chip, and the circuit board; The error risk estimator optimizes the electrical characteristics of the signal receiver based on the measured heat source information and the electrical characteristic status. The system of claim 1, wherein the system comprises: At least one signal conditioner in the electrical circuit includes the signal conditioning information; By adjusting the electrical characteristics of the at least one signal conditioner, the electrical characteristics of the signal receiver are optimized. The system as described in claim 1, wherein the second system chip includes a link trainer that provides the electrical characteristic state of the signal receiver and signal adjustment information of the signal transmitter and the signal receiver, and the error risk assessor is a function set attached to the link trainer that transmits signal adjustment instructions to at least one equalizer in the first system chip and/or the second system chip or at least one signal adjuster in the electrical circuit. The system of claim 4, wherein the additional function of the link trainer includes an activation condition or an exclusion condition for restarting link training between the signal transmitter and the signal receiver. In the system described in claim 1, the electrical characteristics of the signal receiver are optimized to adjust the signal by restarting the system through a control console on the system to update the signal adjustment combination of the signal transmitter and the signal receiver to achieve optimal signal adjustment. The system of claim 1, wherein the second SoC includes a link trainer that provides the electrical characteristic state of the signal receiver and signal adjustment information for the signal transmitter and the signal receiver, and wherein the error risk estimator is a function executed on the system that transmits signal adjustment instructions to at least one equalizer within the first SoC and/or the second SoC or at least one signal adjuster in the electrical circuit. The system as described in claim 1 includes a network module to connect to an external database, and the training model of the signal adjustment information is linked to the external database information, refers to the real-time updated training information, and transmits adjustment instructions for at least one equalizer or at least one signal adjuster in the system. The system as described in claim 1 includes a network module for connecting to a database of an external system architecture combination. The information of the heat source meter is referenced to a training model adjusted by the database of the system architecture combination to generate heat source information for providing to the error risk assessment machine, which optimizes the signal by adjusting the electrical characteristics of the signal receiver according to the electrical characteristic state. A method for signal adjustment based on different heat source information, the method comprising: obtaining heat source information of a first system chip including a signal transmitter and heat source information of a second system chip including a signal receiver from a plurality of heat source sensors within a system; obtaining heat source information of at least one circuit board included in an electrical circuit internally connected to the first system chip and the second system chip; obtaining electrical characteristic status of the signal receiver provided by the second system chip and signal adjustment information of the signal transmitter and/or the signal receiver; calculating at least one error risk assessment; and Based on the at least one error risk assessment, heat source information from the heat source sensors is collected and, based on the limit or warning temperature of each component, feedback indicating risk or no risk is provided, thereby optimizing the electrical characteristics of the signal receiver. The method of claim 10, wherein the plurality of heat source sensors include a first heat source sensor located within the first system chip, a second heat source sensor located within the second system chip, and a third heat source sensor, respectively measuring heat source information of heat generated by the first system chip, heat source information of heat generated by the second system chip, and heat source information of heat generated by the circuit board; The error risk estimator optimizes the electrical characteristics of the signal receiver based on the measured heat source information and the electrical characteristic status. The method of claim 10, wherein the method comprises: obtaining signal adjustment information of at least one signal modulator, and optimizing electrical characteristics of the signal receiver by adjusting electrical characteristics of the at least one signal modulator. The method of claim 10, wherein the second SoC includes a link trainer, the method comprising: obtaining from the link trainer an electrical characteristic state of the signal receiver and the signal adjustment information of the signal transmitter and/or the signal receiver, and sending a signal adjustment instruction to at least one equalizer or at least one signal adjuster of the electrical circuit within the first SoC and/or the second SoC, or initiating link training between the signal transmitter and the signal receiver. The method of claim 10, comprising: defining a system architecture and component information, including the first system chip, the second system chip, and the circuit board, from a geometry and material file; initializing thermal conditions of each component and thermal flow conditions of a system chassis; and generating a grid file or an equivalent node matrix data file. The method of claim 14, comprising: Generating a heat source analysis data file comprising heat source information of the first system chip, the second system chip, and the circuit board. The method of claim 14, comprising: Executing an electrical simulation engine for thermoelectric analysis to generate an electrical characteristic state based on thermoelectric coupling of different heat sources in respective segments, thereby calculating the electrical characteristic state of the signal receiver provided by the second system chip and the signal conditioning information of the signal transmitter and/or the signal receiver. The method of claim 15, wherein the system architecture and component information further includes one or more cables in the electrical circuit, and the heat source analysis data file further includes heat source information of one or more cables. The method of claim 16, wherein the electrical simulation engine for thermoelectric analysis includes the electrical characteristic states of the thermoelectric coupling of sections of one or more chip packages. The method of claim 15, wherein the data file for heat source analysis is generated by a finite volume method or a finite element method, and the error risk assessment optimizes the signal based on the electrical characteristics of the signal receiver. The method of claim 14, wherein the signal optimization adjustment is performed by adjusting one or more impedance matches of the geometry and material file. The method of claim 14, wherein the signal optimization adjustment is performed by adjusting one or more trace lengths of the geometry and material file.