Beyene et al., 2009 - Google Patents
Advanced modeling and accurate characterization of a 16 Gb/s memory interfaceBeyene et al., 2009
- Document ID
- 13578516566108807382
- Author
- Beyene W
- Madden C
- Chun J
- Lee H
- Frans Y
- Leibowitz B
- Chang K
- Kim N
- Wu T
- Yip G
- Perego R
- Publication year
- Publication venue
- IEEE transactions on advanced packaging
External Links
Snippet
As the input/output (I/O) data rate increases to several gigabits per second, determining the performance of high-speed interfaces using conventional simulation and measurement techniques is becoming very challenging. The models of the interconnects have to be …
- 238000010192 crystallographic characterization 0 title abstract description 41
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31708—Analysis of signal quality
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. varying supply voltage
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8626474B2 (en) | Simulation tool for high-speed communications links | |
Moreira et al. | An engineer's guide to automated testing of high-speed interfaces | |
Aprile et al. | An eight-lane 7-Gb/s/pin source synchronous single-ended RX with equalization and far-end crosstalk cancellation for backplane channels | |
Kam et al. | Is 25 Gb/s on-board signaling viable? | |
Dehlaghi et al. | A 0.3 pJ/bit 20 Gb/s/wire parallel interface for die-to-die communication | |
Beyene et al. | Advanced modeling and accurate characterization of a 16 Gb/s memory interface | |
Chiu et al. | A 65-nm 10-Gb/s 10-mm on-chip serial link featuring a digital-intensive time-based decision feedback equalizer | |
Levant et al. | EMC assessment at chip and PCB level: Use of the ICEM model for jitter analysis in an integrated PLL | |
Choudhary et al. | A methodology to emulate the effect of EMI in circuit simulators for wireline communication channel | |
Choi et al. | An approximate closed-form channel model for diverse interconnect applications | |
Lee et al. | A crosstalk reduction technique for microstrip MTL using mode velocity equalization | |
Song et al. | Modeling and design optimization of a wideband passive equalizer on PCB based on near-end crosstalk and reflections for high-speed serial data transmission | |
Beyene et al. | Performance analysis and model-to-hardware correlation of multigigahertz parallel bus with transmit pre-emphasis equalization | |
Oh et al. | Prediction of system performance based on component jitter and noise budgets | |
Beyene et al. | Design, modeling, and hardware correlation of a 3.2 Gb/s/pair memory channel | |
Kim et al. | Signal integrity design and analysis of a multilayer test interposer for LPDDR4 memory test with silicone rubber-based sheet contact | |
Thürmer | Modelling and performance analysis of multigigabit serial interconnects using real number based analog verification methods | |
Beyene et al. | Measurement and characterization of backplanes for serial links operating at 56 Gbps | |
Oh et al. | Statistical link analysis and in-situ characterization of high-speed memory bus in 3D package systems | |
Beyene et al. | Design and analysis methodologies of a 6.4 Gb/s memory interconnect system using conventional packaging and board technologies | |
Oikawa et al. | Return-path extraction technique for SSO analysis of low-cost wire-bonding BGA packages | |
Madrigal-Boza et al. | An IC mixed-signal framework for design, optimization, and verification of high-speed links | |
Beyene et al. | Electromagnetic modeling methodologies and design challenges of packages for 6.4-12.8 Gbps chip-to-chip interconnects | |
Beyene et al. | System performance comparisons of coreless and standard packages for data rate beyond 20 Gbps | |
Beyene et al. | Design and analysis of a TB/sec memory system |