TWI893925B - Gamma voltage generator, data driving circuit, and method for generating gamma voltages - Google Patents

Abstract

The present disclosure relates to a gamma voltage generator, a data driving circuit and a method for generating gamma voltages. The gamma voltage generator includes at least a main resistor string and at least one sampling module. The main resistor string includes multiple main voltage division nodes for outputting different gamma voltages. Some of the main voltage division nodes also serve as main reference voltage nodes, and some of the main voltage division nodes also serves as a main sampling node. The number of the main sampling nodes is less than the number of the main voltage division nodes. At least one main sampling node is disposed between two adjacent main reference voltage nodes. An inputting end and an outputting end of the sampling module are electrically connected to a same main sampling node. The sampling module samples the voltage of the main sampling node to obtain a sampled voltage, and clamps the voltage of the main sampling node at a level of the sampled voltage.

Description

Gamma voltage generator, data drive circuit, and gamma voltage generating method

This application relates to the field of display technology, and in particular to a gamma voltage generator, a data drive circuit, and a gamma voltage generation method.

With the continuous advancement of electronic technology, most consumer electronic products, such as mobile phones, portable computers, personal digital assistants (PDAs), tablet computers, and media players, now use displays as input and output devices, making these products more user-friendly. A display typically consists of a display panel and a driver circuit that drives the panel to display images. A display panel consists of multiple pixel units. The driver circuit includes a timing control circuit, a scan driver circuit, and a data driver circuit. The data-driven circuit receives multiple different gamma voltages provided by a gamma voltage generator, selects a corresponding gamma voltage based on the display data, converts the display data into a drive voltage based on the selected gamma voltage, and then provides the drive voltage to the corresponding pixel unit via the data line. The gamma voltage generator includes at least one resistor string. Typically, a terminal is connected between two adjacent resistors in the resistor string to output the gamma voltage. The input terminal of the output buffer circuit in the data-driven circuit performs a charge/discharge operation based on the gamma voltage provided by the terminal. The response time of the charge/discharge operation is related to the equivalent resistance value corresponding to the terminal on the resistor string. When the gamma voltage provided by the gamma voltage generator is less than the number of resistors in the resistor string, that is, when the equivalent resistance corresponding to some or all of the terminals increases, the gamma voltage cannot recover quickly after being disturbed. This will cause the output buffer circuit's charge/discharge operation to respond too slowly, thereby affecting the output slew rate of the data driver circuit.

The primary purpose of this application is to provide a gamma voltage generator, a data drive circuit, and a gamma voltage generation method, aiming to address the prior art problem of improving the gamma voltage recovery speed and drive voltage conversion rate of the data drive circuit.

A gamma voltage generator comprises: At least one main resistor string having multiple main voltage divider nodes for outputting different gamma voltages; at least two of the main voltage divider nodes also serve as main reference voltage nodes for receiving a gamma reference voltage, and at least one of the main voltage divider nodes also serves as a main sampling node; wherein the main voltage divider nodes at different locations serve as main reference voltage nodes and main sampling nodes, respectively, and the number of main sampling nodes is less than the number of main voltage divider nodes; at least one main sampling node is provided between any two adjacent main reference voltage nodes; and At least one sampling module corresponds to at least one main sampling node and is electrically connected to the corresponding main sampling node. The input and output of the same sampling module are electrically connected to the same corresponding main sampling node. The sampling module is used to sample the voltage of the corresponding main sampling node to obtain a sampled voltage and clamp the voltage of the main sampling node to the sampled voltage level.

Furthermore, to achieve the above objectives, this application also proposes a data driver circuit comprising a plurality of data drivers and a gamma voltage generator. Each data driver is configured to output a driving voltage to a corresponding data line based on a gamma voltage output from the gamma voltage generator. The gamma voltage generator comprises: At least one main resistor string has multiple main voltage divider nodes for outputting different gamma voltages; at least two of the main voltage divider nodes also serve as main reference voltage nodes for receiving a gamma reference voltage, and at least one of the main voltage divider nodes also serves as a main sampling node; wherein the main voltage divider nodes at different locations serve as main reference voltage nodes and main sampling nodes, respectively, and the number of main sampling nodes is less than the number of main voltage divider nodes; at least one main sampling node is provided between any two adjacent main reference voltage nodes; and At least one sampling module corresponds to at least one main sampling node and is electrically connected to the corresponding main sampling node. The input and output of the same sampling module are electrically connected to the same corresponding main sampling node. The sampling module is used to sample the voltage of the corresponding main sampling node to obtain a sampled voltage and clamp the voltage of the main sampling node to the sampled voltage level.

Furthermore, to achieve the above-mentioned objectives, this application also proposes a gamma voltage generation method for use in a data-driven circuit; the data-driven circuit includes a plurality of data drivers and a gamma voltage generator; the gamma voltage generation method comprises the following steps: Providing at least one main resistor string and at least one sampling module electrically connected to the main resistor string; Disposing at least two main reference voltage nodes and at least one main sampling node on the main resistor string; Receiving at least two corresponding gamma reference voltages via the at least two main reference voltage nodes; Electrically connecting the input and output of each sampling module to the same main sampling node corresponding to the main resistor string; Through voltage division, at least two gamma reference voltages received by at least two main reference voltage nodes form multiple different gamma voltages across a main resistor string, and these multiple gamma voltages are output to multiple data drivers. During a display cycle, when the sampling module operates in the sampling phase, it samples the voltage of the electrically connected main sampling node to obtain a sampled voltage of the corresponding main sampling node. During the same display cycle, when the sampling module operates in the hold phase, the sampling module outputs the sampled voltage to the corresponding main sampling node to clamp the voltage of the main sampling node to the sampled voltage level.

The gamma voltage generator, data driver circuit, and gamma voltage generation method of this application, by providing a main sampling node and a sampling module, can perform sampling operations during the sampling phase and clamp the voltage of the corresponding main sampling node during the holding phase. The sampled voltage obtained during the sampling phase can prevent other circuits within the system (such as those within the data driver) from disturbing the voltage of the main sampling node, significantly improving the recovery speed within the data driver and achieving the target voltage more quickly. At the same time, the sampling module samples the main sampling node on the main resistor string, which can reduce the area occupied by the gamma voltage generator in the data-driven circuit and reduce the number of gamma reference voltages, thereby reducing the wiring space of the gamma voltage generator.

In order to enable people in this technical field to better understand the solution of this application, the technical solution in the embodiment of this application will be clearly and completely described below in combination with the drawings in the embodiment of this application. Obviously, the described embodiment is only a part of the embodiment of this application, not all of the embodiments.

The terms "first," "second," and "third" in the description of this application and the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order.

Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which this application belongs. The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and/or" as used herein includes any and all combinations of one or more of the relevant listed items.

The following describes the specific implementation of the gamma voltage generator, data drive circuit, and gamma voltage generation method of this application with reference to the accompanying figures.

Please refer to Figure 1, which is a schematic diagram of a display device 1. In at least one embodiment of the present application, the display device 1 can be a liquid crystal display (LCD) or an organic light emitting diode (OLED) display with a self-luminous structure. The display device 1 includes a display area 101 and a non-display area 103 surrounding the display area 101. The display area 101 includes a plurality of scan lines S1-Sn and a plurality of data lines D1-Dm. Here, n and m are positive integers. Multiple scan lines S1-Sn extend along a first direction X and are arranged parallel to each other. Multiple data lines D1-Dm extend along a second direction Y and are arranged parallel to each other. The multiple scan lines S1-Sn and the multiple data lines D1-Dm are insulated from each other and arranged in a grid pattern, defining a plurality of pixel units 20 arranged in a matrix. In at least one embodiment of the present application, the first direction X and the second direction Y are perpendicular to each other. In other embodiments, the first direction X and the second direction Y may intersect at other angles.

The display device 1 includes a data driver circuit 100, a scan driver circuit 200, and a timing control circuit 300 disposed within the non-display area 103. Each row of pixel cells 20 is electrically connected to the data driver circuit 100 via a data line Dm, and each column of pixel cells 20 is electrically connected to the scan driver circuit 200 via a scan line Sn. The timing control circuit 300 is electrically connected to the data driver circuit 100 and the scan driver circuit 200, respectively. Based on the received input control signal CONT, the timing control circuit 300 generates a first synchronization control signal CONT1 for the data driver circuit 100 and a second synchronization control signal CONT2 for the scan driver circuit 200. Based on the received image IMAGE, the timing control circuit 300 generates image data DATA for the data driver circuit 100. Synchronization control signals may include periodic and aperiodic synchronization control signals. Synchronization control signals include vertical synchronization (Vsync), horizontal synchronization (Hsync), and data enable (DE).

Please also refer to FIG2 , which is a schematic diagram of a module of the data driver circuit 100 . In at least one embodiment of the present application, the data driver circuit 100 includes a plurality of data drivers 110 and a gamma voltage generator 120 .

Each data driver 110 is electrically connected to the gamma voltage generator 120. Each data driver 110 receives image data DATA from the timing control circuit 300, receives multiple gamma voltages VGR(1)~VGR(k) output by the gamma voltage generator 120 within a display period Td, and selects one of the gamma voltages VGR(1)~VGR(k) according to the image data DATA to convert and process the image data DATA to generate a driving voltage Sout, and provides the driving voltage Sout to the corresponding pixel unit 20 through the corresponding data line D(i) according to the synchronous control signal of the timing control circuit 300, so that the corresponding pixel unit 20 displays the image. Wherein, i, k are positive integers less than or equal to m. During a display period Td, the data driver 110 sequentially undergoes a non-driving phase T1 and a driving phase T2. During the non-driving phase T1, the data driver 110 does not perform a driving operation. During the driving phase T2, the data driver 110 performs a driving operation and outputs a corresponding driving voltage Sout to the corresponding data line D(i). Each data driver 110 includes a shift register module 111, a data latch module 112, a potential shift module 113, a digital-to-analog converter module 114, and an output buffer module 115.

The shift buffer module 111 is electrically connected to the data latch module 112 and is used to generate a sampling pulse signal to the data latch module 112.

The data lock module 112 is electrically connected to the shift register module 111 and the potential shift module 113 for temporarily storing the data signal DATA.

The potential shift module 113 is electrically connected to the data lock module 112 and the digital-to-analog conversion module 114 and is used to shift the potential of the signal.

The digital-to-analog conversion module 114 is electrically connected to the gamma voltage generator 120, the potential shift module 113, and the output buffer module 115, and is used to select one of the gamma voltages VGR(1)~VGR(k) as the target gamma voltage VGR(target) according to the modulated sampling signal and output it to the output buffer module 115.

The output buffer module 115 is electrically connected to the digital-to-analog conversion module 114 and the corresponding data line D(i) for receiving the target gamma voltage VGR(target) and providing the driving voltage Sout to the corresponding data line D(i) according to the target gamma voltage VGR(target).

The gamma voltage generator 120 is electrically connected to the data driver 110. The gamma voltage generator 120 is used to output a plurality of different gamma voltages VGR(1)-VGR(k) to the data driver 110 in a voltage division manner according to a plurality of gamma reference voltages VGMA(1)-VGMA(j) received. It should be noted that in different embodiments of the present application, the gamma reference voltages VGMA(1) to VGMA(j) can be provided by a power supply circuit external to the data driver circuit 100 or by an internal module of the data driver circuit 100, and these embodiments can all reduce the number of wirings for the gamma reference voltages VGMA(1) to VGMA(j), and in particular, the former can also reduce the number of pads within the data driver circuit 100. The gamma voltage generator 120 is provided with a plurality of main reference voltage nodes Ngama_m(1) to Ngama_m(j) and a plurality of main sampling nodes Nsample_m(1) to Nsample_m(h) for receiving the gamma reference voltages VGMA(1) to VGMA(j). Where j and h are positive integers less than k. That is, the number of main sampling nodes Nsample_m(1) to Nsample_m(h) is less than the number of gamma voltages VGR(1) to VGR(k). The gamma voltage generator 120 is also configured to sequentially operate in the sampling phase Ts and the holding phase Th within a display period Td. During the sampling phase Ts, the gamma voltage generator 120 performs a sampling operation on the main sampling nodes Nsample_m(1)-Nsample_m(h) to obtain a sampled voltage corresponding to each main sampling node Nsample_m(1)-Nsample_m(h). During the holding phase Th, the voltage of the main sampling nodes Nsample_m(1)-Nsample_m(h) is clamped to the sampled voltage level obtained during the sampling operation. The duration of the display period Td is equal to the sum of the durations of the sampling phase Ts and the holding phase Th. In at least one embodiment of the present invention, the duration of the non-driving phase T1 is shorter than the duration of the sampling phase Ts, and the duration of the driving phase T2 is longer than the duration of the holding phase Th. That is, when the data driver 110 switches from the non-driving phase T1 to the driving phase T2, the gamma voltage generator 120 remains in the sampling phase Ts and switches to the holding phase Th after a delay time Tc. In other embodiments, the duration of the non-driving phase T1 is equal to the duration of the sampling phase Ts, and the duration of the driving phase T2 is equal to the duration of the holding phase Th.

The gamma voltage generator 120 includes at least one main resistor string 121 and at least one sampling module 123. In at least one embodiment of the present application, the gamma voltage generator 120 includes one main resistor string 121. In other embodiments, the gamma voltage generator 120 may include two main resistor strings 121, wherein one main resistor string 121 is used to provide a plurality of positive gamma voltages VGR(1) to VGR(k), and the other main resistor string 121 is used to provide a plurality of negative gamma voltages (not shown). The main resistor string 121 outputs a plurality of different gamma voltages VGR(1) to VGR(k) by voltage division according to the received gamma reference voltages VGMA(1) to VGMA(j).

The main resistor string 121 includes a plurality of resistors connected in series, and forms a plurality of main voltage dividing nodes N_m(1) to N_m(k). The plurality of main voltage dividing nodes N_m(1) to N_m(k) are used to output gamma voltages VGR(1) to VGR(k). At the same time, as shown in Figures 3 to 5, a portion of the plurality of main voltage dividing nodes N_m(1) to N_m(k) can also serve as main reference voltage nodes Ngama_m(1) to Ngama_m(j), and another portion of the plurality of main voltage dividing nodes N_m(1) to N_m(k) can also serve as main sampling nodes Nsample_m(1) to Nsample_m(h). The main reference voltage nodes Ngama_m(1)-Ngama_m(j) receive corresponding gamma reference voltages VGMA(1)-VGMA(j). A sampling module 123 is provided corresponding to each main sampling node Nsample_m(1)-Nsample_m(h). The positions of the main sampling nodes Nsample_m(1)-Nsample_m(h) on the main resistor string 121 do not overlap with the positions of the main reference voltage nodes Ngama_m(1)-Ngama_m(j). In addition, as shown in Figures 3 to 5, a predetermined number of resistors are provided between any two adjacent main sampling nodes Nsample_m(1) to Nsample_m(h) and the main reference voltage nodes Ngama_m(1) to Ngama_m(j), and these predetermined numbers can be the same or different, depending on actual needs. The predetermined number can be one or more. In Figure 3, the main sampling node Nsample_m(1) is provided adjacent to the main reference voltage node Ngama_m(1), and a predetermined number of resistors are provided between the two. The main sampling node Nsample_m(1) is also provided adjacent to the main reference voltage node Ngama_m(2), and a predetermined number of resistors are provided between the two. For example, if p=41 and q=81 in FIG3 , it means that 40 resistors are set between the main sampling node Nsample_m(1) and the adjacent main reference voltage node Ngama_m(1), and 40 resistors are set between the main sampling node Nsample_m(1) and the adjacent main reference voltage node Ngama_m(2). For another example, if p=31 and q=81 in FIG3 , it means that 30 resistors are set between the main sampling node Nsample_m(1) and the adjacent main reference voltage node Ngama_m(1), and 50 resistors are set between the main sampling node Nsample_m(1) and the adjacent main reference voltage node Ngama_m(2). In FIG4 , the main sampling node Nsample_m(2) is adjacent to the main sampling node Nsample_m(1), and a predetermined number of resistors are provided between the two nodes. The main sampling node Nsample_m(2) is adjacent to the main sampling node Nsample_m(3), and a predetermined number of resistors are provided between the two nodes. For example, if o=21, p=51, and q=81 in FIG4 , it means that 30 resistors are provided between the main sampling node Nsample_m(2) and the adjacent main sampling node Nsample_m(1), and 30 resistors are provided between the main sampling node Nsample_m(2) and the adjacent main sampling node Nsample_m(3). For another example, if o=21, p=41, and q=81 in FIG4 , 20 resistors are provided between the main sampling node Nsample_m(2) and the adjacent main sampling node Nsample_m(1), and 40 resistors are provided between the main sampling node Nsample_m(2) and the adjacent main sampling node Nsample_m(3). In FIG5 , the main sampling node Nsample_m(1) and the main reference voltage node Ngama_m(1) are provided adjacent to each other, and a predetermined number of resistors are provided between the two. The main sampling node Nsample_m(1) and the main sampling node Nsample_m(2) are provided adjacent to each other, and a predetermined number of resistors are provided between the two. For example, if p=41 and q=81 in FIG5 , it means that 40 resistors are set between the main sampling node Nsample_m(1) and the adjacent main reference voltage node Ngama_m(1), and 40 resistors are set between the main sampling node Nsample_m(1) and the adjacent main sampling node Nsample_m(2). For another example, if p=31 and q=81 in FIG5 , it means that 30 resistors are set between the main sampling node Nsample_m(1) and the adjacent main reference voltage node Ngama_m(1), and 50 resistors are set between the main sampling node Nsample_m(1) and the adjacent main sampling node Nsample_m(2). Similarly, the above method for determining the number of resistors is also applicable to the other main sampling nodes Nsample_m(1)~Nsample_m(h) and main reference voltage nodes Ngama_m(1)~Ngama_m(j) in Figures 3 to 5, so it will not be repeated here.

In addition, the resistance value of each resistor in the main resistor string 121 can also be adjusted according to needs. For example, the resistance values of each resistor in the main resistor string 121 can be different, partially the same, or all the same. In practical applications, the number of gamma reference voltages VGMA(1) to VGMA(j) received by the gamma voltage generator 120 is adjustable. However, when the number of gamma reference voltages VGMA(1) to VGMA(j) is relatively small, the total resistance between two adjacent gamma reference voltages VGMA(1) to VGMA(j) may increase. Consequently, when the data driver 110 performs a charge/discharge operation, the voltage recovery speed of the gamma voltages VGR(1) to VGR(k) slows down, resulting in a decrease in the output conversion rate of the data driver circuit 100. Therefore, this application proposes various implementations to overcome this problem. As shown in FIG3 , it is a circuit diagram of the gamma voltage generator 120 a of the first embodiment. Here, j is equal to 4, k is equal to 256, and h is equal to 3. That is, the gamma voltage generator 120 a receives the first gamma reference voltage VGMA(1), the second gamma reference voltage VGMA(2), the third gamma reference voltage VGMA(3), and the fourth gamma reference voltage VGMA(4) via four main reference voltage nodes Ngama_m(1) to Ngama_m(4). On the main resistor string 121 a, one of the multiple main sampling nodes Nsample_m(1) to Nsample_m(3) can be set between any two adjacent ones of the multiple main reference voltage nodes Ngama_m(1) to Ngama_m(j). That is, a main sampling node Nsample_m(1) is set between the main reference voltage nodes Ngama_m(1)~Ngama_m(2), a main sampling node Nsample_m(2) is set between the main reference voltage nodes Ngama_m(2)~Ngama_m(3), and a main sampling node Nsample_m(3) is set between the main reference voltage nodes Ngama_m(3)~Ngama_m(4). On the main resistor string 121a, the main reference voltage node Ngama_m(1) can also be used as a node for outputting the gamma voltage VGR(1), the main reference voltage node Ngama_m(2) can also be used as a node for outputting the gamma voltage VGR(q), the main reference voltage node Ngama_m(3) can also be used as a node for outputting the gamma voltage VGR(s), and the main reference voltage node Ngama_m(4) can also be used as a node for outputting the gamma voltage VGR(256). Similarly, on the main resistor string 121a, the main sampling node Nsample_m(1) can also serve as a node for outputting the gamma voltage VGR(p), the main sampling node Nsample_m(2) can also serve as a node for outputting the gamma voltage VGR(r), and the main sampling node Nsample_m(3) can also serve as a node for outputting the gamma voltage VGR(t).

As shown in FIG4 , it is a circuit diagram of the gamma voltage generator 120 b of the second embodiment. Here, j is equal to 4, k is equal to 256, and h is equal to 9. That is, the gamma voltage generator 120 b receives the first gamma reference voltage VGMA(1), the second gamma reference voltage VGMA(2), the third gamma reference voltage VGMA(3), and the fourth gamma reference voltage VGMA(4) via four main reference voltage nodes Ngama_m(1) to Ngama_m(4), respectively. On the main resistor string 121 b, three main sampling nodes Nsample_m(1) to Nsample_m(h) are provided between any two adjacent main reference voltage nodes Ngama_m(1) to Ngama_m(j). That is, main sampling nodes Nsample_m(1) to Nsample_m(3) are provided between the main reference voltage nodes Ngama_m(1) to Ngama_m(2), main sampling nodes Nsample_m(4) to Nsample_m(6) are provided between the main reference voltage nodes Ngama_m(2) to Ngama_m(3), and main sampling nodes Nsample_m(7) to Nsample_m(9) are provided between the main reference voltage nodes Ngama_m(3) to Ngama_m(4). On the main resistor string 121b, the main reference voltage node Ngama_m(1) can also be used as a node for outputting the gamma voltage VGR(1), the main reference voltage node Ngama_m(2) can also be used as a node for outputting the gamma voltage VGR(q+1), the main reference voltage node Ngama_m(3) can also be used as a node for outputting the gamma voltage VGR(t+1), and the main reference voltage node Ngama_m(4) can also be used as a node for outputting the gamma voltage VGR(256). Similarly, on the main resistor string 121b, the main sampling node Nsample_m(1) can be used as a node for outputting the gamma voltage VGR(o), the main sampling node Nsample_m(2) can be used as a node for outputting the gamma voltage VGR(p), the main sampling node Nsample_m(3) can be used as a node for outputting the gamma voltage VGR(q), the main sampling node Nsample_m(4) can be used as a node for outputting the gamma voltage VGR(q+2), and the main sampling node Nsample_m (5) can also be used as a node for outputting the gamma voltage VGR(s+1), the main sampling node Nsample_m(6) can also be used as a node for outputting the gamma voltage VGR(t), the main sampling node Nsample_m(7) can also be used as a node for outputting the gamma voltage VGR(t+2), the main sampling node Nsample_m(8) can also be used as a node for outputting the gamma voltage VGR(u+1), and the main sampling node Nsample_m(9) can also be used as a node for outputting the gamma voltage VGR(v).

FIG5 is a schematic circuit diagram of a gamma voltage generator 120 c according to a third embodiment. Here, j is equal to 2, k is equal to 256, and h is equal to 5. Specifically, the gamma voltage generator 120 c receives a first gamma reference voltage VGMA(1) and a second gamma reference voltage VGMA(2) via two main reference voltage nodes Ngama_m(1) to Ngama_m(2). A plurality of main sampling nodes Nsample_m(1) to Nsample_m(h) are provided between the two main reference voltage nodes Ngama_m(1) to Ngama_m(2) on the main resistor string 121 c. That is, five main sampling nodes Nsample_m(1) to Nsample_m(5) are provided between the main reference voltage nodes Ngama_m(1) to Ngama_m(2). The main reference voltage node Ngama_m(1) on the main resistor string 121c can also serve as a node for outputting the gamma voltage VGR(1), and the main reference voltage node Ngama_m(2) on the main resistor string 121c can also serve as a node for outputting the gamma voltage VGR(256). Similarly, on the main resistor string 121c, the main sampling node Nsample_m(1) can also serve as a node for outputting the gamma voltage VGR(p), the main sampling node Nsample_m(2) can also serve as a node for outputting the gamma voltage VGR(q), the main sampling node Nsample_m(3) can also serve as a node for outputting the gamma voltage VGR(r), the main sampling node Nsample_m(4) can also serve as a node for outputting the gamma voltage VGR(s), and the main sampling node Nsample_m(5) can also serve as a node for outputting the gamma voltage VGR(t).

In other embodiments, the number of primary sampling nodes Nsample_m(1) to Nsample_m(h) inserted between any two adjacent primary reference voltage nodes Ngama_m(1) to Ngama_m(j) on the primary resistor string 121 may be different or partially the same, and may be set according to actual needs. Taking the primary resistor string 121c shown in FIG5 as an example, the number of primary sampling nodes Nsample_m(1) to Nsample_m(h) that can be set between the primary reference voltage nodes Ngama_m(1) to Ngama_m(2) can be adjusted to any value less than k. For example, one main sampling node Nsample_m(1), ten main sampling nodes Nsample_m(1)-Nsample_m(10), one hundred main sampling nodes Nsample_m(1)-Nsample_m(100), or two hundred main sampling nodes Nsample_m(1)-Nsample_m(200) may be set between the main reference voltage nodes Ngama_m(1)-Ngama_m(2). In addition, taking the main resistor string 121b shown in FIG4 as an example, the number of main sampling nodes Nsample_m(1)-Nsample_m(h) set between any two adjacent main reference voltage nodes Ngama_m(1)-Ngama_m(j) may also be adjusted as needed. For example, one main sampling node Nsample_m(1) can be set between the main reference voltage nodes Ngama_m(1) to Ngama_m(2), two main sampling nodes Nsample_m(2) to Nsample_m(3) can be set between the main reference voltage nodes Ngama_m(2) to Ngama_m(3), and four main sampling nodes Nsample_m(4) to Nsample_m(7) can be set between the main reference voltage nodes Ngama_m(3) to Ngama_m(4). In addition, the positions of the main sampling nodes Nsample_m(1) to Nsample_m(3) can be adjusted as needed. Taking the main resistor string 121a shown in FIG3 as an example, the main sampling node Nsample_m(1) is set at a position midway between the main reference voltage nodes Ngama_m(1) and Ngama_m(2). That is, the amount of resistance between the main sampling node Nsample_m(1) and the main reference voltage node Ngama_m(1) is equal to the amount of resistance between the main sampling node Nsample_m(1) and the main reference voltage node Ngama_m(2). Alternatively, the main sampling node Nsample_m(1) can also be set close to the main reference voltage node Ngama_m(1). That is, the amount of resistance between the main sampling node Nsample_m(1) and the main reference voltage node Ngama_m(1) is smaller than the amount of resistance between the main sampling node Nsample_m(1) and the main reference voltage node Ngama_m(2). Alternatively, the main sampling node Nsample_m(1) may be arranged close to the main reference voltage node Ngama_m(2). That is, the amount of resistance between the main sampling node Nsample_m(1) and the main reference voltage node Ngama_m(1) is greater than the amount of resistance between the main sampling node Nsample_m(1) and the main reference voltage node Ngama_m(2).

For example, in the embodiments shown in Figures 3 to 5 , a sampling module 123a is provided corresponding to each main sampling node Nsample_m(1) to Nsample_m(h), and the input and output of the same sampling module 123a are electrically connected to the same main sampling node Nsample_m(h) on the main resistor string 121. The input of the sampling module 123a is used to sample the main sampling node Nsample_m(h) during the sampling phase Ts to obtain a sampled voltage, and the output of the sampling module 123a is used to output the sampled voltage to the main sampling node Nsample_m(h) during the holding phase Th, thereby clamping the voltage of the main sampling node Nsample_m(h) to the sampled voltage level. In other words, in the embodiments of FIG. 3 to FIG. 5 , the sampling module 123 a performs a sampling operation and a holding operation on the same main sampling node Nsample_m(h), so that the voltage on the corresponding main sampling node Nsample_m(h) can quickly recover to the corresponding sampling voltage level when disturbed (e.g., during the driving phase).

Please refer to Figures 6 and 7, which are schematic circuit diagrams of the sampling module 123a in the sampling phase Ts and the holding phase Th, respectively. The sampling module 123a is electrically connected to the corresponding main sampling node Nsample_m(1), and the main sampling node Nsample_m(1) can also serve as a node for outputting the gamma voltage VGR(p). Here, p is a positive integer less than or equal to k. Within a display period Td, the sampling module 123a operates in the sampling phase Ts and the holding phase Th, respectively. During the sampling phase Ts, the sampling module 123a samples the voltage on the main sampling node Nsample_m(1) to obtain a corresponding sampled voltage. During the holding phase Th, the sampling module 123a clamps the voltage on the corresponding main sampling node Nsample_m(1) to the level of the sampled voltage.

The sampling module 123a includes an operational amplifier OP1, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, and a holding capacitor C. The control terminal of the first transistor Q1 receives a first control signal HSPB, a first connection terminal of the first transistor Q1 is electrically connected to the output terminal of the operational amplifier OP1, and a second connection terminal of the first transistor Q1 is electrically connected to the corresponding main sampling node Nsample_m(1). The control terminal of the second transistor Q2 receives a second control signal HSP, a first connection terminal of the second transistor Q2 is electrically connected to the output terminal of the operational amplifier OP1, and a second connection terminal of the second transistor Q2 is electrically connected to the corresponding main sampling node Nsample_m(1). The control end of the third transistor Q3 receives the first control signal HSPB, the first connection end of the third transistor Q3 is electrically connected to the positive input end of the operational amplifier OP1, and the second connection end of the third transistor Q3 is electrically connected to the corresponding main sampling node Nsample_m(1). The control end of the fourth transistor Q4 receives the second control signal HSP, the first connection end of the fourth transistor Q4 is electrically connected to the positive input end of the operational amplifier OP1, and the second connection end of the fourth transistor Q4 is electrically connected to the corresponding main sampling node Nsample_m(1). That is, the first transistor Q1 and the second transistor Q2 are connected in parallel as a first switching element, and the third transistor Q3 and the fourth transistor Q4 are connected in parallel as a second switching element. One end of the capacitor C is electrically connected to the positive input end of the operational amplifier OP1, and the other end is grounded. Holding capacitor C is used to charge and discharge during the sampling phase Ts to preserve the sampled voltage and to maintain the voltage at the positive input of operational amplifier OP1 at the sampled voltage level during the holding phase Th. The negative input of operational amplifier OP1 is electrically connected to the output of operational amplifier OP1. Due to the connection of operational amplifier OP1, a virtual short circuit exists between the positive and negative inputs of operational amplifier OP1, resulting in the same voltage at the positive, negative, and output of operational amplifier OP1. In other words, the voltages at the positive, negative, and output of operational amplifier OP1 are the same as the sampled voltage of holding capacitor C. The first control signal HSPB and the second control signal HSP are output by timing control circuit 300 and are inverse signals of each other. At any given moment, the potential states of the first control signal HSPB and the second control signal HSP are opposite. That is, when the first control signal HSPB is high, the second control signal HSP is low; when the first control signal HSPB is low, the second control signal HSP is high. In at least one embodiment of the present application, the first transistor Q1 and the fourth transistor Q4 are N-type field-effect transistors (NMOS); the second transistor Q2 and the third transistor Q3 are P-type field-effect transistors (PMOS); wherein the control terminal is a gate, the first connection terminal is a source, and the second connection terminal is a drain.

Please refer to FIG8 , which is a timing diagram showing the drive signal LD, the gamma voltage VGR(p), the target gamma voltage VGR(target), the drive voltage Sout output by the output buffer module 115, and the first control signal HSPB. The input and output of the sampling module 123 a are both electrically connected to the main sampling node Nsample_m(1), and the main sampling node Nsample_m(1) can also serve as a node for outputting the gamma voltage VGR(p). That is, the input and output of the sampling module 123 a are both electrically connected to the main voltage divider node N_m(p) on the main resistor string 121. The dotted waveforms in FIG8 are voltage variation curves of the gamma voltage VGR(p), the target gamma voltage VGR(target), and the drive voltage Sout output by the output buffer module 115 in the prior art. The working principle of the data drive circuit 100 is described in detail as follows:

During the non-driving phase T1, the display drive signal LD is at a low level, the voltage of the main sampling node Nsample_m(1) is the gamma voltage VGR(p), and the gamma voltage VGR(p) is the reference voltage Va1. The voltage on the corresponding target gamma voltage VGR(target) is at a first low voltage Vb2, and the drive voltage Sout output by the output buffer module 115 is at a second low voltage Vc2. At this time, the first control signal HSPB is at a low level, the first transistor Q1 and the second transistor Q2 are turned off, and the third transistor Q3 and the fourth transistor Q4 are turned on, causing the sampling module 123a to operate in the sampling phase Ts and perform a sampling operation. At this time, the signal path is shown by the arrow in Figure 6. The current on the main sampling node Nsample_m(1) flows from the main sampling node Nsample_m(1) through the third transistor Q3 and the fourth transistor Q4 connected in parallel to the positive input terminal of the operational amplifier OP1, and charges the holding capacitor C. The driving voltage Sout output by the output buffer module 115 is at the second low voltage Vc2. In at least one embodiment of the present application, the first low voltage Vb2 and the second low voltage Vc2 are the same. The first low voltage Vb2 and the second low voltage Vc2 can be 0V or other values.

When the device switches from the non-driving phase T1 to the driving phase T2 and within the delay time Tc, the display drive signal LD is at a high level, and the data driver 110 begins driving. At this time, the first control signal HSPB remains at a low level, and the sampling module 123a remains in the sampling phase Ts. The first transistor Q1 and the second transistor Q2 remain off, while the third transistor Q3 and the fourth transistor Q4 remain on. The gamma voltage VGR(p) of the main sampling node Nsample_m(1) is maintained at the reference voltage Va1, the voltage on the corresponding target gamma voltage VGR(target) is maintained at the first low voltage Vb2, and the driving voltage Sout output by the output buffer module 115 is maintained at the second low voltage Vc2.

After a delay time Tc, the first control signal HSPB switches to a high level, and the sampling module 123a switches to the hold phase Th. At this time, the first transistor Q1 and the second transistor Q2 are turned on, while the third transistor Q3 and the fourth transistor Q4 are turned off. In the event of interference (for example, when the data driver 110 draws current from the gamma voltage generator 120 during the driving phase T2), the gamma voltage VGR(p) at the main sampling node Nsample_m(1) experiences a transient disturbance. Specifically, the gamma voltage VGR(p) changes from the reference voltage Va1 to the transient voltage Va2. In the example of FIG8 , the transient voltage Va2 is less than the reference voltage Va1, but in other cases, the transient voltage Va2 may also be greater than the reference voltage Va1. Under the combined action of the holding capacitor C and the operational amplifier OP1, the gamma voltage VGR(p) on the main sampling node Nsample_m(1) quickly recovers from the transient voltage Va2 to the reference voltage Va1. At this time, the signal path is as shown by the arrow in FIG7 . The voltage is provided to the main sampling node Nsample_m(1) from the positive input terminal of the operational amplifier OP1 through the first transistor Q1 and the second transistor Q2 connected in parallel, so that the gamma voltage VGR(p) of the main sampling node Nsample_m(1) can recover quickly. Corresponding to the voltage on the target gamma voltage VGR(target) rising from the first low voltage Vb2 to the first high voltage Vb1, the drive voltage Sout output by the output buffer module 115 rises from the second low voltage Vc2 to the second high voltage Vc1. In at least one embodiment of the present application, the reference voltage Va1, the first high voltage Vb1, and the second high voltage Vc1 are the same.

In the above-mentioned data driver circuit 100, compared with the prior art (dashed waveform in FIG8 ), by performing a sampling operation in the sampling phase Ts by the sampling module 123a and clamping the voltage of the main sampling nodes Nsample_m(1) to Nsample_m(h) to the sample voltage level obtained in the sampling phase Ts in the holding phase Th, other circuits in the system (e.g., circuits in the data driver 110) can be prevented from disturbing the voltage of the main sampling nodes Nsample_m(1) to Nsample_m(h). This significantly improves the recovery speed of the internal voltage of the data driver 110, thereby increasing the conversion rate of the driving voltage Sout and achieving the target voltage level more quickly. In addition, by designing the gamma voltage generator 120 so that the number of sampling modules 123a is smaller than the number of gamma voltages VGR(1) to VGR(k), the area occupied by the gamma voltage generator 120a in the data-driven circuit 100 can be reduced. Furthermore, by sampling and holding the main sampling nodes Nsample_m(1) to Nsample_m(h) on the main resistor string 121, the number of gamma reference voltages VGMA(1) to VGMA(j) can be reduced, thereby reducing the wiring space of the gamma voltage generator 120a.

In other words, the first to third embodiments of the present invention can improve the recovery speed of the gamma voltages VGR(1) to VGR(k) in the data driver circuit 100 and the conversion rate of the driving voltage Sout output by the data driver circuit 100 while reducing the circuit area of the gamma voltage generator 120a and the number of wirings of the gamma reference voltages VGMA(1) to VGMA(j).

Please refer to Figures 9 and 10. Figure 9 is a schematic diagram of the data-driven circuit 100 according to the fourth embodiment of the present invention, and Figure 10 is a schematic diagram of the gamma voltage generator 120d according to the fourth embodiment of the present invention. The circuit structure of the gamma voltage generator 120d according to the fourth embodiment is substantially the same as that of the gamma voltage generator 120a according to the first embodiment. In other words, the description of the gamma voltage generator 120a according to the first embodiment is generally applicable to the gamma voltage generator 120d according to the fourth embodiment. The main difference between the two is that the gamma voltage generator 120d also includes a pre-stage resistor string 122 and a sampling module 123b. The pre-stage resistor string 122 has the same structure as the main resistor string 121, and the two are connected in parallel. The main resistor string 121 and the pre-stage resistor string 122 have the same number of resistors, and the resistance values of the corresponding resistors at the same position are the same or approximately the same. That is, the pre-stage resistor string 122 has a plurality of pre-stage voltage divider nodes N_f(1) to N_f(k). At the same time, a portion of the plurality of pre-stage voltage divider nodes N_f(1) to N_f(k) on the pre-stage resistor string 122 can be used as pre-stage reference voltage nodes Ngama_f(1) to Ngama_f(j), and these nodes are respectively electrically connected to the corresponding main reference voltage nodes Ngama_m(1) to Ngama_m(j) on the main resistor string 121 for receiving the gamma reference voltage VGMA(1) to VGMA(j). For example, as shown in FIG10 , the pre-stage reference voltage node Ngama_f(1) on the pre-stage resistor string 122 is electrically connected to the main reference voltage node Ngama_m(1) on the main resistor string 121 and is used to receive the gamma reference voltage VGMA(1). In addition, another portion of the multiple pre-stage voltage divider nodes N_f(1) to N_f(k) on the pre-stage resistor string 122 can be used as pre-stage sampling nodes Nsample_f(1) to Nsample_f(h), and these nodes are respectively located at the same position as the corresponding main sampling nodes Nsample_m(1) to Nsample_m(h) on the main resistor string 121, and the pre-stage sampling nodes Nsample_f(1) to Nsample_f(h) at the same position further serve as inputs of the sampling module 123b. In other words, two ends of each sampling module 123 b are electrically connected between the pre-stage sampling nodes Nsample_f(1)-Nsample_f(h) of the pre-stage resistor string 122 and the corresponding main sampling nodes Nsample_m(1)-Nsample_m(h) on the main resistor string 121 .

For example, as shown in FIG10 , a sampling module 123 b is provided between the pre-stage sampling node Nsample_f(1) on the pre-stage resistor string 122 and the main sampling node Nsample_m(1) on the main resistor string 121, and an input end of the sampling module 123 b is electrically connected to the pre-stage sampling node Nsample_f(1), and an output end of the sampling module 123 b is electrically connected to the main sampling node Nsample_m(1).

Please refer to Figures 11 to 13 . Figure 11 is a schematic circuit diagram of sampling module 123b in the sampling phase Ts. Figure 12 is a schematic circuit diagram of sampling module 123b in the holding phase Th. Figure 13 is a timing diagram showing the driving signal LD, gamma voltage VGR(p), target gamma voltage VGR(target), driving voltage Sout output by output buffer module 115, and first control signal HSPB. The dashed waveforms in Figure 13 represent the voltage variation curves of gamma voltage VGR(p), target gamma voltage VGR(target), and driving voltage Sout output by output buffer module 115 in the prior art. The input end of sampling module 123b is electrically connected to the pre-stage sampling node Nsample_f(1) on the pre-stage resistor string 122, and the output end of sampling module 123b is electrically connected to the main sampling node Nsample_m(1) on the main resistor string 121. In other words, the input end of sampling module 123b is electrically connected to the pre-stage voltage divider node N_f(p) on the pre-stage resistor string 122, which serves as the pre-stage sampling node Nsample_f(1), and the output end of sampling module 123b is electrically connected to the main voltage divider node N_m(p) on the main resistor string 121. Compared to the sampling module 123a of the aforementioned embodiment, the sampling module 123b does not include the third transistor Q3, the fourth transistor Q4, and the holding capacitor C, and the non-inverting input terminal of the operational amplifier OP1 is directly electrically connected to the pre-stage sampling node Nsample_f(1) of the pre-stage resistor string 122. During the sampling phase Ts and the holding phase Th, the sampling module 123b continuously performs a sampling operation to provide the voltage of the pre-stage sampling node Nsample_f(1) on the pre-stage resistor string 122, i.e., the pre-stage gamma voltage (not shown), as a sampling voltage to the non-inverting input terminal of the operational amplifier OP1. In addition, the positions of the plurality of pre-stage sampling nodes Nsample_f(1) to Nsample_f(h) on the pre-stage resistor string 122 are the same as the positions of the plurality of main sampling nodes Nsample_m(1) to Nsample_m(h) on the corresponding main resistor string 121. That is, the plurality of pre-stage gamma voltages are substantially the same as the corresponding VGR(1) to VGR(k) on the main resistor string 121. When switching to the driving stage T2, as described above, the gamma voltage VGR(p) of the main sampling node Nsample_m(1) may be disturbed and change from the reference voltage Va1 to the transient voltage Va2. At the same time, according to the sampling voltage provided by the pre-stage sampling node Nsample_f(1) of the pre-stage resistor string 122, the gamma voltage VGR(p) of the main sampling node Nsample_m(1) on the main resistor string 121 can quickly recover from the transient voltage Va2 to the reference voltage Va1.

In the above-mentioned data driver circuit 100, compared with the prior art (dashed waveform in FIG13 ), by continuously performing sampling operations in the sampling phase Ts and the holding phase Th by the sampling module 123b and clamping the voltage of the main sampling nodes Nsample_m(1) to Nsample_m(h) to the level of the sampled voltage obtained in the sampling phase Ts in the holding phase Th, other circuits in the system (e.g., circuits in the data driver 110) can be prevented from disturbing the voltage of the main sampling nodes Nsample_m(1) to Nsample_m(h), thereby significantly improving the recovery speed of the internal voltage of the data driver 110, thereby increasing the conversion rate of the driving voltage Sout and achieving the target voltage level more quickly. At the same time, within a display period Td, the sampling module 123b samples the pre-stage sampling nodes Nsample_f(1) to Nsample_f(h) on the pre-stage resistor string 122 in real time, and clamps the voltage of the main sampling nodes Nsample_m(1) to Nsample_m(h) only during the hold phase Th. This can reduce the number of gamma reference voltages VGMA(1) to VGMA(j), thereby reducing the wiring space of the gamma voltage generator 120. In addition, the gamma voltage generator 120d can reduce the area occupied by the gamma voltage generator 120d in the data driving circuit 100 by setting the number of sampling modules 123b to be smaller than the number of gamma voltages VGR(1) to VGR(k).

On the other hand, by adding the pre-stage resistor string 122, the circuit structure of the sampling module 123 is simplified, so that the operational amplifier OP1 can directly clamp the main sampling nodes Nsample_m(1) to Nsample_m(h) to the sampling voltage via the voltage divider on the pre-stage resistor string 122. This can reduce the number of electronic components in the sampling module 123 (i.e., the third transistor Q3, the fourth transistor Q4, and the holding capacitor C are omitted), making it applicable to gamma voltage generators 120 with different structures.

In addition, it should be noted that in this embodiment, the node configuration of the main resistor string 121 and the corresponding pre-stage resistor string 122 of the gamma voltage generator 120d can be varied in many ways, just like the main resistor strings 121a, 121b, and 121c in the other embodiments described above, such as changing the number of gamma reference voltages VGMA(1) to VGMA(j), and changing the number and location of the sampling modules 123b.

Please refer to Figure 14, which is a flow chart of a gamma voltage generation method according to a first embodiment. In this embodiment, the gamma voltage generation method can be applied to a data driver circuit 100. The data driver circuit 100 may include more or less hardware or software than shown in Figures 1 to 7, or a different component configuration. It is understood that the implementation of the gamma voltage generation method is not limited to application to the data driver circuit 100 shown in Figures 1 to 7. The gamma voltage generation method is illustrated with the aid of the diagrams for ease of explanation only. The gamma voltage generation method includes the following steps:

S1401, provide at least one main resistor string 121 and at least one sampling module 123a electrically connected to the main resistor string 121.

The main resistor string 121 includes a plurality of resistors connected in series, and forms a plurality of main voltage dividing nodes N_m(1) to N_m(k). The plurality of main voltage dividing nodes N_m(1) to N_m(k) are used to output different gamma voltages VGR(1) to VGR(k).

S1402, set at least two main reference voltage nodes Ngama_m(1)-Ngama_m(j) and at least one main sampling node Nsample_m(1)-Nsample_m(h) on the main resistor string 121.

As shown in Figures 3 to 5, a portion of the multiple main voltage divider nodes N_m(1) to N_m(k) can also serve as main reference voltage nodes Ngama_m(1) to Ngama_m(j), and another portion of the multiple main voltage divider nodes N_m(1) to N_m(k) can also serve as main sampling nodes Nsample_m(1) to Nsample_m(h). The main reference voltage nodes Ngama_m(1) to Ngama_m(j) receive the corresponding gamma reference voltages VGMA(1) to VGMA(j).

In other embodiments, the number of primary sampling nodes Nsample_m(1) to Nsample_m(h) inserted between any two adjacent primary reference voltage nodes Ngama_m(1) to Ngama_m(j) on the primary resistor string 121 may be different or partially the same, and may be set according to actual needs. Taking the primary resistor string 121c shown in FIG5 as an example, the number of primary sampling nodes Nsample_m(1) to Nsample_m(h) that can be set between the primary reference voltage nodes Ngama_m(1) to Ngama_m(2) can be adjusted to any value less than k. For example, one main sampling node Nsample_m(1), ten main sampling nodes Nsample_m(1)-Nsample_m(10), one hundred main sampling nodes Nsample_m(1)-Nsample_m(100), or two hundred main sampling nodes Nsample_m(1)-Nsample_m(200) may be set between the main reference voltage nodes Ngama_m(1)-Ngama_m(2). In addition, taking the main resistor string 121b shown in FIG4 as an example, the number of main sampling nodes Nsample_m(1)-Nsample_m(h) set between any two adjacent main reference voltage nodes Ngama_m(1)-Ngama_m(j) may also be adjusted as needed. For example, one main sampling node Nsample_m(1) can be set between the main reference voltage nodes Ngama_m(1) to Ngama_m(2), two main sampling nodes Nsample_m(2) to Nsample_m(3) can be set between the main reference voltage nodes Ngama_m(2) to Ngama_m(3), and four main sampling nodes Nsample_m(4) to Nsample_m(7) can be set between the main reference voltage nodes Ngama_m(3) to Ngama_m(4). On the other hand, the positions of the main sampling nodes Nsample_m(1) to Nsample_m(3) can be adjusted as needed. Taking the main resistor string 121a shown in Figure 3 as an example, the positions of the main sampling nodes Nsample_m(1) to Nsample_m(3) can be adjusted as needed. For example, the main sampling node Nsample_m(1) is set at a middle position between the main reference voltage nodes Ngama_m(1) and Ngama_m(2). That is, the amount of resistance between the main sampling node Nsample_m(1) and the main reference voltage node Ngama_m(1) is equal to the amount of resistance between the main sampling node Nsample_m(1) and the main reference voltage node Ngama_m(2). Alternatively, the main sampling node Nsample_m(1) can also be set close to the main reference voltage node Ngama_m(1). That is, the amount of resistance between the main sampling node Nsample_m(1) and the main reference voltage node Ngama_m(1) is smaller than the amount of resistance between the main sampling node Nsample_m(1) and the main reference voltage node Ngama_m(2). Alternatively, the main sampling node Nsample_m(1) may be arranged close to the main reference voltage node Ngama_m(2). That is, the resistance between the main sampling node Nsample_m(1) and the main reference voltage node Ngama_m(1) is greater than the resistance between the main sampling node Nsample_m(1) and the main reference voltage node Ngama_m(2).

S1403, receiving at least two gamma reference voltages VGMA(1)-VGMA(j) via at least two main reference voltage nodes Ngama_m(1)-Ngama_m(j).

Specifically, as shown in the embodiment of FIG3 , four main reference voltage nodes Ngama_m(1) to Ngama_m(4) are provided on the main resistor string 121a, and the main reference voltage nodes Ngama_m(1) to Ngama_m(4) can be used to receive corresponding gamma reference voltages VGMA(1) to VGMA(4), respectively.

S1404 , electrically connecting the input and output of each sampling module 123 a to the corresponding primary sampling nodes Nsample_m( 1 ) to Nsample_m(g) on the primary resistor string 121 .

Specifically, as shown in the embodiment of FIG3 , three main sampling nodes Nsample_m(1) to Nsample_m(3) are provided on the main resistor string 121a, and a sampling module 123a is provided on each main sampling node Nsample_m(1) to Nsample_m(3). The input and output of each sampling module 123a are electrically connected to the corresponding main sampling node.

S1405, by voltage splitting, the at least two gamma reference voltages VGMA(1)-VGMA(j) received by the main reference voltage nodes Ngama_m(1)-Ngama_m(j) generate a plurality of different gamma voltages VGR(1)-VGR(k) on the main resistor string 121, and the plurality of gamma voltages VGR(1)-VGR(k) are output to the plurality of data drivers 110.

Specifically, in the embodiment shown in FIG3 , 256 main voltage dividing nodes N_m(1) to N_m(256) are provided on the main resistor string 121a, and the main voltage dividing nodes N_m(1) to N_m(256) respectively provide corresponding gamma voltages VGR(1) to VGR(256).

S1406, within a display period Td, when the sampling module 123a operates in the sampling phase Ts, the sampling module 123a samples the voltages of the electrically connected main sampling nodes Nsample_m(1)~Nsample_m(h) to obtain the sampled voltages of the corresponding main sampling nodes Nsample_m(1)~Nsample_m(h).

S1407, within the same display period Td, when the sampling module 123a operates in the holding phase Th, the sampling module 123a outputs the sampled voltage to the corresponding main sampling nodes Nsample_m(1)~Nsample_m(h) to clamp the voltage of the main sampling nodes Nsample_m(1)~Nsample_m(h) to the sampled voltage level.

In at least one embodiment of the present application, the duration of a display period Td is equal to the sum of the durations of the sampling phase Ts and the holding phase Th.

S1408, within the same display period Td, the data driver circuit 100 outputs the driving voltage Sout to the corresponding data lines D1-Dm in the driving phase T2.

In at least one embodiment of the present invention, the gamma voltage generator 120 can sequentially operate in the non-driving phase T1 and the driving phase T2 within the same display period Td. The duration of the non-driving phase T1 is shorter than the duration of the sampling phase Ts. That is, when the data driver 110 switches from the non-driving phase T1 to the driving phase T2, the gamma voltage generator 120 remains in the sampling phase Ts and switches to the holding phase Th after a delay time Tc. In other embodiments, the duration of the non-driving phase T1 is equal to the duration of the sampling phase Ts.

In the above-mentioned gamma voltage generation method, by performing a sampling operation in the sampling phase Ts and clamping the voltage of the corresponding main sampling nodes Nsample_m(1) to Nsample_m(h) in the holding phase Th, the sampling voltage level obtained in the sampling phase Ts can be prevented from being disturbed by other circuits in the system (e.g., circuits in the data driver 110). This improves the recovery speed of the internal voltage of the data driver 110 and allows the target voltage level to be reached more quickly. At the same time, the sampling module 123a performs sampling/holding on the main sampling nodes Nsample_m(1) to Nsample_m(h) on the main resistor string 121, thereby reducing the number of gamma reference voltages VGMA(1) to VGMA(j), thereby reducing the wiring space of the gamma voltage generator 120. In addition, by designing the gamma voltage generator 120 such that the number of sampling modules 123a is less than the number of gamma voltages VGR(1) to VGR(k), the area occupied by the gamma voltage generator 120 in the data driver circuit 100 can be further reduced.

Please refer to Figure 15, which is a flow chart of a gamma voltage generation method according to a second embodiment. In this embodiment, the gamma voltage generation method can be applied to a data driver circuit 100. The data driver circuit 100 may include more or less hardware or software than shown in Figures 9 to 12, or a different component arrangement. It is understood that the implementation of the gamma voltage generation method is not limited to application to the data driver circuit 100 shown in Figures 9 to 12. The gamma voltage generation method is described with reference to the figures for ease of explanation only. The gamma voltage generation method includes the following steps:

S1501, provide at least one main resistor string 121, at least one pre-stage resistor string 122, and at least one sampling module 123b.

The main resistor string 121 includes a plurality of resistors connected in series, forming a plurality of main voltage divider nodes N_m(1) to N_m(k). The plurality of main voltage divider nodes are used to output gamma voltages VGR(1) to VGR(k). The pre-stage resistor string 122 includes a plurality of resistors connected in series, forming a plurality of pre-stage voltage divider nodes N_f(1) to N_f(k). Specifically, as shown in the embodiment of FIG10 , the main resistor string 121 and the pre-stage resistor string 122 have corresponding node configurations. For example, the main voltage divider node N_m(1) of the main resistor string 121 corresponds to the pre-stage voltage divider node N_f(1) of the pre-stage resistor string 122, and the main voltage divider node N_m(p) of the main resistor string 121 corresponds to the pre-stage voltage divider node N_f(p) of the pre-stage resistor string 122.

S1502, at least two main reference voltage nodes Ngama_m(1) to Ngama_m(j) and at least one main sampling node Nsample_m(1) to Nsample_m(h) are set on the main resistor string 121, and at least two pre-stage reference voltage nodes Ngama_f(1) to Ngama_f(j) and at least one pre-stage sampling node Nsample_f(1) to Nsample_f(h) are correspondingly set on the pre-stage resistor string 122.

As shown in Figure 10, a portion of the multiple main voltage divider nodes N_m(1) to N_m(k) can also serve as main reference voltage nodes Ngama_m(1) to Ngama_m(j), and another portion of the multiple main voltage divider nodes N_m(1) to N_m(k) can also serve as main sampling nodes Nsample_m(1) to Nsample_m(h). The main reference voltage nodes Ngama_m(1) to Ngama_m(j) receive the corresponding gamma reference voltages VGMA(1) to VGMA(j).

A portion of the plurality of front-stage voltage divider nodes N_f(1) to N_f(k) can also serve as front-stage reference voltage nodes Ngama_f(1) to Ngama_f(j), and another portion of the plurality of front-stage voltage divider nodes N_f(1) to N_f(k) can also serve as front-stage sampling nodes Nsample_f(1) to Nsample_f(h). The front-stage reference voltage nodes Ngama_f(1) to Ngama_f(j) receive corresponding gamma reference voltages VGMA(1) to VGMA(j). The front-stage sampling nodes Nsample_f(1) to Nsample_f(h) are used to provide corresponding sampling voltages to the corresponding sampling modules 123b.

S1503, receiving corresponding gamma reference voltages VGMA(1)-VGMA(j) via at least two main reference voltage nodes Ngama_m(1)-Ngama_m(j) of the main resistor string 121 and at least two pre-stage reference voltage nodes Ngama_f(1)-Ngama_f(j) of the pre-stage resistor string 122.

Specifically, in the embodiment shown in FIG10 , four main reference voltage nodes Ngama_m(1) to Ngama_m(4) are provided on the main resistor string 121, and four pre-stage reference voltage nodes Ngama_f(1) to Ngama_f(4) are provided on the pre-stage resistor string 122. The main reference voltage nodes Ngama_m(1) to Ngama_m(4) are electrically connected to the corresponding pre-stage reference voltage nodes Ngama_f(1) to Ngama_f(4), and are used to receive the corresponding gamma reference voltages VGMA(1) to VGMA(4), respectively.

S1504, electrically connect the input end of the sampling module 123b to the pre-stage sampling nodes Nsample_f(1)~Nsample_f(g) on the pre-stage resistor string 122, and electrically connect the output end of the sampling module 123b to the corresponding main sampling nodes Nsample_m(1)~Nsample_m(g) on the main resistor string 121.

Specifically, in the embodiment shown in FIG10 , three main sampling nodes Nsample_m(1) to Nsample_m(3) are provided on the main resistor string 121, three pre-stage sampling nodes Nsample_f(1) to Nsample_f(3) are provided on the pre-stage resistor string 122, and a sampling module 123b is provided between each of the main sampling nodes Nsample_m(1) to Nsample_m(3) and the corresponding pre-stage sampling nodes Nsample_f(1) to Nsample_f(3). The input terminals of these sampling modules 123b are electrically connected to the corresponding pre-stage sampling nodes Nsample_f(1) to Nsample_f(3), and the output terminals of these sampling modules 123b are electrically connected to the corresponding main sampling nodes Nsample_m(1) to Nsample_m(3).

S1505, by voltage splitting, the at least two gamma reference voltages VGMA(1)-VGMA(j) received by the main reference voltage nodes Ngama_m(1)-Ngama_m(j) generate a plurality of different gamma voltages VGR(1)-VGR(k) on the main resistor string 121, and the plurality of gamma voltages VGR(1)-VGR(k) are output to the plurality of data drivers 110.

Specifically, in the embodiment shown in FIG10 , 256 main voltage dividing nodes N_m(1) to N_m(256) are provided on the main resistor string 121, and the main voltage dividing nodes N_m(1) to N_m(256) respectively provide corresponding gamma voltages VGR(1) to VGR(256).

S1506, within a display period Td, when the sampling module 123b operates in the sampling phase Ts, the sampling module 123b samples the voltage of the electrically connected previous sampling nodes Nsample_f(1)~Nsample_f(h) to obtain the sampling voltage of the corresponding previous sampling nodes Nsample_f(1)~Nsample_f(h).

S1507, within the same display period Td, when the sampling module 123b operates in the holding phase Th, the sampling module 123b continues to sample the front-stage sampling nodes Nsample_f(1) to Nsample_f(h), and outputs the sampled voltages of the front-stage sampling nodes Nsample_f(1) to Nsample_f(h) to the corresponding main sampling nodes Nsample_m(1) to Nsample_m(h), so as to clamp the voltages of the main sampling nodes Nsample_m(1) to Nsample_m(h) to the level of the sampled voltages of the front-stage sampling nodes Nsample_f(1) to Nsample_f(h).

In at least one embodiment of the present application, the duration of a display period Td is equal to the sum of the durations of the sampling phase Ts and the holding phase Th.

S1508: Within the same display period Td, the data driver circuit 100 outputs the driving voltage Sout to the data lines D1-Dm.

In at least one embodiment of the present invention, within the same display period Td, the data-driven circuit 100 can sequentially operate in a non-driving phase T1 and a driving phase T2. The duration of the non-driving phase T1 is shorter than the duration of the sampling phase Ts. That is, when the data-driven circuit 100 switches from the non-driving phase T1 to the driving phase T2, the gamma voltage generator 120 remains in the sampling phase Ts and, after a delay time Tc, switches to the holding phase Th. In other embodiments, the duration of the non-driving phase T1 is equal to the duration of the sampling phase Ts.

In the above-mentioned gamma voltage generation method, the sampling module 123b continuously performs sampling operations in the sampling phase Ts and the holding phase Th, and clamps the voltage of the corresponding main sampling nodes Nsample_m(1) to Nsample_m(h) to the sample voltage level obtained in the sampling phase Ts during the holding phase Th. This can prevent other circuits in the system (such as circuits in the data driver 110) from disturbing the voltage of the main sampling nodes Nsample_m(1) to Nsample_m(h), thereby improving the recovery speed of the internal voltage of the data driver 110 and achieving the target voltage level more quickly. At the same time, within a display period Td, the sampling module 123b samples the pre-stage sampling nodes Nsample_f(1) to Nsample_f(h) on the pre-stage resistor string 122 in real time, and clamps the voltage of the main sampling nodes Nsample_m(1) to Nsample_m(h) during the hold phase Th, thereby reducing the number of gamma reference voltages VGMA(1) to VGMA(j), thereby reducing the wiring space of the gamma voltage generator 120. In addition, the gamma voltage generator 120 can further reduce the area occupied by the gamma voltage generator 120d in the data driving circuit 100 by setting the number of sampling modules 123b to be less than the number of gamma reference voltage nodes VGMA(1) to VGMA(j). Finally, by adding the pre-stage resistor string 122, the circuit structure of the sampling module 123b is simplified, allowing the sampling module 123b to directly clamp the main sampling nodes Nsample_m(1)-Nsample_m(h) to the sampling voltage via the voltage divider on the pre-stage resistor string 122. This reduces the number of electronic components in the sampling module 123b (i.e., omitting the third transistor Q3, the fourth transistor Q4, and the holding capacitor C), making it applicable to gamma voltage generators 120 with different structures.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of this application, rather than to limit them. Although this application has been described in detail with reference to the above embodiments, ordinary technical personnel in this field should understand that they can still modify the technical solutions described in the above embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

In summary, this application meets the patent application requirements and is hereby filed in accordance with the law. However, the foregoing description represents only the preferred embodiment of this application. Equivalent modifications or variations made by persons skilled in the art and in accordance with the spirit of this invention should be included within the scope of the patent application below.

1: Display device 101: Display area 103: Non-display area 100: Data driver circuit 200: Scan driver circuit 300: Timing control circuit S1-Sn: Scan lines D1-Dn: Data lines 20: Pixel unit DATA: Image data 110: Data driver 120, 120a, 120b, 120c, 120d: Gamma voltage generator 111: Shift register module 112: Data lock module 113: Potential shift module 114: Digital-to-analog conversion module 115: Output buffer module VGR(1)~VGR(k): Gamma voltage N_m(1)~N_m(k): Main voltage divider node Nsample_m(1)~Nsample_m(h): Main sampling node VGMA(1)~VGMA(j): Gamma reference voltage Ngama_m(1)~Ngama_m(j): Main reference voltage node Ngama_f(1)~Ngama_f(j): Pre-stage main reference voltage node N_f(1)~N_f(k): Pre-stage voltage divider node Nsample_f(1)~Nsample_f(h): Pre-stage sampling node VGR(target): Target gamma voltage Sout: Drive voltage 121, 121a, 121b, 121c, 121d: Main resistor string 122: Pre-stage resistor string 123a, 123b: Sampling module OP1: Operational amplifier Q1: First transistor Q2: Second transistor Q3: Third transistor Q4: Fourth transistor C: Holding capacitor HSPB: First control signal HSP: Second control signal Td: Display period T1: Non-driving phase T2: Driving phase Ts: Sampling phase Th: Holding phase Tc: Delay time S1401-S1408, S1501-S1508: Steps

FIG1 is a schematic diagram of a module of a display device according to a preferred embodiment of the present application.

Figure 2 is a schematic diagram of the data drive circuit module in Figure 1.

FIG3 is a schematic diagram of a module of the gamma voltage generator of the first embodiment shown in FIG2.

FIG4 is a schematic diagram of a module of the gamma voltage generator of the second embodiment shown in FIG2.

FIG5 is a schematic diagram of a module of the gamma voltage generator of the third embodiment shown in FIG2.

FIG6 is a schematic circuit diagram of the sampling module in FIG3 to FIG5 when it is in the sampling stage.

FIG7 is a schematic diagram of the circuit when the sampling module in FIG3 to FIG5 is in the holding phase.

FIG8 is a timing diagram showing the driving signal, the main sampling node, the output of the digital-to-analog conversion module, the output of the output buffer module, and the first control signal in FIG2.

FIG9 is a schematic diagram of a module of the data drive circuit of the fourth embodiment in FIG1.

FIG10 is a schematic circuit diagram of the gamma voltage generator in FIG9 .

FIG11 is a circuit diagram of the sampling module in FIG10 when it is in the sampling stage.

FIG12 is a circuit diagram of the sampling module in FIG10 when it is in the holding phase.

FIG13 is a timing diagram showing the driving signal, the main sampling node, the output of the digital-to-analog conversion module, the output of the output buffer module, and the first control signal in FIG9.

FIG14 is a flow chart of a gamma voltage generating method according to the first embodiment.

FIG15 is a flow chart of a gamma voltage generating method according to a second embodiment.

120: Gamma voltage generator

123a: Sampling Module

110: Data drive

111: Shift temporary module

112: Data Lock Module

113: Potential Shift Module

114: Digital-to-analog conversion module

115: Output buffer module

121: Main resistor string

VGMA(1)~VGMA(j):Gamma reference voltage

N_m(1)~N_m(k): Main voltage divider node

VGR(1)~VGR(k):Gamma voltage

VGR(target): Target gamma voltage

Sout: driving voltage

Di: data line

DATA: Image data

Claims (14)

A gamma voltage generator comprises: At least one main resistor string having multiple main voltage divider nodes for outputting different gamma voltages; at least two of the main voltage divider nodes also serve as main reference voltage nodes for receiving a gamma reference voltage, and at least one of the main voltage divider nodes also serves as a main sampling node; wherein the main voltage divider nodes at different locations serve as the main reference voltage nodes and the main sampling nodes, respectively, and the number of the main sampling nodes is less than the number of the main voltage divider nodes; at least one main sampling node is disposed between any two adjacent main reference voltage nodes; and At least one sampling module corresponds to the at least one main sampling node and is electrically connected to the corresponding main sampling node; wherein the input and output of the same sampling module are electrically connected to the corresponding main sampling node; the sampling module is used to sample the voltage of the corresponding main sampling node to obtain a sampled voltage and clamp the voltage of the main sampling node to the sampled voltage level. The gamma voltage generator of claim 1, wherein, within a display cycle, the sampling module operates sequentially in a sampling phase and a holding phase; in the sampling phase, the sampling module samples the voltage of the corresponding main sampling node to obtain a sampled voltage and stores the sampled voltage internally; in the holding phase, the sampling module provides the stored sampled voltage to the corresponding main sampling node to clamp the voltage of the corresponding main sampling node to the level of the sampled voltage. The gamma voltage generator of claim 2, wherein, within a display cycle, a data driver electrically connected to the gamma voltage generator operates in a non-driving phase and a driving phase sequentially; wherein the duration of the non-driving phase is less than or equal to the duration of the sampling phase. The gamma voltage generator of claim 2, wherein the sampling module comprises an operational amplifier, a first transistor, a second transistor, a third transistor, a fourth transistor, and a holding capacitor; a control terminal of the first transistor receives a first control signal, a first connection terminal of the first transistor is electrically connected to the output terminal of the operational amplifier, and a second connection terminal of the first transistor is electrically connected to the corresponding main sampling node; a control terminal of the second transistor receives a second control signal, a first connection terminal of the second transistor is electrically connected to the output terminal of the operational amplifier, and a second connection terminal of the second transistor is electrically connected to the corresponding main sampling node; The control terminal of the transistor receives the first control signal, the first connection terminal of the third transistor is electrically connected to the positive input terminal of the operational amplifier, and the second connection terminal of the third transistor is electrically connected to the corresponding main sampling node; the control terminal of the fourth transistor receives the second control signal, the first connection terminal of the fourth transistor is electrically connected to the positive input terminal of the operational amplifier, and the second connection terminal of the fourth transistor is electrically connected to the corresponding main sampling node; one end of the holding capacitor is electrically connected to the positive input terminal of the operational amplifier, and the other end is grounded; the inverting input terminal of the operational amplifier is electrically connected to the output terminal of the operational amplifier. The gamma voltage generator of claim 4, wherein the first control signal is used to control the cutoff and conduction of the first transistor and the third transistor, and the second control signal is used to control the cutoff and conduction of the second transistor and the fourth transistor, and the first control signal and the second control signal are inverse signals of each other; During the sampling phase, the first transistor and the second transistor are cut off, and the third transistor and the fourth transistor are turned on, thereby establishing a signal path between the main sampling node and the positive input terminal of the operational amplifier and the holding capacitor; the holding capacitor stores the sampled voltage; During the hold phase, the first and second transistors are turned on, and the third and fourth transistors are turned off, thereby establishing a signal path between the main sampling node and the output terminal of the operational amplifier. The sampled voltage stored on the hold capacitor is provided to the main sampling node via the output terminal of the operational amplifier, thereby clamping the voltage of the main sampling node to the sampled voltage level. The gamma voltage generator of claim 1, wherein the same number of the main sampling nodes and the corresponding sampling modules electrically connected to each main sampling node are arranged between any two adjacent main reference voltage nodes. The gamma voltage generator of claim 1, wherein a predetermined number of resistors are provided between any two adjacent ones of the plurality of the main sampling nodes and the plurality of the main reference voltage nodes. A data driver circuit includes a plurality of data drivers and a gamma voltage generator; each data driver is configured to output a driving voltage to a corresponding data line based on a gamma voltage output from the gamma voltage generator; wherein the gamma voltage generator is a gamma voltage generator as described in any one of claims 1 to 7. A gamma voltage generation method is provided for use in a data-driven circuit; the data-driven circuit includes multiple data drivers and a gamma voltage generator. The gamma voltage generation method comprises the following steps: Providing at least one main resistor string and at least one sampling module electrically connected to the main resistor string; Disposing at least two main reference voltage nodes and at least one main sampling node on the main resistor string; Receiving at least two corresponding gamma reference voltages via the at least two main reference voltage nodes; Electrically connecting the input and output of each sampling module to the same main sampling node on the main resistor string; By voltage splitting, the at least two gamma reference voltages received by the at least two main reference voltage nodes generate a plurality of different gamma voltages across the main resistor string, and the plurality of gamma voltages are output to the plurality of data drivers. During a display cycle, when the sampling module operates in a sampling phase, the sampling module samples the voltage of the electrically connected main sampling node to obtain a sampled voltage of the corresponding main sampling node. During the same display cycle, when the sampling module operates in a holding phase, the sampling module outputs the sampled voltage to the corresponding main sampling node to clamp the voltage of the main sampling node to the sampled voltage level. The gamma voltage generation method of claim 9, further comprising: During the same display cycle, the data driver sequentially operates in a non-driving phase and a driving phase; the duration of the non-driving phase is less than or equal to the duration of the sampling phase. The gamma voltage generation method as described in claim 9, wherein the sampling module includes an operational amplifier, a first transistor, a second transistor, a third transistor, a fourth transistor, and a holding capacitor; the control terminal of the first transistor receives a first control signal, the first connection terminal of the first transistor is electrically connected to the output terminal of the operational amplifier, and the second connection terminal of the first transistor is electrically connected to the corresponding main sampling node; the control terminal of the second transistor receives a second control signal, the first connection terminal of the second transistor is electrically connected to the output terminal of the operational amplifier, and the second connection terminal of the second transistor is electrically connected to the corresponding main sampling node; the third transistor receives a second control signal, the first connection terminal of the second transistor is electrically connected to the output terminal of the operational amplifier, and the second connection terminal of the second transistor is electrically connected to the corresponding main sampling node; The control terminal of the transistor receives the first control signal, the first connection terminal of the third transistor is electrically connected to the positive input terminal of the operational amplifier, and the second connection terminal of the third transistor is electrically connected to the corresponding main sampling node; the control terminal of the fourth transistor receives the second control signal, the first connection terminal of the fourth transistor is electrically connected to the positive input terminal of the operational amplifier, and the second connection terminal of the fourth transistor is electrically connected to the corresponding main sampling node; one end of the holding capacitor is electrically connected to the positive input terminal of the operational amplifier, and the other end is grounded; the inverting input terminal of the operational amplifier is electrically connected to the output terminal of the operational amplifier. The gamma voltage generation method of claim 11, wherein the first control signal is used to control the cutoff and conduction of the first transistor and the third transistor, and the second control signal is used to control the cutoff and conduction of the second transistor and the fourth transistor, and the first control signal and the second control signal are inverse signals of each other; During the sampling phase, the first transistor and the second transistor are cut off, and the third transistor and the fourth transistor are turned on to establish a signal path between the main sampling node and the positive input terminal of the operational amplifier and the holding capacitor; the holding capacitor stores the sampled voltage; and During the hold phase, the first and second transistors are turned on, and the third and fourth transistors are turned off, thereby establishing a signal path between the main sampling node and the output terminal of the operational amplifier. The sampled voltage stored on the hold capacitor is provided to the main sampling node via the output terminal of the operational amplifier, thereby clamping the voltage of the main sampling node to the sampled voltage level. The gamma voltage generating method as described in claim 9, wherein the same number of the main sampling nodes and the corresponding sampling modules electrically connected to each of the main sampling nodes are arranged between any two adjacent main reference voltage nodes. The gamma voltage generating method as described in claim 9, wherein a predetermined number of resistors are provided between any two adjacent ones of the plurality of the main sampling nodes and the plurality of the main reference voltage nodes.