TWI893531B - Dual system server - Google Patents

Abstract

A dual system server includes: a central processing unit, a first baseboard management controller, a second baseboard management controller and a complex programmable logic device. The first baseboard management controller is connected to the central processing unit through a first peripheral component interconnect express interface. The second baseboard management controller is connected to the central processing unit through a second peripheral component interconnect express interface. The complex programmable logic device is connected to the first baseboard management controller through a first inter-integrated circuit interface, and is connected to the second baseboard management controller through a second inter-integrated circuit interface.

Description

Dual-system server

The present invention relates to a dual-system server.

Most current servers use dual sockets, connected via an ultra-path interconnect (UPI). However, this architecture is costly and can easily cause the entire system to malfunction if one socket fails.

In view of the above, the present invention provides a dual-system server that solves the above problems.

According to one embodiment of the present invention, a dual-system server includes a central processing unit (CPU), a first baseboard management controller (BMC), a second BMC, and a complex programmable logic device (CPLD). The first BMC is connected to the CPU via a first QPI (Quick Peripheral Component Interconnect) interface. The second BMC is connected to the CPU via a second QPI (Quick Peripheral Component Interconnect) interface. The CPL is connected to the first BMC via a first IIC interface and to the second BMC via a second IIC interface.

In summary, the dual-system server according to one or more embodiments of the present invention can realize the architecture of two single-channel servers on one motherboard and can be compatible with the functions of the dual systems at the same time, thereby reducing the cost of the server.

The above description of the present disclosure and the following description of the embodiments are intended to demonstrate and explain the spirit and principles of the present invention, and to provide further explanation of the scope of the patent application of the present invention.

The following detailed description of the features and advantages of the present invention is sufficient to enable anyone skilled in the relevant art to understand the technical content of the present invention and implement it accordingly. Based on the disclosure, patent application scope, and drawings in this specification, anyone skilled in the relevant art can easily understand the relevant objectives and advantages of the present invention. The following examples are intended to further illustrate the concepts of the present invention in detail and are not intended to limit the scope of the present invention in any way.

Please refer to FIG1 , which is a block diagram of a dual-system server according to a first embodiment of the present invention. As shown in FIG1 , the dual-system server 1 includes a central processing unit 10 , a first baseboard management controller 11 , a second baseboard management controller 12 , and a complex programmable logic device 13 .

The first baseboard management controller 11 is connected to the central processing unit 10 via a first express peripheral component interconnect interface 101. The second baseboard management controller 12 is connected to the central processing unit 10 via a second express peripheral component interconnect interface 102. The complex programmable logic device 13 is connected to the first baseboard management controller 11 via a first inter-IC interface 103 and to the second baseboard management controller 12 via a second inter-IC interface 104.

The first BMC 11 and the second BMC 12 are preferably of the same model. In the architecture of Figure 1 , the first BMC 11 and the second BMC 12 can each access the CPU 10 . This architecture allows for two single-socket servers on a single motherboard, while maintaining dual-system functionality and reducing server costs.

The complex programmable logic device 13 is further connected to the fan controller A1. The complex programmable logic device 13 may include multiple registers for storing the fan's pulse width modulation (PWM) values. The complex programmable logic device 13 can determine the maximum fan speed based on the PWM values in the registers. Furthermore, the complex programmable logic device 13 can control the fan at a safe speed if it cannot read either the first integrated circuit interface 103 or the second integrated circuit interface 104. In other words, the complex programmable logic device 13 can detect the first integrated circuit interface 103 and the second integrated circuit interface 104. If the complex programmable logic device 13 fails to detect either the first integrated circuit interface 103 or the second integrated circuit interface 104, it may indicate that the corresponding baseboard management controller has failed. Therefore, the complex programmable logic device 13 can output a safe speed to the fan controller A1 to control the fan to operate at the safe speed. This ensures that the system fans operate normally and prevents false freezes caused by abnormal conditions (such as excessive temperature).

Please refer to Figure 2, which is a block diagram of a dual-system server according to a second embodiment of the present invention. As shown in Figure 2, the dual-system server 2 includes a central processing unit 20, a first baseboard management controller 21, a second baseboard management controller 22, a complex programmable logic device 23, and a demultiplexer chip 24.

The first baseboard management controller 21 is connected to the central processing unit 20 via a first express peripheral component interconnect interface 201. The second baseboard management controller 22 is connected to the central processing unit 20 via a second express peripheral component interconnect interface 202. The complex programmable logic device 23 is connected to the first baseboard management controller 21 via a first inter-IC interface 203 and to the second baseboard management controller 22 via a second inter-IC interface 204. The demultiplexer 24 can be connected to the first baseboard management controller 21, the second baseboard management controller 22, and the complex programmable logic device 23.

The CPU 20, first BMC 21, second BMC 22, and complex programmable logic device 23 of the dual-system server 2 are respectively the same as the CPU 10, first BMC 11, second BMC 12, and complex programmable logic device 13 of the dual-system server 1 in FIG. 1 , and therefore are not described in detail here.

Demultiplexer 24 is used to allow communication between one of first and second integrated circuit interfaces 203 and 204, and to prevent communication between the other. In other words, if first inter-IC interface 203 is the interface permitted to communicate, demultiplexer 24 can function as an arbitration element, allowing communication between first inter-IC interface 203 and preventing second inter-IC interface 204 from communicating while first inter-IC interface 203 is communicating. For example, demultiplexer 24 can be a PCA9641.

Please refer to Figure 3, which is a block diagram of a dual-system server according to a third embodiment of the present invention. As shown in Figure 3, the dual-system server 3 includes a central processing unit 30, a first baseboard management controller 31, a second baseboard management controller 32, a complex programmable logic device 33, a low-profile connector 34, a signal connector 35, a first M.2 connector 36, a second M.2 connector 37, and a temperature sensor 38.

The first baseboard management controller 31 is connected to the central processing unit 30 via a first express peripheral component interconnect interface 301. The second baseboard management controller 32 is connected to the central processing unit 30 via a second express peripheral component interconnect interface 302. The complex programmable logic device 33 is connected to the first baseboard management controller 31 via a first inter-IC interface 303 and to the second baseboard management controller 32 via a second inter-IC interface 304.

The CPU 30, first BMC 31, second BMC 32, and complex programmable logic device 33 of the dual-system server 3 are respectively the same as the CPU 10, first BMC 11, second BMC 12, and complex programmable logic device 13 of the dual-system server 1 in FIG. 1 , and therefore are not described in detail here.

As shown in Figure 3, the dual-system server 3 further includes a motherboard 300A. A CPU 30, a first baseboard management controller 31, a second baseboard management controller 32, a complex programmable logic device 33, a low-profile connector 34, and a signal connector 35 may all be located on the motherboard 300A. The low-profile connector 34 may be a J3 connector, and the signal connector 35 may be a J4 connector, both of which may be sideband connectors on the motherboard 300A. Furthermore, the dual-system server 3 further includes an M.2 backplane 300B, and a first M.2 connector 36 and a second M.2 connector 37 located on the M.2 backplane 300B.

The M.2 backplane 300B is connected to the motherboard 300A. The low-profile connector 34 is connected to the first M.2 connector 36 and the second M.2 connector 37. The signal connector 35 is connected to the first M.2 connector 36 and the second M.2 connector 37. For example, the low-profile connector 34 and the signal connector 35 can be connected to the first M.2 connector 36 and the second M.2 connector 37, respectively, via a Y-shaped cable. The first M.2 connector 36 and the second M.2 connector 37 can each be connected to an M.2 hard drive, which can be used to store the boot system. Furthermore, the first M.2 connector 36 and the second M.2 connector 37 can support the Peripheral Component Interconnect Gen5 standard and each can have four slots.

In other words, signals generated by components on the motherboard 300A (e.g., the first baseboard management controller 31 and the second baseboard management controller 32) can be output to the first M.2 connector 36 and the second M.2 connector 37 via the low-profile connector 34 and the signal connector 35. This allows them to control the M.2 hard drives connected to them (e.g., power on). Specifically, the low-profile connector 34 transmits quick peripheral component interconnect signals, a standby voltage (e.g., 3.3 volts), a detection signal for detecting the presence of an M.2 hard drive, and a clock signal to the first and second M.2 connectors 36 and 37, respectively. This architecture ensures that even if one M.2 connector experiences a problem, the other can still operate normally.

The temperature sensor 38 of the dual-system server 3 is installed on the M.2 backplane 300B and connected to the signal connector 35. The temperature sensor 38 can be used to sense the temperature of the M.2 backplane 300B. For example, the temperature sensor 38 can be used to sense the temperature of the first M.2 connector 36, the second M.2 connector 37, and/or the temperature of the M.2 hard drives connected to the first and second M.2 connectors 36 and 37. Furthermore, the sensing results of the temperature sensor 38 can be transmitted to the first and second baseboard management controllers 31 and 32 via the signal connector 35.

In addition, a field replacement unit (FRU) may be provided on the motherboard 300A and connected to the M.2 backplane 300B. The FRU may transmit information about the M.2 backplane 300B (e.g., the serial number of the M.2 backplane 300B) to the motherboard 300A.

Please refer to Figure 4, which is a block diagram of a dual-system server according to a fourth embodiment of the present invention. As shown in Figure 4, the dual-system server 4 includes a central processing unit 40, a first baseboard management controller 41, a second baseboard management controller 42, a complex programmable logic device 43, a thin connector 44, a first network port connector 45, and a second network port connector 46.

The first baseboard management controller 41 is connected to the central processing unit 40 via a first quick peripheral component interconnect interface 401. The second baseboard management controller 42 is connected to the central processing unit 40 via a second quick peripheral component interconnect interface 402. The complex programmable logic device 43 is connected to the first baseboard management controller 41 via a first inter-IC interface 403 and to the second baseboard management controller 42 via a second inter-IC interface 404.

The CPU 40, first BMC 41, second BMC 42, and complex programmable logic device 43 of the dual-system server 4 are respectively the same as the CPU 10, first BMC 11, second BMC 12, and complex programmable logic device 13 of the dual-system server 1 in FIG. 1 , and therefore are not described in detail here.

The first baseboard management controller 41 and the second baseboard management controller 42 can be connected to a thin connector 44, such as a J1 connector. The thin connector 44 is further connected to a first network port connector 45 and a second network port connector 46, respectively. The first network port connector 45 and the second network port connector 46 can be dual-port J2 network port connectors. The first network port connector 45 and the second network port connector 46 can each be an RJ45 network port connector.

The first and second network port connectors 45 and 46 can output their respective network port speeds to the thin connector 44. The network port speeds can then be transmitted to the first and second baseboard management controllers 41 and 42 via the thin connector 44. For example, the thin connector 44 can transmit the network port speed to the field replaceable unit (FRU) described above, and the FRU can transmit the network port speed to the first and second baseboard management controllers 41 and 42.

Furthermore, the thin connector 44 is further connected to the third network port connector. The third network port connector can be a single-port connector like J2. The third network port connector can be an RJ45 network port connector. Furthermore, the thin connector 44 can perform bidirectional communication with the first network port connector 45, the second network port connector 46, and the third network port connector, respectively, such as transmitting medium-dependent interface (MDI) signals. This architecture allows for compatibility with both single-node and dual-node network port functions, effectively reducing the design cost of dual-system servers.

Please refer to Figure 5, which is a block diagram of a dual-system server according to a fifth embodiment of the present invention. As shown in Figure 5, the dual-system server 5 includes a central processing unit 50, a first baseboard management controller 51, a second baseboard management controller 52, a complex programmable logic device 53, a first connector 54, a second connector 55, a third connector 56, a fourth connector 57, a temperature sensor 58, and a field replaceable unit 59.

The first baseboard management controller 51 is connected to the central processing unit 50 via a first quick peripheral component interconnect interface 501. The second baseboard management controller 52 is connected to the central processing unit 50 via a second quick peripheral component interconnect interface 502. The complex programmable logic device 53 is connected to the first baseboard management controller 51 via a first inter-IC interface 503 and to the second baseboard management controller 52 via a second inter-IC interface 504.

The CPU 50, first BMC 51, second BMC 52, and complex programmable logic device 53 of the dual-system server 5 are respectively the same as the CPU 10, first BMC 11, second BMC 12, and complex programmable logic device 13 of the dual-system server 1 in FIG. 1 , and therefore are not described in detail here.

As shown in Figure 5, the dual-system server 5 further includes a mainboard 500A and an earboard 500B. The CPU 50, the first baseboard management controller 51, the second baseboard management controller 52, the complex programmable logic device 53, the first connector 54, and the second connector 55 can be collectively arranged on the mainboard 500A. The first connector 54 through the fourth connector 57 can be collectively arranged on the earboard 500B and can be soldered to the earboard 500B using an on-board cable. The first connector 54 is connected to the second connector 55, the temperature sensor 58, and the field-replaceable unit 59. The second connector 55 is connected to the third connector 56 and the display A2, and the third connector 56 is connected to the fourth connector 57. In addition, the field-replaceable unit 59 is further connected to the first baseboard management controller 51 and the second baseboard management controller 52. By placing the first to fourth connectors 54 to 57 on the ear board 500B, the connectors can share one ear board, thereby reducing the cost of the dual-system server.

The first connector 54 to the fourth connector 57 can be J1 connector, J2 connector, J7 connector and J5 connector respectively. For example, the first connector 54 can be an MP connector, the second connector 55 can be a display port, the third connector 56 can be a low-profile connector, and the fourth connector 57 can be a type-C Universal Serial Bus connector. There can be one or two fourth connectors 57.

The first connector 54 enables bidirectional communication with the second connector 55, for example, transmitting video graphic array (VGA) signals. Furthermore, the first connector 54 can also communicate with the second connector 55 to improve integrated circuit interface debugging. The third connector 56 can output communication signals to the second connector 55. The third connector 56 can also be connected to multiple light-emitting diodes, each configured to emit light indicating power status, user identifier (UID), and signal status. The fourth connector 57 enables bidirectional communication with the third connector 56 via the Universal Serial Bus (USB).

The temperature sensor 58 can be used to sense the temperature of the air inlet of the ear plate 500B, and can output the sensed temperature to the first baseboard management controller 51 and the second baseboard management controller 52 via the first connector 54 and the field replaceable unit 59.

Please refer to Figure 6, which is a block diagram of a dual-system server according to a sixth embodiment of the present invention. As shown in Figure 6, the dual-system server 6 includes a central processing unit 60, a first baseboard management controller 61, a second baseboard management controller 62, a complex programmable logic device 63, a first long hard drive 64, a second long hard drive 65, and a short hard drive 66.

The first baseboard management controller 61 is connected to the central processing unit 60 via a first quick peripheral component interconnect interface 601. The second baseboard management controller 62 is connected to the central processing unit 60 via a second quick peripheral component interconnect interface 602. The complex programmable logic device 63 is connected to the first baseboard management controller 61 via a first inter-IC interface 603 and to the second baseboard management controller 62 via a second inter-IC interface 604.

The CPU 60, first BMC 61, second BMC 62, and complex programmable logic device 63 of the dual-system server 6 are respectively the same as the CPU 10, first BMC 11, second BMC 12, and complex programmable logic device 13 of the dual-system server 1 in FIG. 1 , and therefore are not described in detail here.

As shown in FIG6 , the dual-system server 6 further includes a motherboard 600A and a backplane 600B. The central processing unit 60, the first baseboard management controller 61, the second baseboard management controller 62, and the complex programmable logic device 63 can be collectively disposed on the motherboard 600A. A first long hard drive 64, a second long hard drive 65, and a short hard drive 66 can be connected to the backplane 600B, respectively. Specifically, the first long hard drive 64 can be connected to the backplane 600B via a first express peripheral component interconnect interface; the second long hard drive 65 can be connected to the backplane 600B via a second express peripheral component interconnect interface; and the short hard drive 66 can be connected to the backplane 600B via a third express peripheral component interconnect interface. Furthermore, the backplane 600B may include three mini cool edge input/output (MCIO) connectors, which are connected to the first long hard drive 64, the second long hard drive 65, and the short hard drive 66 respectively.

Furthermore, the first and second Express Peripheral Component Interconnect interfaces each correspond to eight slots, and the third Express Peripheral Component Interconnect interface can correspond to four slots. In other words, the first long hard drive 64 and the second long hard drive 65 each connect to the backplane 600B via eight slots on the Express Peripheral Component Interconnect interface, while the short hard drive 66 connects to the backplane 600B via four slots on the Express Peripheral Component Interconnect interface.

The first, second, and third EPI interfaces conform to the Enterprise and Data Center Standard Form Factor (EDSFF) format. The first long hard drive 64, the second long hard drive 65, and the short hard drive 66 can be EDSFF hard drives. For example, the first long hard drive 64 and the second long hard drive 65 can be E3 long drives, and the short hard drive 66 can be E3 short drives.

By using one board to accommodate both long and short hard drives, the cost of dual-system servers can be effectively reduced and resource utilization can be improved.

It should be noted that the dual-system server according to the present invention can be a combination of multiple embodiments from the first embodiment to the sixth embodiment.

In summary, a dual-system server according to one or more embodiments of the present invention can implement an architecture with two single-channel servers on a single motherboard, while also being compatible with dual-system functions, thereby reducing server costs and ensuring the normal operation of system fans, preventing false crashes due to abnormal conditions. The architecture of multiple network port connectors allows for compatibility with both single-node and dual-node network port functions, effectively reducing the design cost of the dual-system server. By arranging multiple connectors on a single lug board, the connectors can share a single lug board, further reducing the cost of the dual-system server. Furthermore, by using a single board to accommodate both long and short hard drive configurations, the cost of the dual-system server can be effectively reduced and resource utilization improved.

Although the present invention is disclosed above with reference to the aforementioned embodiments, they are not intended to limit the present invention. Any modifications and enhancements that do not depart from the spirit and scope of the present invention are within the scope of patent protection of the present invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

1, 2, 3, 4, 5, 6: Dual-system server 10, 20, 30, 40, 50, 60: Central processing unit 11, 21, 31, 41, 51, 61: First baseboard management controller 12, 22, 32, 42, 52, 62: Second baseboard management controller 13, 23, 33, 43, 53, 63: Complex programmable logic device 101, 201, 301, 401, 501, 601: First fast peripheral component interconnect interface 102, 202, 302, 402, 502, 602: Second fast peripheral component interconnect interface 103, 203, 303, 403, 503, 603: First integrated circuit interface 104, 204, 304, 404, 504, 604: Second integrated circuit interface 24: Demultiplexer chip 34, 44: Low-profile connector 35: Signal connector 36: First M.2 connector 37: Second M.2 connector 38, 58: Temperature sensor 45: First network port connector 46: Second network port connector 54: First connector 55: Second connector 56: Third connector 57: Fourth connector 59: Field-replaceable unit 64: First long hard drive 65: Second long hard drive 66: Short hard drive 300A, 500A, 600A: Motherboard 300B, 600B: Backplane 500B: Ear plate A1: Fan controller A2: Monitor

Figure 1 is a block diagram of a dual-system server according to the first embodiment of the present invention. Figure 2 is a block diagram of a dual-system server according to the second embodiment of the present invention. Figure 3 is a block diagram of a dual-system server according to the third embodiment of the present invention. Figure 4 is a block diagram of a dual-system server according to the fourth embodiment of the present invention. Figure 5 is a block diagram of a dual-system server according to the fifth embodiment of the present invention. Figure 6 is a block diagram of a dual-system server according to the sixth embodiment of the present invention.

1: Dual-system server

10: Central Processing Unit

11: First Baseboard Management Controller

12: Second baseboard management controller

13: Complex Programmable Logic Device

101: First Quick Peripheral Component Interconnection Interface

102: Second Quick Peripheral Component Interconnection Interface

103: Interface between first integrated circuits

104: Interface between the second integrated circuits

A1: Fan controller

Claims (10)

A dual-system server includes: a central processing unit (CPU); a first baseboard management controller (BMC) connected to the CPU via a first express peripheral component interconnect (PCI) interface; a second BMC connected to the CPU via a second express peripheral component interconnect (PCI) interface; and a complex programmable logic device (CPLD) connected to the first BMC via a first inter-IC interface and to the second BMC via a second inter-IC interface. The dual-system server of claim 1, wherein the complex programmable logic device is configured to control the fan at a safe speed when either the interface between the first integrated circuit and the interface between the second integrated circuit cannot be read. The dual-system server of claim 1 further comprises: A demultiplexer chip connected to the first baseboard management controller, the second baseboard management controller, and the complex programmable logic device, the demultiplexer chip being configured to enable communication between one of the interfaces between the first integrated circuit and the second integrated circuit, and to disable communication between the other. The dual-system server of claim 1 further comprises: A motherboard, wherein the central processing unit, the first baseboard management controller, the second baseboard management controller, and the complex programmable logic device are disposed on the motherboard; an M.2 backplane connected to the motherboard; a low-profile connector disposed on the motherboard; a signal connector disposed on the motherboard; a first M.2 connector disposed on the M.2 backplane and connected to the low-profile connector and the signal connector; and a second M.2 connector disposed on the M.2 backplane and connected to the low-profile connector and the signal connector, wherein the first M.2 connector and the second M.2 connector support the Peripheral Component Interconnect Gen5 Express standard. The dual-system server as described in claim 4 further includes a temperature sensor connected to the signal connector and used to sense the temperature of at least one of the first M.2 connector and the second M.2 connector. The dual-system server of claim 1 further comprises: A low-profile connector connected to the first baseboard management controller and the second baseboard management controller; a first network port connector connected to the low-profile connector; and a second network port connector connected to the low-profile connector. The dual-system server of claim 1 further comprises: A field replaceable unit (FRU) connected to the first BMC and the second BMC; a first connector connected to the FRU; a second connector connected to the first connector and a display, configured to communicate bidirectionally with the first connector via a video graphics array; a third connector connected to the second connector, configured to output communication signals to the second connector; and a fourth connector connected to the third connector, configured to communicate bidirectionally with the third connector via a USB. The dual-system server as described in claim 7, wherein the second connector is further used to perform an improved integrated circuit interface debugging with the first connector. The dual-system server of claim 7 further comprises: an ear plate, wherein the first connector, the second connector, the third connector, and the fourth connector are disposed on the ear plate; and a temperature sensor connected to the first connector and configured to sense the temperature of the air inlet of the ear plate. The dual-system server as described in claim 1 further comprises: a motherboard, wherein the central processing unit, the first baseboard management controller, the second baseboard management controller, and the complex programmable logic device are arranged on the motherboard; a backplane connected to the motherboard; a first long hard drive connected to the backplane via a first express peripheral component interconnect interface; a second long hard drive connected to the backplane via a second express peripheral component interconnect interface; and a short hard drive connected to the backplane via a The third Express Peripheral Component Interconnect interface is connected to the backplane. The first Express Peripheral Component Interconnect interface and the second Express Peripheral Component Interconnect interface each correspond to eight slots, while the third Express Peripheral Component Interconnect interface corresponds to four slots. Furthermore, the first Express Peripheral Component Interconnect interface, the second Express Peripheral Component Interconnect interface, and the third Express Peripheral Component Interconnect interface comply with enterprise and data center solid-state drive form factor specifications.