TWI890101B - Package structure and method of forming the same - Google Patents

Abstract

Embodiments include methods of forming three-dimensional packages and the packages resulting therefrom. The packages may utilize a bridge die to electrically connect one die to another die and at least one additional die adjacent to the bridge die. The height-to-width ratio of the gap between the bridge die and the at least one additional die is controlled by thinning the bridge die to be thinner than the at least one additional die. The packages may utilize landing structures to adjoin a dielectric material of an attached die to a metallic landing structure of a base die.

Description

Package structure and method of forming the same

The present invention relates to a packaging structure and a method for forming the same.

Integrated circuit (IC) packages are becoming increasingly complex, with more device dies being packaged into the same package to achieve greater functionality. For example, System on Integrated Chip (SoIC) has been developed to include multiple device dies, such as multiple processors and multiple memory cubes, in the same package. A SoIC can include multiple device dies, each formed using different technologies and having different functionality from other device dies bonded to the same device die, to form a system. This can reduce manufacturing costs and optimize device performance.

An embodiment of the present invention provides a method for forming a package structure, comprising: aligning a bonding pad of a second die with a first bonding pad metal of a first die, wherein the first die includes the first bonding pad metal and a second bonding pad metal, the second bonding pad metal being adjacent to the first bonding pad metal; bonding a second dielectric bonding layer of the second die to the first dielectric bonding layer of the first die; bonding the bonding pad of the second die to the first bonding pad metal of the first die, directly connecting the bonding pad of the second die to the first bonding pad metal; and bonding the second dielectric bonding layer of the second die adjacent to the second bonding pad metal of the first die.

The present invention provides a method for forming a package structure, comprising: bonding a bridge die to a first die and a second die, wherein the bridge die electrically couples the first die to the second die, and wherein the bridge die has a first thickness; bonding a third die to the first die and bonding a fourth die to the second die, wherein the bridge die is sandwiched between the third die and the fourth die, wherein the third die has a second thickness and the fourth die has a third thickness, wherein the third die has a second thickness and the fourth die has a third thickness. The second thickness and the third thickness each fall between 5 and 15 times the first thickness; depositing an encapsulation over the bridge die, the first die, and the second die, the encapsulation laterally surrounding the third die, the fourth die, and the bridge die; and grinding the upper surface of the encapsulation and upper portions of the third die and the fourth die until each of the second thickness and the third thickness falls between 3 and 10 times the first thickness.

An embodiment of the present invention provides a package structure comprising: a first die, the first die including a first bonding pad and a dummy bonding structure disposed on a first surface of the first die, the first bonding pad and the dummy bonding structure being laterally surrounded by a first dielectric bonding layer; and a second die, the second die including a second bonding pad disposed on a second surface of the second die, the second bonding pad being laterally surrounded by a second dielectric bonding layer, the second bonding pad being directly bonded to the first bonding pad, an inner portion of the second dielectric bonding layer being bonded to the first dielectric bonding layer, and an edge portion of the second dielectric bonding layer being adjacent to the dummy bonding structure.

10: Supporting base

12: Exfoliation layer

14, 22: Encapsulation

16: Insulating layer

18: Joint layer

20, 154: Joint structure

20b, 154b: Active engagement pad

20bp, 154bp, 254, 354, 404: junction pads

20c, 154c: Corner positioning structure

20d, 154d: Virtual bonding pad

20e, 154e: Edge positioning structure

20ls, 154ls: Positioning structure

20r, 154r: Ring positioning structure

23, 138, 238, 332, 338: Dielectric layer

24: Wafer bonding layer

25, 136, 146, 236, 246, 336: Through holes

25m: Metallized pattern

26, 100, 200, 300: Wafers

27: Re-routing wiring structure

28: Passivation layer

30: Metal column

32: Metal roofing

34: Conductive connector

50: SoIC package device

105: Grain, first grain

205: Grain, Second Grain

105a: First die, die, device die

105b: Second die, die, device die

106: Cutting Line

116: Optional perforation, silicon through-hole

120, 220: semiconductor substrate

122, 222: Integrated circuit device

124, 224: Interlayer dielectric

128, 228: Contact plug

130, 230, 330: Internal connection structure

132: Dielectric layer, intermetallic dielectric layer

132A: Corresponding dielectric layer

134, 234, 334: Metal wire

134A: Metal wire, top metal wire

138A, 138B, 138C, 238A, 238B, 238C: Dielectric layer

144, 244: Metal Characteristics

152, 252, 352: Dielectric bonding layer

156, 157, 256, 257, 356: Bonding pad through holes

160: Monomerization process

202a, 202b, 202c: Die bonding area

205a, 205b: Device chips

216: Silicon perforation

305: Bridge Die

305a, 305b: Silicon bridge die, bridge die

320, 320’: Base

395, 397: Package device

400: Package substrate

402: Base core

D1, D2, D3, D4, D5: Distance

G1: Gap

T1, T2, T3: Thickness

The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Figure 1 shows a perspective view of a package structure at an intermediate step according to some embodiments.

Figure 2 shows a top view of a package assembly in which multiple device dies are defined.

Figures 3 and 4 illustrate cross-sectional views of intermediate stages in the formation of a package assembly according to some embodiments of the present disclosure.

Figures 5 and 6 illustrate cross-sectional views of intermediate stages in the formation of a package assembly according to some embodiments of the present disclosure.

Figures 7 and 8 illustrate cross-sectional views of intermediate stages in the formation of a bridge assembly according to some embodiments of the present disclosure.

Figures 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 12C, 12D, 12E, 12F, 12G, 13A, 13B, 13C, 13D, 13E, 13F, 13G, 14A, 14B, Figures 15, 16, 17, 18, and 19 illustrate intermediate stages in the formation of a package structure having die positioning structures using bridge dies and various architectures, according to some embodiments.

Figures 20A, 20B, 20C, 20D, 20E, 20F, 21A, 21B, 21C, 21D, 21E, 21F, 22, 23, 24, and 25 illustrate intermediate stages in the formation of a package structure using die positioning structures of various configurations, according to some embodiments.

This disclosure provides numerous different embodiments or examples for implementing various features of the disclosure. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature being formed on a second feature or the second feature being formed on the second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing the first and second features from directly contacting each other. Furthermore, this disclosure may reuse reference numbers and/or letters throughout the various examples. This repetition is for the sake of brevity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of explanation, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and similar terms, may be used herein to describe the relationship of one element or feature to another element or feature as depicted in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

Three-dimensionally packaged devices can utilize die stacking or chip-on-wafer stacking to achieve greater functionality in a smaller overall footprint. Bonding multiple dies to other dies or other wafers can utilize a direct bonding method, in which multiple bond pads in a first device are pressed to multiple bond pads in a second device, and the dielectric layer of the first device is pressed to the dielectric layer of the second device. Through pressure and annealing processes, the dielectric layers melt or bond together, forming a fusion bond across the interface, and the bond pads are bonded together through inter-diffusion of the materials. One of the challenges faced when bonding devices is warpage. The devices may experience varying warp characteristics, and direct bonding techniques may fail due to warp stress, resulting in delamination or voids. Embodiments provide a direct bonding technique to increase bonding interface strength, in which dielectric material along the edge of the top die is bonded adjacent to a dummy bond pad on the underlying die or wafer. The connection between the dummy bond pad (which is metallization) and the dielectric material is achieved through a variety of mechanisms, discussed in further detail below. These metal-to-dielectric bonds can be located at the edges and/or corners of the top die, which are the portions of the top die most susceptible to delamination or other warp-induced failures.

A bridge die can be used to electrically couple multiple metal features from one device to another. For example, the bridge die can provide an electrical path from a first external connector on the bridge die to a second external connector on the bridge die. The first external connector can then be connected to a first device, and the second external connector can be connected to a second device, thereby forming an electrically conductive bridge between the first and second devices. One problem with such bridge intra-die interconnects is that in devices with multiple top device dies, the die thickness and gaps between the dies can result in multiple openings between them. These openings have a high height-to-width ratio, making it difficult to reliably deposit an encapsulation between the bridge die and the top device die. For example, when the spacing is between approximately 50 μm and 100 μm and the thickness of the bridge die and the thickness of the top device die are between 200 μm and 500 μm, the combination of an aspect ratio between 4:1 and 10:1 and a relatively deep opening between 200 μm and 500 μm may result in insufficient encapsulant deposition. Embodiments use a bridge die that is much thinner than the top device die, effectively reducing the aspect ratio to between 1:5 and 1:3 (measured based on the smaller height of the bridge die).

The embodiments discussed herein are discussed in the context of three-dimensional packages (e.g., system-on-integrated-circuit (SoIC) packages) and methods for forming the same, but it should be understood that the disclosed techniques and devices can be used in other packaging contexts. Intermediate stages in forming a SoIC package will be described with respect to some embodiments. Certain variations of some embodiments will also be discussed. Similar reference numerals are used to denote similar components throughout the various views and illustrative embodiments. It should be understood that while the concepts of the disclosed embodiments are explained using the formation of a SoIC package as an example, the disclosed embodiments can also be readily applied to other bonding methods and structures (e.g., where metal pads and vias are bonded to each other).

Figure 1 shows a perspective view of a SoIC package device 50 at an intermediate stage according to some embodiments. For clarity, some details are omitted. Although some examples of die types 105 and 205 are listed below, dies 105 and 205 can be any die. Die 105 can be a logic die, such as a central processing unit (CPU) die, a microcontroller unit (MCU) die, an input-output (IO) die, a baseband (BB) die, an application processor (AP) die, or the like. Die 105 may also be a memory die, such as a dynamic random access memory (DRAM) die or a static random access memory (SRAM) die. Die 105 may be part of a wafer (see FIG2 ). In some embodiments, multiple dies 205 may be bonded to a wafer that is later singulated (see, for example, FIG20A and FIG20B to FIG25 ). Die 205 is electrically bonded to die 105. Die 205 may be a logic die, which may be a CPU die, an MCU die, an IO die, a baseband die, or an AP die. Die 205 may also be a memory die. Multiple dies 205 may be bonded to die 105, each die 205 having different and/or similar functions.

The bridge die 305 is bonded to the first die 105a (also referred to as a die or device die) and the second die 105b (also referred to as a die or device die), and bridges the connection between the first die 105a and the second die 105b. It should be understood that in some embodiments, multiple bridge dies 305 can be used in various combinations with multiple dies 105.

FIG2 illustrates a wafer 100 having multiple dies 105 defined or formed therein (or, more generally, a package assembly having multiple dies 105 defined or formed therein, for example, with the wafer being provided as an example). Dies 105 may all be of the same design and function, or may be of different designs and functions. Dashed lines represent dicing lines 106, where dies 105 are separated from one another during a subsequent singulation process.

Figures 3 to 6 show cross-sectional views of intermediate stages in the formation of a package assembly according to some embodiments of the present disclosure. Figure 3 shows a partial cross-sectional view of a wafer 100. According to some embodiments of the present disclosure, wafer 100 is a device wafer that includes a plurality of integrated circuit devices 122, which may include, for example, active devices such as transistors and/or diodes, and may be passive devices such as capacitors, inductors, resistors, or the like. In other embodiments of the present disclosure, wafer 100 includes passive devices (without active devices). Wafer 100 may include a plurality of package device areas, which will be separated from wafer 100 during the singulation process to form a plurality of dies 105. These package device regions are referred to as die 105. As shown, wafer 100 includes a portion of die 105a and a portion of die 105b. Die 105 can be an integrated circuit die, a passive die, an interposer, etc. It should be understood that these views are illustrative only and not limiting.

According to some embodiments of the present disclosure, wafer 100 includes a semiconductor substrate 120 and a plurality of features formed on a top surface of semiconductor substrate 120. Semiconductor substrate 120 may be formed of crystalline silicon, crystalline germanium, crystalline silicon germanium, and/or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or the like. Semiconductor substrate 120 may also be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. A plurality of shallow trench isolation (STI) regions (not shown) may be formed in semiconductor substrate 120 to isolate a plurality of active regions within semiconductor substrate 120. A plurality of optional through vias 116 (also referred to as TSVs) may be formed to extend into the semiconductor substrate 120 , and the optional through vias 116 may be used to electrically couple features on opposite sides of the wafer 100 to each other.

According to some embodiments of the present disclosure, wafer 100 includes a plurality of integrated circuit devices 122 formed on a top surface of a semiconductor substrate 120. Exemplary integrated circuit devices 122 may include complementary metal-oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, and/or the like. Details of integrated circuit devices 122 are not shown. According to other embodiments, wafer 100 is used to form an interposer, wherein semiconductor substrate 120 may be a semiconductor substrate, or a dielectric substrate in place of a semiconductor substrate.

An inter-layer dielectric (ILD) 124 is formed over semiconductor substrate 120 and fills the spaces between gate stacks (not shown) of multiple transistors in integrated circuit device 122. In some embodiments, ILD 124 is formed from phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), fluoro-silicate glass (FSG), silicon oxide formed from tetraethyl ortho-silicate (TEOS), or the like. The interlayer dielectric 124 can be formed using spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or similar processes.

A plurality of contact plugs 128 are formed in the interlayer dielectric 124 to electrically connect the integrated circuit device 122 to a plurality of overlying metal lines 134 and a plurality of vias 136. According to some embodiments of the present disclosure, the contact plugs 128 are formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and/or multiple layers thereof. The formation of the contact plugs 128 may include forming a plurality of contact openings in the interlayer dielectric 124, filling the contact openings with a conductive material, and performing a planarization process (e.g., a chemical mechanical polishing (CMP) process) to align the top surfaces of the contact plugs 128 with the top surface of the interlayer dielectric 124.

An interconnect structure 130 resides above the interlayer dielectric 124 and the contact plugs 128. The interconnect structure 130 includes a plurality of dielectric layers 132, a plurality of metal lines 134, and a plurality of vias 136 formed in the dielectric layers 132. Dielectric layers 132 are hereinafter alternatively referred to as inter-metal dielectric (IMD) layers 132. According to some embodiments of the present disclosure, at least the lower dielectric layer of dielectric layers 132 is formed of a low-k dielectric material having a dielectric constant (k-value) less than approximately 3.0 or approximately 2.5. The dielectric layer 132 may be formed of black diamond (a registered trademark of Applied Materials), a low-k dielectric material containing carbon, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like. According to alternative embodiments of the present disclosure, some or all of the dielectric layer 132 may be formed of a non-low-k dielectric material, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or the like. According to some embodiments of the present disclosure, the formation of dielectric layer 132 includes depositing a dielectric material containing a porogen, followed by a curing process to remove the porogen, leaving dielectric layer 132 porous. Multiple etch stop layers (not shown), which may be formed of silicon carbide, silicon nitride, or the like, may be formed between intermetallic dielectric layers 132 and are not shown for simplicity.

Metal lines 134 and through-holes 136 are formed in dielectric layer 132. Hereinafter, metal lines 134 at the same level are sometimes collectively referred to as metal layers. According to some embodiments of the present disclosure, interconnect structure 130 includes multiple metal layers interconnected through through-holes 136. Metal lines 134 and through-holes 136 can be formed of copper or copper alloys, or can be formed of other metals. The formation process can include a single damascene process and a double damascene process. In the single damascene process, a trench is first formed in one of the dielectric layers 132, and then the trench is filled with a conductive material. A planarization process (e.g., CMP) is then performed to remove excess conductive material above the top surface of the IMD layer, leaving metal lines in the trenches. In a dual damascene process, trenches and via openings are simultaneously formed in the IMD layer, with the via openings connecting to the underlying trenches. Conductive material is then filled into the trenches and via openings to form metal lines and vias, respectively. The conductive material may include a diffusion barrier and a copper-containing metal material above the diffusion barrier. The diffusion barrier may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

Metal lines 134 include multiple metal lines 134A, which may be referred to as top metal lines. Top metal lines 134A are also collectively referred to as the top metal layer. The corresponding dielectric layer 132A may be formed from a non-low-k dielectric material such as undoped silicate glass (USG), silicon oxide, silicon nitride, or the like. The corresponding dielectric layer 132A may also be formed from a low-k dielectric material, which may be selected from materials similar to those of the underlying intermetallic dielectric layer 132.

According to some embodiments of the present disclosure, multiple dielectric layers 138 and multiple dielectric bonding layers 152 are formed above top metal line 134A. For example, dielectric layers 138 and dielectric bonding layers 152 may be formed of silicon oxide, silicon oxynitride, silicon oxycarbide, or the like. In some embodiments, dielectric layer 138 may be formed of multiple dielectric sublayers 138A, 138B, and 138C. First, dielectric layer 138A is formed. Next, a lithographic process can be used to form a plurality of via openings corresponding to the plurality of vias 146 in dielectric layer 138A. The lithographic process uses, for example, a photoresist and/or hard mask formed and patterned on dielectric layer 138A to facilitate the formation of the plurality of via openings corresponding to vias 146. Anisotropic etching can be used to form these trenches through the photoresist and/or hard mask.

A plurality of vias 146 and a plurality of metal features 144 may be formed on dielectric layer 138A. Vias 146 and metal features 144 may be formed using processes similar to those used to form vias 136 and metal lines 134, although other suitable processes may also be used. Metal features 144 and vias 146 may be formed from copper or a copper alloy, or other metals. In one embodiment, metal features 144 and/or vias 146 may be formed from aluminum or an aluminum-copper alloy. In some embodiments, metal features 144 may be used for die testing.

In some embodiments, metal features 144 may be directly probed to perform chip probe (CP) testing on wafer 100. Optionally, multiple solder areas (e.g., solder balls or solder bumps) may be provided on metal features 144, and the solder areas may be used to perform CP testing on wafer 100. CP testing may be performed on wafer 100 to determine whether each die 105 in wafer 100 is a known good die (KGD). Consequently, only die 105 (i.e., KGDs) undergo subsequent processing steps for packaging, while dies that fail CP testing are not packaged. After testing, the solder areas (if any) may be removed in subsequent processing steps.

Then, dielectric layer 138B may be deposited over metal features 144 to a desired thickness. In some embodiments, dielectric layer 138B may then be planarized to align with the top surface, while in other embodiments, the planarization step may be omitted. In some embodiments, dielectric layer 138C is then deposited. Other embodiments may not utilize dielectric layer 138C and may even omit it.

Next, a plurality of bonding pad vias 156 and a plurality of bonding pad vias 157 may be formed. Bonding pad vias 156 extend through dielectric layer 138 to interconnect structure 130, while bonding pad vias 157 extend to and electrically couple with metal features 144. The plurality of openings for bonding pad vias 156 and 157 may be formed using a photoresist (not shown) and/or a hard mask (not shown). The photoresist and/or hard mask is formed and patterned on dielectric layer 138 to facilitate the formation of the plurality of openings for bonding pad vias 156 and 157. According to some embodiments of the present disclosure, an anisotropic etch is performed to form the openings. The etch may stop on the metal feature 144 (for bond pad via 157) or on the metal line 134 of the interconnect structure 130 (for bond pad via 156).

Next, the plurality of openings for bond pad vias 156 and bond pad vias 157 may be filled with a conductive material. A conductive diffusion barrier (not shown, also referred to as a diffusion barrier) may be formed first. According to some embodiments of the present disclosure, the conductive diffusion barrier may be formed of titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive diffusion barrier is formed, for example, by atomic layer deposition (ALD), physical vapor deposition (PVD), or a similar process. The conductive diffusion barrier may include a layer in the openings of bond pad vias 156 and 157 and a layer extending over the top surface of dielectric layer 138.

Next, metal material is deposited by electrochemical plating (ECP) or another suitable deposition process to form bond pad vias 156 and 157, for example. The metal material is deposited on the conductive diffusion barrier and fills the remaining openings for bond pad vias 156 and 157. The metal material may also extend over the top surface of dielectric layer 138. The metal material may include copper or a copper alloy. Bond pad vias 156 and 157 may be formed simultaneously.

A planarization process, such as a chemical mechanical polishing (CMP) process, may then be performed to remove excess metal material and the conductive diffusion barrier until the dielectric layer 138 is exposed. The remaining portions of the conductive diffusion barrier and the conductive metal material include the bond pad via 156 and the bond pad via 157.

Next, a dielectric bonding layer 152 may be formed over dielectric layer 138, and a plurality of openings for a plurality of bond pads 154bp may be formed in dielectric bonding layer 152. Bond pads 154bp may include a plurality of dummy bond pads 154d (which may be pads that are not electrically coupled to any other conductive elements in the device) or a plurality of active bond pads 154b (which may be electrically coupled to any underlying conductive features, such as bond pad vias 156 and bond pad vias 157). The plurality of openings may be formed using a photoresist (not shown) and/or a hard mask (not shown) formed and patterned over dielectric bonding layer 152 to facilitate formation of the plurality of openings for bond pads 154bp. According to some embodiments of the present disclosure, an anisotropic etch or wet etch is performed to form an opening for bond pad 154bp. The etch may stop on dielectric layer 138C, which may serve as an etch stop in some embodiments. In other embodiments, dielectric bond layer 152 may be etched selectively to dielectric layer 138, such that after dielectric bond layer 152 is etched through, dielectric layer 138 is not etched through. In some embodiments, the etch may be time-dependent. The opening for bond pad 154bp may expose the upper surfaces of bond pad via 156 and bond pad via 157.

Next, a diffusion barrier and metal material may be deposited in the opening to form bond pad 154bp. Bond pad 154bp may be formed using processes and materials similar to those used to form bond pad via 156 and bond pad via 157 described above. A planarization process, such as a chemical mechanical polishing (CMP) process, may then be performed to remove excess metal material and diffusion barrier until dielectric bonding layer 152 is exposed. The remaining diffusion barrier and metal material comprise bond pad 154bp, which is subsequently used for bonding to another device. It should be understood that a metal wire may also be formed simultaneously with bond pad 154bp.

In some embodiments, bond pad via 156 and bond pad via 157 may be formed simultaneously with bond pad 154bp. In such embodiments, after dielectric bonding layer 152 is formed, a plurality of openings are formed in dielectric bonding layer 152, as described above. Then, additional plurality of openings for bond pad via 156 and bond pad via 157 are formed in dielectric layer 138, as described above. Next, a conductive diffusion barrier and metal material may be formed for bond pad vias 156 and 157 and bond pad 154bp in the same process, as described above. A planarization process, such as a CMP process, may then be used to remove excess metal material and the conductive diffusion barrier until dielectric bonding layer 152 is exposed. The conductive diffusion barrier and the remaining metal material comprise bond pads 154bp, which are subsequently used to bond to another device. Metal lines extending in the same layer as bond pads 154bp may also be formed simultaneously with bond pads 154bp. It should be understood that additional bond pad vias 156 and 157, as shown, may be formed.

The location and number of bond pads 154bp can be adjusted based on the devices to be bonded thereto in subsequent processing. In some embodiments, one or more of bond pads 154bp are not electrically connected to any device in die 105. Such bond pads 154bp can be considered dummy bond pads 154d. In some embodiments, dummy bond pads 154d may continue across the surface of die 105, while in other embodiments, bond pads 154bp, including dummy bond pads 154d, may be located only where other devices are to be attached.

FIG4 shows the die 105 after being separated from the wafer 100. The singulation process 160 (see FIG3 ) for singulating the device die from the wafer 100 can be any suitable process, such as using a die saw, laser cutting, or the like to cut through the wafer 100 and the structures formed thereon.

FIG5 illustrates the formation of a wafer 200 including multiple dies 205 (e.g., device die 205a and device die 205b). According to some embodiments of the present disclosure, the die 205 is a logic die, which may be a CPU die, an MCU die, an I/O die, a baseband die, or an AP die. The die 205 may also be a memory die. The wafer 200 includes a semiconductor substrate 220, which may be a silicon substrate.

The die 205 may include an integrated circuit device 222, an interlayer dielectric 224 above the integrated circuit device 222, and a plurality of contact plugs 228 for electrically connecting to the integrated circuit device 222. The die 205 may further include a plurality of interconnect structures 230 for connecting to a plurality of active devices and a plurality of passive devices in the die 205. The interconnect structures 230 include a plurality of metal lines 234 and a plurality of vias 236.

A plurality of through-silicon vias (TSVs) 216, sometimes referred to as through-semiconductor vias (TSVs) or through-holes, may optionally be formed to penetrate into semiconductor substrate 220 (and ultimately through semiconductor substrate 220 by being exposed from the opposite side). If used, TSVs 216 can be used to connect devices and metal lines formed on the front side (top side, shown) of semiconductor substrate 220 to the back side of semiconductor substrate 220. TSVs 216 can be formed using processes and materials similar to those used to form bond pad vias 156, described above and not repeated herein, including, for example, a time-based etching process such that TSVs 216 have a bottom portion disposed between the top and bottom surfaces of semiconductor substrate 220.

Die 205 may include multiple dielectric layers 238 and multiple dielectric bonding layers 252. Multiple vias 246 and multiple metal features 244 may be formed and disposed in dielectric layer 238 (which may include multiple dielectric layers 238A, 238B, and 238C). Multiple bond pad vias 256 and multiple bond pad vias 257 are also formed and disposed in dielectric layer 238, and multiple bond pads 254 are also formed and disposed in dielectric bonding layer 252.

The processes and materials used to form the various features of die 205 can be similar to the processes and materials used to form the various similar features of die 105 and are therefore not repeated here. Similar features between die 105 and die 205 share the same last two digits in their reference numerals.

In FIG6 , wafer 200 is singulated into a plurality of separate device dies 205 , including, for example, device die 205 a and device die 205 b . The singulation process 160 (see FIG5 ) can be the same as or similar to the singulation process discussed above with respect to FIG4 .

FIG7 illustrates the formation of a wafer 300 according to some embodiments, wherein the wafer 300 includes a plurality of bridge die 305 (e.g., a silicon bridge die (also referred to as bridge die) 305a and a silicon bridge die (also referred to as bridge die) 305b). The substrate 320 may include any of the candidate substrates discussed above with respect to the semiconductor substrate 120. An interconnect structure 330 is provided to electrically connect various bond pads 354 to other bond pads 354 and/or to a plurality of optional through-silicon vias.

The interconnect structure 330 includes multiple dielectric layers 332, multiple metal lines 334, and multiple vias 336 formed in the dielectric layers 332. The interconnect structure 330 can be formed using the same processes and materials as described above for the interconnect structure 130 (and using the same processes and materials for the dielectric layers 332 as described above for the dielectric layers 132, the same processes and materials for the metal lines 334 as described above for the metal lines 134, and the same processes and materials for the vias 336 as described above for the vias 136).

Bridge die 305 may include multiple dielectric layers 338 and a dielectric bonding layer 352. Multiple bonding pad vias 356 are formed and disposed in dielectric layer 338, and multiple bonding pads 354 are formed and disposed in dielectric bonding layer 352. The processes and materials used to form the various features of bridge die 305 may be similar to the processes and materials used to form the various similar features of die 105 and are therefore not repeated here. Similar features between die 105 and bridge die 305 share the same last two digits in their reference numerals.

After forming the bonding pads 354, the base 320 of the bridge die 305 may be thinned to form a base 320', such that the total thickness of the wafer 300 is between approximately 15 μm and 30 μm. In some embodiments, the base 320 may be completely removed by a thinning process. The thinning process may include an etching process, a grinding process, a CMP process, or a combination thereof.

In FIG8 , wafer 300 is divided into a plurality of separate bridge dies 305 , including, for example, bridge die 305 a and bridge die 305 b . The singulation process 160 (see FIG7 ) can be the same as or similar to the singulation process discussed above with respect to FIG4 .

Figures 9A, 9B, through 19 illustrate intermediate steps in forming a SoIC package using a bridge die (e.g., bridge die 305). Some of the figures include one or more top-down views. For example, Figure 9A is a cross-sectional view, and Figure 9B is a top view. It should be understood that these views are merely examples and variations are within the scope of this disclosure. For example, the top view and cross-sectional view provided in each figure may be only partial views and may be incorporated into other devices or structures.

In Figures 9A and 9B , a carrier substrate 10 is provided, and a release layer 12 is formed on the carrier substrate 10. The carrier substrate 10 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 10 may be a wafer, allowing multiple packages to be formed on the carrier substrate 10 simultaneously.

The release layer 12 can be formed from a polymer-based material that can be removed along with the carrier substrate 10 from an overlying structure to be formed in a subsequent step. In some embodiments, the release layer 12 is an epoxy-based thermal-release material that loses adhesion when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 12 can be a UV adhesive that loses adhesion when exposed to UV light. The release layer 12 can be dispensed and cured via a liquid, can be a lamination film laminated onto the carrier substrate 10, or can be similar. The top surface of the release layer 12 can be horizontal and highly flat.

Two or more of the plurality of dies 105 may be placed on a carrier substrate 10 and attached to a release layer 12. Each die 105 (e.g., die 105a and 105b, collectively referred to as die 105) may be placed on the release layer 12 using a pick-and-place process to position each die 105 on the carrier substrate 10. In some embodiments, as shown in Figures 9A and 9B, dies 105a and 105b may be placed face-down (backside up). In other embodiments, dies 105a and 105b may be placed face-up. It should be understood that each die 105 may have the same or different functions and may be the same size or different sizes.

In Figures 10A and 10B , a filler material (e.g., an insulating material or encapsulant 14) may be deposited over and laterally surrounding the die 105a and 105b. Encapsulant 14 may comprise a dielectric material such as a resin, epoxy, polymer, oxide, nitride, the like, or combinations thereof. Encapsulant 14 may be deposited by any suitable process, such as flow CVD, spin-on coating, PVD, the like, or combinations thereof.

In Figures 11A and 11B , a planarization process can be used to align the upper surface of the encapsulant 14 with the upper surfaces of the dies 105a and 105b. The planarization process can include grinding and/or chemical mechanical polishing (CMP) processes. The planarization process can continue until the through-silicon vias 116 are exposed through the semiconductor substrate 120 (see Figure 4) of each die 105.

Figures 12A, 12B, 12C, 12D, 12E, 12F, and 12G illustrate the formation of a bonding layer 18 and the formation of a plurality of bonding structures 20 in the bonding layer 18. Figure 12A is a cross-sectional view, and Figures 12B, 12C, 12D, 12E, 12F, and 12G illustrate top views of the structure of Figure 12A according to various embodiments, wherein the various embodiments illustrate a plurality of different architectures of the bonding structure 20. The bonding layer 18 may be formed on the upper surfaces of the encapsulation 14 and the through-silicon vias 116. The bonding structures 20 are formed in the bonding layer 18. The bonding structure 20 may include multiple active bond pads 20b physically coupled to the through-silicon vias 116; multiple dummy bond pads 20d not connected to any metal features on the die 105; multiple edge landing structures 20e disposed around the die-attach area and serving as a special type of dummy bond pad; multiple ring landing structures 20r disposed as ring-shaped metal wires surrounding and overlapping the die-attach area; and multiple corner landing structures 20c disposed at the corners of the die-attach area and in the form of L-shaped metal wires. The various bonding structures 20 are discussed in more detail below. For simplicity, the dummy bonding pad 20d and the active bonding pad 20b may be referred to as bonding pad 20bp.

Bonding layer 18 may be formed of any suitable insulating layer, such as silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, the like, or combinations thereof, and may be deposited using any suitable technique, such as CVD, PVD, spin-on coating, and the like. To form bonding structure 20, a plurality of openings may be formed in bonding layer 18 depending on the location and shape of bonding structure 20. The plurality of openings may be formed using a photoresist (not shown) and/or a hard mask (not shown) formed over bonding layer 18 and patterned to facilitate formation of the plurality of openings in bonding structure 20. In some embodiments, anisotropic etching or wet etching is performed to form the plurality of openings in bonding structure 20. The etching may stop on the base 120 of the encapsulation 14 and the dies 105a, 105b. The openings for bonding the structure 20 may expose the upper surface of the TSV 116.

Next, a diffusion barrier and metal material may be deposited in the plurality of openings to form bonding structure 20. The diffusion barrier and metal material may be deposited using the same materials and techniques discussed above for forming bond pad vias 156 and 157. A planarization process, such as a chemical mechanical polishing (CMP) process, may then be performed to remove excess metal material and diffusion barrier until bonding layer 18 is exposed. The remaining diffusion barrier and metal material comprise bonding structure 20, which is then ready for bonding to another device.

As shown in FIG12A , in some embodiments, one or more dummy bond pads 20 d may be disposed on the portion of encapsulation 14 located between dies 105 a and 105 b. Dummy bond pads 20 d may be included for pattern loading purposes and may also help provide better direct bonding, thereby reducing the likelihood of failure.

Referring to Figures 12B, 12C, 12D, 12E, 12F, and 12G, die-attach region 202a (shown in dashed lines) is located on the upper surface of die 105a (shown in dashed lines). Similarly, die-attach region 202b (shown in dashed lines) is located on the upper surface of die 105b (shown in dashed lines). Furthermore, die-attach region 202c is located on the upper surfaces of both die 105a and die 105b and overlaps encapsulation body 14 between dies 105a and 105b. The bonding structure 20 completely within die-attach regions 202a, 202b, and 202c may be a bonding pad 20bp, which includes an active bonding pad 20b and/or a dummy bonding pad 20d. The bonding structures 20 disposed at the edges of the die-attach regions 202a, 202b, and 202c are dummy structures, which may be edge positioning structures 20e, annular positioning structures 20r, or corner positioning structures 20c. These may be collectively referred to as positioning structures 201s. Each of these positioning structures 201s is disposed at the edges and/or corners of the die-attach regions 202a, 202b, and 202c, and is partially located within the die-attach regions 202a, 202b, and 202c and partially located outside the die-attach regions 202a, 202b, and 202c.

In subsequent fabrication processes, multiple device dies and/or multiple bridge dies are attached to the die-attachment regions 202a, 202b, and 202c and bonded to the bonding pads 20bp. According to some embodiments, the edges of the device dies and/or bridge dies are placed on the positioning structures 201s (including edge positioning structures 20e, annular positioning structures 20r, and/or corner positioning structures 20c), and the dielectric material located at the edges of the device dies and/or bridge dies is adjacent to the positioning structures 201s, as described below.

In FIG12B , edge locating structures 20e are continuously arranged completely around the die-attachment areas 202a, 202b, and 202c. The edge locating structures 20e have the same size and spacing as the bonding pads 20bp. Edge locating structures 20e are located at each of the four corners of each of the die-attachment areas 202a, 202b, and 202c. In some embodiments, the bonding structures 20 are dispersed in a regular pattern, with each bonding structure 20 having the same size and spacing. In such embodiments, the regular pattern can help achieve a pattern loading effect. In FIG. 12B , for example, a dummy bonding pad 20 d (indicated by a dotted line) is disposed between the die attach region 202 a and the die attach region 202 c to continue the regular pattern of the bonding structure 20 .

In FIG12C , the edge positioning structures 20e are only provided at the corners of the die attach regions 202a, 202b, and 202c.

In FIG12D , edge-positioning structures 20e are disposed at the corners of die-attach regions 202a, 202b, and 202c. Furthermore, one of the edge-positioning structures 20e is disposed around the die-attach regions 202a, 202b, and 202c in each direction from the edge-positioning structure 20e at the corner toward the edge-positioning structure 20e at the adjacent corner. When the spacing between the bonding structures 20 in the die-attach regions 202a, 202b, and/or 202c is regular, additional edge-positioning structures 20e may be spaced one pitch apart from the edge-positioning structures 20e at the corners in each of two directions toward the edge-positioning structures 20e at the other corners.

In FIG12E , the positioning structure 201s is replaced by an annular positioning structure 20r, replacing the edge positioning structure 20e. The annular positioning structure 20r extends across the perimeter of the die-attachment regions 202a, 202b, and 202c. In some embodiments, the annular positioning structure 20r may be a broken or segmented ring, such as shown relative to the corresponding die-attachment region 202a, where the annular positioning structure 20r appears as a discontinuous line segment in a top-down view.

In Figure 12F, the positioning structure 201s is a corner positioning structure 20c. Corner positioning structure 20c is a special type of ring-shaped positioning structure 20r, in which portions of the ring are removed between multiple corner portions. For example, at a corner of the die-attach area 202a, the first leg of the L-shaped corner positioning structure 20c extends along a first edge of the die-attach area 202a, and the second leg of the L-shaped corner positioning structure 20c extends along a second edge of the die-attach area 202a, where the first edge intersects the second edge.

FIG12G shows an embodiment of a positioning structure that does not utilize the engagement structure 20. In such an embodiment, each of the engagement structures 20 is an active engagement pad 20b or a dummy engagement pad 20d.

It should be understood that each of the arrangements of the bonding structures 20 discussed with respect to Figures 12B through 12G can be combined with one another without limitation. For example, the die-attach areas 202a and 202b can utilize edge locating structures 20e, and the die-attach area 202c can utilize annular locating structures 20r. In another example, the die-attach area 202c can utilize corner locating structures 20c, and both the die-attach area 202a and the die-attach area 202b can omit locating structures. In short, any locating structure 201s may or may not be used with any of the die-attach areas 202a, 202b, and/or 202c, without limitation.

In Figures 13A, 13B, 13C, 13D, 13E, 13F, and 13G, device dies 205a and 205b (which may be referred to as dies 205) and bridge die 305 are bonded to die 105. Figure 13A is a cross-sectional view, and Figures 13B, 13C, 13D, 13E, 13F, and 13G are top views of the structure of Figure 13A according to the embodiments discussed above with respect to Figures 12B, 12C, 12D, 12E, 12F, and 12G, respectively.

Each component (i.e., die 205 and bridge die 305) can be positioned over bonding structure 20 using a pick-and-place process. In some embodiments, each die 205 and each bridge die 305 can be placed and bonded one at a time, while in other embodiments, all die 205 and bridge die 305 can be placed together and then bonded simultaneously. In some embodiments, such as when bridge die 305 has a smaller thickness than die 205, bridge die 305 can be placed and bonded first, followed by placement and bonding of the remaining die 205.

The bonding mechanism for bonding bridge die 305 to device dies 105a, 105b may utilize a direct bonding process, wherein the metal of bond pad 20bp is directly bonded to the metal of bond pad 354 and the metal of bond pad 254, without using solder material at the interface between bond pad 354 and bond pad 254. Furthermore, the bonding mechanism for bonding bridge die 305 to device dies 105a, 105b may further include melting dielectric bonding layer 252 to bonding layer 18. Furthermore, as discussed in more detail below, the bonding mechanism for bonding bridge die 305 to device dies 105a, 105b may further include bonding edge portions and/or corner portions of dielectric bonding layer 252 to positioning structure 201s.

Each die 205 bonded to die 105 may have been tested and determined to be KGD prior to being bonded to die 105. Although each of die 105a and 105b is shown bonded to one die 205, it should be understood that other device dies similar to die 205 may be bonded to die 105. The other device dies may be the same as die 205 or different from die 205. For example, die 205 and the other device dies may be different types of dies selected from the types listed above. Additionally, die 205 may be a digital circuit die, while the other device dies may be an analog circuit die. Die 105 and die 205 (and other device dies, if any) function in combination as a system. Separating system functionality and circuitry into different dies, such as die 105 and die 205, can optimize the formation of these dies and reduce manufacturing costs. Similarly, each bridge die 305 bonded to die 105 to provide bridge connections between dies 105 can be tested and certified as KGD before being bonded to die 105.

Die 205 and bridge die 305 are bonded to die 105a and 105b through direct metal-to-metal electrical contact, fusion of dielectric materials, and bonding between metal and dielectric materials. For example, bond pads 254 and 354 are bonded to bonding structure 20 through direct metal-to-metal bonding. According to some embodiments of the present disclosure, the direct metal-to-metal bonding is copper-to-copper bonding. The dimensions of bond pads 254 and 354 can be greater than, equal to, or less than the dimensions of corresponding bond pads 20bp. Furthermore, dielectric bonding layers 252 and 352 are bonded to bonding layer 18 through dielectric-to-dielectric bonding, which can be, for example, fusion bonding (with formed Si-O-Si bonds). In addition, the edge regions and/or corner regions of the dielectric bonding layers 252 and 352 are bonded or fused to the positioning structure 201s.

To achieve direct bonding, die 205 and bridge die 305 are positioned relative to die 105 so that their respective bond pads 254 and 354 align with bond pad 20bp on die 105. The upper die (die 205 and bridge die 305) are pressed together with the lower die (dies 105a and 105b). Annealing is then performed to allow for cross-diffusion between the metal in bond pad 20bp and the metal in the corresponding overlying bond pads 254 and 354. In some embodiments, the metal in bonding structure 20 diffuses into the metal in corresponding bonding pads 254 and 354, aligning the metal lattices of the corresponding bonding pads and thereby achieving bonding between the bonding pads. Even if they adhere together, an interface between the corresponding bonding pads may still be observed. In other words, bonding pad 254 and bonding pad 20bp will remain discrete and will not fully merge, as if fused together.

During the same process, annealing fuses dielectric bonding layer 252 and dielectric bonding layer 352 to their corresponding bonding layer 18. Specifically, the dielectric material in each layer can cross-bond with the opposing layer. For example, if both dielectric bonding layer 252 and bonding layer 18 are silicon oxide (SiO ₂ ), oxygen atoms in molecules in one bonding layer can bond with silicon atoms and oxygen atoms in molecules in the other bonding layer, forming cross-links, such as Si-O-Si bonds. Similar effects occur with other dielectric materials, such as silicon nitride and silicon oxynitride.

During the same annealing process, the annealing causes the portion of the dielectric bonding layer 252 that contacts the positioning structures 201s (e.g., edge positioning structures 20e, annular positioning structures 20r, and/or corner positioning structures 20c) and the portion of the dielectric bonding layer 352 that contacts the positioning structures 201s (e.g., edge positioning structures 20e, annular positioning structures 20r, and/or corner positioning structures 20c) to be adjacent to (or bonded to) the metal of the positioning structures 201s. In some embodiments, the dielectric-to-metal bonding can occur through metal diffusion into the dielectric bonding layer 252. For example, the metal of the positioning structures 201s can diffuse into the dielectric bonding layer 252 or 352. Then, due to annealing, a crystallized lattice comprising the metal and the material of the dielectric bonding layer 252 or 352 may be formed. At the same time, the dielectric bonding layer 252 or 352 may act as a diffusion barrier, so that diffusion does not continue into the dielectric bonding layer 252 or 352 and negatively affect the insulating properties of the dielectric bonding layer 252 or 352. In some embodiments, the dielectric-to-metal bonding may occur by forming a chemical bond between the metal of the positioning structure 201s and the dielectric bonding layer 252 or 352. For example, the annealing temperature may cause some bonds in dielectric bonding layer 252 or 352 to break, allowing chemical recombination to form bonds with the metal of positioning structure 201s. For example, a nitride or oxide of the metal material in positioning structure 201s may form. For example, when positioning structure 201s is made of copper and dielectric bonding layer 252 or 352 is made of silicon oxide, silicon nitride, silicon oxynitride, or the like, CuO or CuN may form at the interface between dielectric bonding layer 252 or 352 and positioning structure 201s. In some embodiments, diffusion and chemical bonding may occur simultaneously. The resulting bond between the locating structure 201s and the dielectric bonding layer 252 or 352 is stronger for the edges and/or corners of the die 205 and the bridge die 305 than for typical fused edges and/or corners.

The annealing temperature may be greater than about 350° C., and according to some embodiments may be in the range of about 350° C. to about 550° C. The annealing time may be in the range of about 1.5 hours to about 3.0 hours, and according to some embodiments may be in the range of about 1.0 hours to about 2.5 hours.

FIG13A further illustrates the distance D1 of gap G1 between bridge die 305 and device die 205b. A similar gap and distance are located on the opposite side of bridge die 305 from device die 205b (between bridge die 305 and device die 205a), and the following discussion also applies to this gap. As described above, the thickness T1 of bridge die 305 is much smaller than the thickness T2 of device die 205b. Having a thickness T1 smaller than T2 allows the aspect ratio of gap G1 to be controlled by thickness T1, rather than by thickness T2. For example, for a particular distance D1 within gap G1, if thickness T1 is as large as thickness T2, gap G1 may not be reliably filled due to the extreme aspect ratio. However, using a thinner thickness T1 can reduce the aspect ratio, as the aspect ratio of gap G1 becomes determined by thickness T1. Furthermore, by utilizing a reduced thickness T1, distance D1 can also be reduced, allowing for better chip density on die 105. In some embodiments, thickness T1 can be in a range between approximately 15 μm and 50 μm, and thickness T2 can be in a range between approximately 5 times and 20 times the thickness T1, for example, between approximately 100 μm and approximately 500 μm. In some embodiments, thickness T2 can range from approximately 5 times to 15 times thickness T1. The distance D1 of gap G1 between bridge die 305 and device die 205b can range from approximately 50 μm to 100 μm. Thus, compared to an aspect ratio of approximately 2:1 to 10:1 (which would be the case if bridge die 305 had a thickness similar to device die 205b), the aspect ratio is actually reduced to approximately 1:5 to 1:3 (bridge die 305 is measured to have a smaller height). The distance D2 between die 105 can range from approximately 50 μm to 100 μm.

Embodiments may use the positioning structure 201s with die 205 and bridge die 305 having similar thicknesses, may use the positioning structure 201s with die 205 and bridge die 305 having different thicknesses (as shown in FIG. 13A ), or may omit the positioning structure 201s and utilize die 205 and bridge die 305 having different thicknesses. An example of using the positioning structure 201s with multiple dies having similar thicknesses is provided below.

For embodiments utilizing positioning structure 201s, a callout circle is shown in FIG13A to illustrate an enlarged section of the interface at the edge of die 205 and bridge die 305. As can be seen in FIG13A, distance D3 corresponds to the width of positioning structure 201s, distance D4 corresponds to the width of the portion of positioning structure 201s that interfaces with dielectric bonding layer 252 or 352, and distance D5 corresponds to the width of the portion of positioning structure 201s that does not contact dielectric bonding layer 252 or 352. In other words, distance D5 corresponds to the portion of positioning structure 201s that protrudes laterally from the edge of die 205 or bridge die 305. In some embodiments, distance D3 may be within a range between approximately 1 μm and 5 μm. Distances D4 and D5 may each be approximately 10% to 90% of distance D3, their sum being 100% of distance D3, with distance D4 being approximately 0.5 μm at its minimum. Distance D4 having a minimum distance of 0.5 μm provides sufficient positioning area for effective bonding of the corners and/or edges of the die 205 or bridge die 305 to the positioning structure 201s.

13B , 13C , 13D , 13E , 13F , and 13G , top views of connected die 205 and bridge die 305 are shown, depending on the various configurations of the bond pads 20bp and/or the positioning structures 201s . In FIG13B , the edge positioning structures 20e continuously and completely surround the die 205 and bridge die 305 . In FIG13C , the edge positioning structures 20e are positioned within the corner regions of the die 205 and bridge die 305 . In FIG13D , the edge positioning structures 20e are positioned within the corner regions of the die 205 and bridge die 305 . Additionally, at least one of the edge positioning structures 20 e is disposed along the edge between the corner regions of the die 205 and the bridge die 305. In some embodiments, the inner edge positioning structures 20 e may be separated from the edge positioning structures 20 e at the corners by the same spacing as the spacing of the bonding structures 20 (e.g., active bond pads 20 b and dummy bond pads 20 d) within the die 205 and the bridge die 305. In embodiments consistent with each of FIG13B , FIG13C , and FIG13D , the area of the covered edge positioning structure 20 e at the corner regions of the die 205 and the bridge die 305 has a quarter-circular or pie-wedged shape (when the edge positioning structure 20 e is circular in a top view). In embodiments consistent with each of FIG13B and FIG13D , the area of the edge positioning structure 20 e bonded at the corner regions can be approximately half the area of the edge positioning structure 20 e bonded at the edge regions between the corner regions.

In Figure 13E , an annular positioning structure 20r spans the perimeter of die 205 and bridge die 305, with the covered portion bonded to die 205 and bridge die 305, and the laterally protruding portion not contacting die 205 and bridge die 305. In Figure 13F , the positioning structure is a corner positioning structure 20c disposed in the corner region of die 205 and bridge die 305. The first leg of the L-shaped corner positioning structure 20c extends along a first edge of die 205 and bridge die 305, and the second leg of the L-shaped corner positioning structure 20c extends along a second edge of die 205 and bridge die 305, with the first edge intersecting the second edge.

FIG13G illustrates an embodiment that does not utilize a positioning structure for bonding structures 20. In such an embodiment, each of bonding structures 20 is either an active bonding pad 20b or a dummy bonding pad 20d. As described above, in this embodiment, the thickness of bridge grain 305 is significantly smaller than that of grain 205, while in embodiments consistent with those shown in FIG13B-13F, different thicknesses of bridge grain 305 are optional.

It should be understood that each of the die and positioning structure 201s arrangements discussed with respect to Figures 13B through 13G can be combined with one another without limitation. For example, die 205 can utilize a mixed combination of positioning structures 201s from Figures 13B through 13G (including omitting positioning structures 201s for one or more dies 205). Similarly, bridge die 305 can utilize different positioning structures 201s from Figures 13B through 13G (including omitting positioning structures 201s). In short, any one positioning structure 201s may or may not be used with any one of die 205 and bridge die 305 without limitation.

In Figures 14A and 14B , a filler material, such as an insulating material or encapsulation 22, can be deposited over and laterally surround die 205 and bridge die 305. As shown in Figure 14A , because the aspect ratio of gap G1 (see Figure 13A ) between bridge die 305 and die 205 is reduced by reducing the thickness of bridge die 305, encapsulation 22 can reliably fill gap G1 to the bottom of gap G1. Because encapsulation 22 can reliably fill gap G1, it can interface with positioning structure 201s, where positioning structure 201s intersects the sides of die 205 and bridge die 305. The encapsulant 22 may comprise a dielectric material such as a resin, epoxy, polymer, oxide, nitride, the like, or a combination thereof, which may be deposited by any suitable process such as flow CVD, spin-on, PVD, the like, or a combination thereof.

As shown in Figures 14A and 14B, a planarization process can then be used to align the upper surface of the encapsulant 22 with the upper surface of the die 205. Notably, while the thicknesses are different, the bridge die 305 remains buried, as shown in Figure 14A. The planarization process can include grinding and/or chemical mechanical polishing (CMP) processes. The planarization process can continue until the through-silicon vias 216 (if used) are exposed through the base 220 of the die 205. This can reduce the thickness of the die 205 from thickness T2 to thickness T3. Thickness T3 can be greater than 100 μm, for example, in a range between approximately 100 μm and 500 μm. In some embodiments, thickness T3 can range from approximately 3 times thickness T1 to approximately 10 times thickness T1.

In some embodiments, the structure of Figures 14A and 14B is only a single package location among multiple package locations. For example, carrier substrate 10 can be a wafer extending beyond the sidewalls or encapsulation 14 shown in the figures, and additional package areas can be formed adjacent to the package areas shown in the figures. Such package areas can be separated from each other during subsequent processing. In such embodiments, encapsulation 14, bonding layer 18, and encapsulation 22 can also extend beyond the sides of carrier substrate 10. In other embodiments, the structures shown in Figures 14A and 14B are different structures and can be formed separately on separate carrier substrates 10.

In FIG15 , an optional wafer bonding layer 24 may be deposited on the structure of FIG14A , and an optional wafer 26 may be bonded to the structure of FIG14A . In some embodiments, wafer 26 may be a support wafer and may be made of any suitable material, such as silicon, sapphire, or the like. Wafer bonding layer 24 may be deposited using a spin-on technique to achieve high flatness, and wafer 26 may be pressed against wafer bonding layer 24 to achieve adhesion. Wafer bonding layer 24 may include any suitable material deposited by CVD, PECVD, high-density plasma (HDP) CVD (HDP-CVD), or similar processes, such as silicon oxynitride, silicon carbonitride, undoped silica glass, silicon oxide formed from TEOS, the like, or combinations thereof. In some embodiments, wafer bonding layer 24 may include gold, indium, tin, copper, the like, or combinations thereof, deposited by sputtering, PVD, plating (electroplating or electroless plating), or similar processes. In another embodiment, wafer bonding layer 24 may include a polymer or glue and may be deposited by spin-on coating, lamination, or the like.

In Figure 16 , carrier substrate debonding is performed to unload (or peel) carrier substrate 10 from the front side of die 105 and encapsulation 14. According to some embodiments, debonding involves projecting light (e.g., laser light or UV light) onto release layer 12, causing the release layer 12 to decompose under the heat of the light and allowing carrier substrate 10 to be removed. The structure can then be flipped over and placed on tape (not shown).

In FIG17 , a passivation layer 28 is formed on the front sides of device dies 105 a and 105 b and on package 14 . Passivation layer 28 can be a single layer or a composite layer and can be formed from a non-porous material. In some embodiments, passivation layer 28 includes a composite layer having a silicon oxide layer (not shown separately) and a silicon nitride layer (not shown separately) on the silicon oxide layer. Passivation layer 28 can also be formed from other non-porous dielectric materials, such as USG, silicon oxynitride, and the like. Passivation layer 28 can also be formed from polyimide, polybenzoxazole (PBO), and the like. The passivation layer 28 may be deposited by any suitable deposition technique, such as PVD, CVD, spin-on coating, the like, or a combination thereof. The passivation layer 28 may then be patterned such that a plurality of openings in the passivation layer 28 expose the bonding structure 154 and the device dies 105a and 105b.

In FIG. 18 , a plurality of conductive connectors 34 are formed in or within openings in passivation layer 28 . In some embodiments, conductive connectors 34 may include an optional under bump metallurgy (UBM) extending through passivation layer 28 to physically and electrically couple to bonding structure 154 . The UBM may be formed from the same material as bonding structure 154 . Conductive connectors 34 may include ball grid array (BGA) connectors formed from bumps, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, or the like. Conductive connector 34 may comprise a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. Conductive connector 34 may be formed by sputtering, printing, electroplating, electroless plating, CVD, or similar processes. Conductive connector 34 may be solder-free and have substantially vertical sidewalls. In some embodiments, conductive connector 34 comprises a metal pillar 30 and a metal cap layer 32 formed atop metal pillar 30. The metal cap layer 32 may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or combinations thereof, and may be formed by a plating process.

The singulation process 160 described above can be used to separate the plurality of packages into a plurality of package devices 395, each package device 395 including die 105, die 205, bridge die 305, and conductive connectors 34. Wafer 26 can be removed or left in place, if desired. Wafer 26 can be removed by grinding, etching, planarization, or a combination thereof. In some embodiments, wafer bonding layer 24 can be light-sensitive, and the stripping process can include using UV light to strip wafer 26.

In FIG19 , package device 395 is attached to package substrate 400 via conductive connector 34. Package substrate 400 may be a printed circuit board (PCB). Package substrate 400 may include a substrate core 402 and a plurality of bond pads 404 on substrate core 402. An optional redistribution structure (not shown) may also be used on substrate core 402. Substrate core 402 may be made of a semiconductor material such as silicon germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. Furthermore, substrate core 402 may be an SOI substrate. Generally, an SOI substrate includes a semiconductor material layer, such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. Substrate core 402 may also be an organic substrate. In an alternative embodiment, base core 402 is based on an insulating core, such as a fiberglass reinforced resin core. An example core material is a fiberglass resin, such as FR4. Alternative core materials include bismaleimide-triazine (BT) resin, or other PCB materials or films. Build-up films such as ABF or other laminate layers can be used for base core 402.

The base core 402 may include active and passive devices (not shown). A wide variety of devices (e.g., transistors, capacitors, resistors, combinations thereof, and the like) may be used to create and design the device stack to meet the structural and functional requirements. The devices may be formed using any suitable method.

In some embodiments, the conductive connectors 34 are reflowed to electrically couple and physically bond the package device 395 to the bonding pads 404. In some embodiments, a solder resist (not shown) is formed over the substrate core 402, and the conductive connectors 34 may be disposed within a plurality of openings in the solder resist to electrically and mechanically couple to the bonding pads 404. The solder resist may be used to protect areas of the substrate core 402 and/or the bonding pads 404 from external damage.

Figures 20A-20F through 25 illustrate intermediate stages of forming a package using positioning structures according to other embodiments. These figures do not use bridge die 305, but do show two variations of the above-described embodiment, both of which can be incorporated into the above-described embodiment using bridge die 305. The first variation is that the die 105 is used face-up. In the above-described embodiment, the die 105 is used face-down. In addition, because bridge die are not used, the die 105 is not shown as having been singulated prior to use. In other words, the wafer 100 includes each of the die 105 (e.g., die 105a and die 105b) prior to singulation. It should therefore be understood that the above embodiment can utilize the die 105 face-up. Details on how to use the face-up die 105 can be found in the following description. A second variation is that the die 205 have approximately the same thickness. In the above embodiment, the bridge die 305 can be modified to have the same thickness as the die 205. Therefore, the following discussion should provide an understanding of how to use the die with the positioning structure 201s (described above) when the die have the same thickness.

In the following description, like reference numerals are used to refer to like elements. Therefore, the discussion of these elements is omitted, and details about the like elements can be referred to above. It should also be noted that because die 105 is face-up, bond pads 154bp (comprising multiple active bond pads 154b and multiple dummy bond pads 154d) are used instead of bond pads 20bp (comprising multiple active bond pads 20b and multiple dummy bond pads 20d). Similarly, positioning structures 154ls (dummy structures, comprising multiple edge positioning structures 154e, multiple annular positioning structures 154r, and multiple corner positioning structures 154c) are used instead of positioning structures 20ls (comprising multiple edge positioning structures 20e, multiple annular positioning structures 20r, and multiple corner positioning structures 20c).

FIG20A shows that multiple dies 105 (e.g., die 105a and die 105b) are formed in corresponding regions of wafer 100. This structure is similar to the structure of FIG3 and will not be described in detail. However, the dies 105 are not separated from wafer 100 by sawing, but are temporarily left intact. However, in some embodiments, the dies 105 may be singulated and bonded to a carrier (as described above with respect to FIG4), but the dies 105 may be bonded face-up and packaged sideways.

20A is a cross-sectional view, and FIG. 20B, FIG. 20C, FIG. 20D, FIG. 20E and FIG. 20F are top views of the structure of FIG. 12A according to various embodiments, wherein the various embodiments show a plurality of different architectures of the bonding structure 154 (including the positioning structure 154ls and the bonding pad 154bp). Bonding structure 154 may include multiple active bond pads 154b physically coupled to bond pad vias 156 or 157 (see FIG. 3 ), multiple dummy bond pads 154d not connected to any metal features of die 105, multiple edge positioning structures 154e disposed around the die-attach area and serving as a special type of dummy bond pad, multiple annular positioning structures 154r disposed as ring-shaped metal wires surrounding and overlapping the die-attach area, and multiple corner positioning structures 154c disposed at the corners of the die-attach area and in the form of L-shaped metal wires. Bond pads 154bp may include active bond pads 154b and/or dummy bond pads 154d.

Referring to Figures 20B, 20C, 20D, 20E, and 20F, die-attach region 202a (shown by dashed lines) is located on the upper surface of die 105a. Similarly, die-attach region 202b (shown by dashed lines) is located on the upper surface of die 105b. Bonding structures 154 that fall entirely within die-attach regions 202a and 202b may be active bond pads 154b and/or dummy bond pads 154d. For simplicity, active bond pads 154b and/or dummy bond pads 154d may be referred to as bond pads 154bp. The bonding structures 154 disposed at the edges of the die-attach regions 202a and 202b may be edge positioning structures 154e, annular positioning structures 154r, or corner positioning structures 154c. The edge positioning structures 154e, annular positioning structures 154r, and/or corner positioning structures 154c may be referred to as positioning structures 154ls. Each of these positioning structures 154ls is disposed at the edges and/or corners of the die-attach regions 202a and 202b, and is partially within and partially outside the die-attach regions 202a and 202b.

In subsequent fabrication processes, multiple device dies are attached to the die attach regions 202a and 202b and bonded to the active bond pads 154b and dummy bond pads 154d. According to some embodiments, the edges of the device dies rest on the positioning structures 154ls (including the edge positioning structures 154e, the annular positioning structures 154r, and/or the corner positioning structures 154c), and the dielectric material at the edges of the device dies abuts the positioning structures 154ls, as described below.

In FIG20B , edge locating structures 154e are similar to edge locating structures 20e of FIG12B and extend continuously around the perimeter of die attach regions 202a and 202b. Edge locating structures 154e have the same dimensions and spacing as bond pads 154bp.

In FIG20C , the edge positioning structure 154e is only provided at the corners of the die attach regions 202a and 202b , just like the edge positioning structure 20e of FIG12C .

In FIG20D , edge-positioning structures 154e are similar to edge-positioning structures 20e in FIG12D and are disposed at the corners of die-attachment regions 202a and 202b. Furthermore, at least one edge-positioning structure 154e is disposed around die-attachment regions 202a and 202b in each direction from the edge-positioning structure 154e at the corners.

In FIG20E , the edge positioning structure 154e is replaced by a ring-shaped positioning structure 154r, similar to the ring-shaped positioning structure 20r of FIG12E . The ring-shaped positioning structure 20r extends across the perimeter of the die-attachment regions 202a and 202b. In some embodiments, the ring-shaped positioning structure 20r can be a broken or segmented ring, such as that shown relative to the corresponding die-attachment region 202a of FIG12E , which appears as a discontinuous line segment in a top view.

In FIG. 20F , the positioning structure is a corner positioning structure 154c , similar to corner positioning structure 20c , as shown in FIG. 12F above.

In Figures 21A, 21B, 21C, 21D, 21E, and 21F, multiple dies 205 (e.g., device dies 205a and 205b) can be coupled to die attach regions (e.g., die attach regions 202a and 202b) of die 105 (e.g., die 105a and die 105b). The dies can be attached in a manner similar to that described above with respect to Figures 13A, 13B, 13C, 13D, 13E, and 13F, respectively. However, for embodiments consistent with those shown in Figures 21A, 21B, 21C, 21D, 21E, and 21F, the dies 205 and die 105 are face-to-face rather than back-to-back. In particular, die 205 can be bonded to die 105 via a direct bonding process without the need for solder material, such that bond pad 254 is directly bonded to bond pad 154bp, dielectric bonding layer 252 is fused or bonded to dielectric bonding layer 152, and portions of dielectric bonding layer 252 are adjacent to positioning structure 154ls (similar to the bonding to positioning structure 20ls described above and therefore not repeated).

21B , 21C , 21D , 21E , and 21F , top views of connected dies 205 are shown, depending on the various configurations of the bond pads 154bp and/or positioning structures 154ls . In FIG21B , the edge positioning structures 154e extend continuously around the entire perimeter of the die 205. In FIG21C , the edge positioning structures 154e are positioned within the corner regions of the die 205. In FIG21D , the edge positioning structures 154e are positioned within the corner regions of the die 205. Additionally, at least one of the edge positioning structures 154e is positioned along the edge between the corner regions of the die 205. In some embodiments, the inner edge positioning structures 154e can be separated from the edge positioning structures 154e located at the corners by the same spacing as the spacing of the bonding pads 154bp at the inner portion of the die 205. In embodiments consistent with each of FIG. 21B , FIG. 21C , and FIG. 21D , the area of the covered edge positioning structures 154e at the corner regions of the die 205 has a quarter-circle or wedge-shaped shape (when the edge positioning structures 154e are circular in a top view). In embodiments consistent with each of FIG. 21B and FIG. 21D , the area of the edge positioning structures 154e bonded at the corner regions can be approximately half the area of the edge positioning structures 154e bonded at the edge regions between the corner regions.

In Figure 21E , an annular positioning structure 154r spans the perimeter of die 205, with the covered portion bonded to die 205 and the laterally protruding portion not contacting die 205. In Figure 21F , the positioning structure is a corner positioning structure 154c disposed in a corner region of die 205. The first leg of the L-shaped corner positioning structure 154c extends along a first edge of die 205, and the second leg of the L-shaped corner positioning structure 154c extends along a second edge of die 205, with the first edge intersecting the second edge.

In FIG22 , a filler material (e.g., an insulating material or encapsulant 22) can be deposited over and laterally surrounding die 205. As shown in FIG22 , a planarization process similar to that described above with respect to FIG14A and FIG14B can then be used to align the top surface of encapsulant 22 with the top surface of die 205. This planarization process can expose a plurality of through-silicon vias 216 (see FIG5 ).

In FIG23 , a redistribution structure 27 is formed over the package 22 and over the die 205. The redistribution structure 27 can electrically couple signals from the through-silicon vias 216 and/or other signals to subsequently formed conductive connections. The redistribution structure 27 can be formed using a single damascene process or a dual damascene process, using alternating dielectric layers 23 to form a plurality of metallization patterns 25 m and a plurality of vias 25 v coupled to the metallization patterns 25 through the dielectric layers 23. As an example of forming the redistribution structure 27, a first dielectric layer 23 can be formed over the package 22 and over the die 205. An acceptable lithographic process can then be used to form a plurality of openings in the dielectric layer 23 to expose the TSVs 216 or other conductive features. Vias 25v and metallization pattern 25m can be formed in the same process by, for example, depositing a blanket seed layer over the dielectric layer 23 and over the TSVs 216 and other conductive features within the plurality of openings, such as by PVD, CVD, sputtering, or the like. A photoresist can then be formed over the seed layer by spin coating and patterned, leaving a plurality of openings where the metallization pattern 25m will be deposited, extending to the seed layer. Next, the conductive material of the metallization pattern 25m is deposited over the exposed seed layer, for example by electroplating or an electrochemical process. The photoresist can then be removed, and the now-exposed seed layer can be removed, for example, by an etching process. Another layer of dielectric layer 23 can then be deposited, and metallization pattern 25m and vias 25 formed on and through the other layer of dielectric layer 23. This process can be repeated to form any desired number of layers in the redistribution wiring structure 27.

Next, a passivation layer 28 and a plurality of conductive connectors 34 can be formed on the above structure, with the conductive connectors 34 located within the plurality of openings in the passivation layer 28. The passivation layer 28 and the conductive connectors 34 can be formed using the materials and processes described above.

In FIG. 24 , singulation process 160 may be used to separate die 105 and die 205 from each other. Singulation process 160 may, for example, cut along scribe lines between package regions or between die regions. In some embodiments, each of the singulated packages may include multiple dies 105 and/or multiple dies 205.

In FIG. 25 , package device 397 includes second die 205 mounted to first die 105 using a plurality of locating structures 154 ls. The locating structures 154 ls provide greater adhesion at the edges and/or corners of second die 205 than typical dielectric-to-dielectric fusion bonding. Package device 397 can then be mounted to package substrate 400, similar to the description above for package device 395 of FIG. 19 .

Embodiments (at least in some embodiments) achieve advantages by providing positioning structures at the edges of the die-attach region of the first die. The edges and/or corners of the second die can then be bonded to the positioning structures using a direct bonding process, with the dielectric material of the second die adjacent to the conductive material of the positioning structures. In some embodiments, a bridge die can be used whose thickness is less than the thickness of the additional device die, thereby controlling the aspect ratio of the gap between the bridge die and the additional attached device die based on the thickness of the bridge die (to have a width greater than its height). Embodiments including bridge die of reduced thickness can also be used in conjunction with positioning structures to achieve better bonding of the bridge die and/or device die to the die-attach region of the first die.

One embodiment provides a method that includes aligning a bond pad of a second die with a first bond pad metal of a first die, wherein the first die includes the first bond pad metal and a second bond pad metal, with the second bond pad metal adjacent to the first bond pad metal. The method further includes bonding a second dielectric bonding layer of the second die to the first dielectric bonding layer of the first die. The method further includes bonding the bond pad of the second die to the first bond pad metal of the first die, with the bond pad of the second die and the first bond pad metal directly interfacing. The method further includes bonding the second dielectric bonding layer of the second die adjacent to the second bond pad metal of the first die.

In one embodiment, bonding the second dielectric bonding layer, bonding the bonding pad of the second die, and bonding the adjacent second dielectric bonding layer occurs in the same bonding process. In one embodiment, the bonding process may include: placing the second die on the first die; pressing the bonding pad of the second die onto the first bonding pad metal, pressing the second dielectric bonding layer onto the first dielectric bonding layer, and pressing the second dielectric bonding layer onto the second bonding pad metal; and annealing the combination of the second die and the first die to cause the metal material of the bonding pad to diffuse with the first bonding pad metal, forming a dielectric-to-dielectric bond between the second dielectric bonding layer and the first dielectric bonding layer, and forming a plurality of chemical bonds between the second dielectric bonding layer and the first bonding pad metal. In one embodiment, the first bonding pad metal is arranged into a first group of bonding pads, and the second bonding pad metal is arranged into a second group of bonding pads. In one embodiment, the first bonding pads in the first group are spaced apart by a first spacing, and the second bonding pads in the second group are spaced apart by the first spacing. In one embodiment, the second bonding pad metal protrudes laterally from the edge of the second die. In one embodiment, the bond pad is a first bond pad, the second die is a bridge die, and the method may include: attaching the first die to a carrier; attaching the third die to the carrier; depositing a first encapsulant on the carrier, the first encapsulant laterally surrounding the first die and the third die; forming a first bonding layer over the first encapsulant and over the first and third die; forming a first bonding pad metal of the first die in the first bonding layer on the first die; forming a third bonding pad metal of the third die in the first bonding layer on the third die; bonding the second bonding pad of the second die to the third bonding pad metal of the third die; and bonding the second dielectric bonding layer of the second die adjacent to the fourth bonding pad metal of the third die. In one embodiment, the method may include: bonding a first bond pad of a fourth die to a first bond pad metal of a first die; bonding a first bond pad of a fifth die to a third bond pad metal of a third die, wherein the fourth die is laterally spaced a first distance from the second die, the second die having a first thickness, and the fourth and fifth die having a second thickness, the second thickness being between 5 times and 15 times the first thickness; and depositing a second encapsulant over the first encapsulant, the first die, the second die, the third die, the fourth die, and the fifth die, wherein the second encapsulant contacts an upper portion of the first die between the second and fourth die. In one embodiment, a ratio of the first thickness to the first distance is 1:1 to 1:3.

Another embodiment is a method comprising laminating a bridge die to a first die and a second die, the bridge die electrically coupling the first die to the second die, the bridge die having a first thickness. The method further comprises laminating a third die to the first die and a fourth die to the second die, the bridge die being positioned between the third and fourth die, the third die having a second thickness, and the fourth die having a third thickness, wherein each of the second and third thicknesses is between 5 times and 15 times the first thickness. The method further comprises depositing an encapsulation over the bridge die, the first die, and the second die, the encapsulation laterally surrounding the third and fourth die, and the bridge die. The method further includes grinding the upper surface of the encapsulation body and upper portions of the third die and the fourth die until each of the second thickness and the third thickness is between 3 times and 10 times the first thickness.

In one embodiment, the method may include forming a dummy support pad on the upper surfaces of the first die and the second die, wherein attaching the bridge die may include placing a dielectric bonding layer of the bridge die adjacent to the dummy support pad. In one embodiment, the dummy support pad extends laterally beyond an edge of the bridge die, such that a first portion of the dummy support pad interfaces with the bridge die, and a second portion of the dummy support pad is exposed from the bridge die. In one embodiment, a dummy support pad is disposed at a corner of the bridge die, with a second portion of the dummy support pad exposed from the bridge die along a first side of the bridge die, and a third portion of the dummy support pad exposed from the bridge die along a second side of the bridge die. In one embodiment, the dummy support pad has a linear configuration in plan view, with the first linear portion of the dummy support pad and the second linear portion of the dummy support pad meeting and intersecting at the corner of the bridge die. In one embodiment, the first distance is the shortest distance between the bridge die and the third die, wherein a ratio of the first distance to the first thickness is between 3:1 and 1:1. In an embodiment, the first thickness is between 15 μm and 25 μm.

Another embodiment provides a package structure including a first die and a second die. The first die may have a first bonding pad and a dummy bonding structure disposed on its first surface. The first bonding pad and the dummy bonding structure are laterally surrounded by a first dielectric bonding layer. The second die may have a second bonding pad disposed on its second surface. The second bonding pad is laterally surrounded by a second dielectric bonding layer. The second bonding pad is directly bonded to the first bonding pad, an inner portion of the second dielectric bonding layer is bonded to the first dielectric bonding layer, and an edge portion of the second dielectric bonding layer is adjacent to the dummy bonding structure.

In one embodiment, the virtual bonding structure corresponds to a corner region of the second die, and the corner region of the second die contacts the virtual bonding structure. In one embodiment, the virtual bonding structure may include a first line segment extending along a first edge of the second die and a second line segment extending along a second edge of the second die, the first line segment and the second line segment meeting at the corner region of the second die. In one embodiment, the second thickness is between 3 times and 10 times the first thickness; the encapsulation laterally surrounds the second die, the fourth die, and the bridge die, and the encapsulation completely fills a space between the bridge die and the second die, the space having a width between 1 times and 3 times the first thickness.

The above summarizes the features of several embodiments to help those skilled in the art better understand the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and/or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they may make various changes, substitutions, and alterations thereto without departing from the spirit and scope of this disclosure.

10: Supporting base

50: SoIC package device

205: Grain, Second Grain

105a: First die, die, device die

305: Bridge Die

Claims (10)

A method for forming a package structure includes: aligning a bonding pad of a second die with a first bonding pad metal of a first die, wherein the first die includes the first bonding pad metal and a second bonding pad metal, the second bonding pad metal being adjacent to the first bonding pad metal; bonding a second dielectric bonding layer of the second die to the first dielectric bonding layer of the first die; bonding the bonding pad of the second die to the first bonding pad metal of the first die, directly connecting the bonding pad of the second die to the first bonding pad metal; and bonding the second dielectric bonding layer of the second die adjacent to the second bonding pad metal of the first die. The method of claim 1, wherein the bonding pad is a first bonding pad, and wherein the second die is a bridge die, the method further comprising: attaching the first die to a carrier; attaching a third die to the carrier; depositing a first encapsulant on the carrier, the first encapsulant laterally surrounding the first die and the third die; forming a first bonding layer over the first encapsulant and over the first die and the third die; forming the first bonding pad metal of the first die in the first bonding layer over the first die; forming the third bonding pad metal of the third die in the first bonding layer over the third die; bonding the second bonding pad of the second die to the third bonding pad metal of the third die; and bonding the second dielectric bonding layer adjacent to the second die to the fourth bonding pad metal of the third die. The method of claim 2 further comprises: bonding a first bond pad of a fourth die to the first bond pad metal of the first die; bonding a first bond pad of a fifth die to the third bond pad metal of the third die, wherein the fourth die is laterally spaced apart from the second die, the second die having a first thickness, and the fourth and fifth dies having a second thickness, the second thickness being 5 to 15 times greater than the first thickness; and depositing a second encapsulant over the first encapsulant, the first die, the second die, the third die, the fourth die, and the fifth die, the second encapsulant contacting an upper portion of the first die between the second die and the fourth die. A method for forming a package structure includes: bonding a bridge die to a first die and a second die, the bridge die electrically coupling the first die to the second die, the bridge die having a first thickness; bonding a third die to the first die and a fourth die to the second die, the bridge die being sandwiched between the third and fourth dies, the third die having a second thickness and the fourth die having a third thickness, wherein the second thickness and the third thickness each fall between 5 and 15 times the first thickness; depositing an encapsulation over the bridge die, the first die, and the second die, the encapsulation laterally surrounding the third, fourth, and bridge die; and grinding an upper surface of the encapsulation and upper portions of the third and fourth dies until each of the second thickness and the third thickness falls between 3 and 10 times the first thickness. The method of claim 4 further comprises: forming dummy support pads on upper surfaces of the first die and the second die, wherein attaching the bridge die comprises attaching a dielectric bonding layer of the bridge die adjacent to the dummy support pads. The method of claim 5, wherein the dummy support pad has a linear structure in a plan view, and a first linear portion of the dummy support pad and a second linear portion of the dummy support pad meet and intersect at a corner of the bridge die. A package structure includes: a first die, the first die including a first bonding pad disposed on a first surface of the first die and a dummy bonding structure, the first bonding pad and the dummy bonding structure being laterally surrounded by a first dielectric bonding layer; and a second die, the second die including a second bonding pad disposed on a second surface of the second die, the second bonding pad being laterally surrounded by a second dielectric bonding layer, the second bonding pad being directly bonded to the first bonding pad, an inner portion of the second dielectric bonding layer being bonded to the first dielectric bonding layer, and an edge portion of the second dielectric bonding layer being adjacent to the dummy bonding structure. The package structure of claim 7, wherein the dummy bonding structure corresponds to a corner region of the second die, and the corner region of the second die contacts the dummy bonding structure. The package structure of claim 8, wherein the dummy bonding structure includes a first line segment extending along a first edge of the second die and a second line segment extending along a second edge of the second die, wherein the first line segment and the second line segment meet at the corner region of the second die. The package structure of claim 7 further comprises: a third die disposed adjacent to the first die and spaced a first distance apart from the first die; a fourth die bonded to the third die; a bridge die bonded to the first die and the third die, the bridge die spanning the first distance, the bridge die having a first thickness, and the second die having a second thickness, wherein the second thickness is 3 to 10 times the first thickness; and an encapsulant laterally surrounding the second die, the fourth die, and the bridge die, the encapsulant completely filling a space between the bridge die and the second die, the space having a width between 1 and 3 times the first thickness.