TWI889976B - High voltage cmos device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a high voltage complementary metal oxide semiconductor (CMOS) device and a manufacturing method thereof. The high voltage CMOS device includes: a semiconductor layer, a plurality of insulation regions, a first high voltage N-type well and a second high voltage N-type well, which are formed by one same ion implantation process step, a first high voltage P-type well and a second high voltage P-type well, which are formed by one same ion implantation process step, a first drift oxided region and a second oxide region, which are formed by one same etch process step by etching a drift oxide layer; a first gate and a second gate, which are formed by one same etch process step by etching a poly silicon layer, an N-type source and an N-type drain, and a P-type source and a P-type drain.

Description

High voltage complementary metal oxide semiconductor device and manufacturing method thereof

The present invention relates to a high-voltage complementary metal oxide semiconductor (MOS) device and a manufacturing method thereof, and more particularly to a high-voltage complementary metal oxide semiconductor (MOS) device that integrates a high-voltage N-type device and a high-voltage P-type device and a manufacturing method thereof.

High-voltage components are commonly used in power management integrated circuits (PMICs), driver ICs, or server ICs. However, due to the different application ranges of N-type and P-type high-voltage components, their applications are limited, particularly in server ICs. Simply coupling N-type and P-type high-voltage components results in excessive board area and poor efficiency.

In view of this, the present invention proposes a high-voltage complementary metal oxide semiconductor (CMOS) device formed by integrating an N-type high-voltage device and a P-type high-voltage device through an integration process step, and a manufacturing method thereof.

In one aspect, the present invention provides a high voltage complementary metal oxide semiconductor device comprising: a semiconductor layer formed on a substrate; a plurality of insulating regions formed on the semiconductor layer to define a high voltage N-type device region and a high voltage P-type device region, wherein a high voltage N-type device is formed in the high voltage N-type device region, and a high voltage P-type device is formed in the high voltage P-type device region; a first high voltage N-type well region and a second high voltage N-type well region, respectively formed in the high voltage N-type device region by the same ion implantation process step; The semiconductor layer of the high voltage N-type device region and the semiconductor layer of the high voltage P-type device region; a first high voltage P-type well region and a second high voltage P-type well region are respectively formed in the semiconductor layer of the high voltage N-type device region and the semiconductor layer of the high voltage P-type device region by the same ion implantation process step, wherein the first high voltage N-type well region and the first high voltage P-type well region are adjacent to each other in a channel direction, and the second high voltage N-type well region and the second high voltage P-type well region are adjacent to each other in the channel direction; a first A drift oxide region and a second drift oxide region are formed by etching a drift oxide layer in the same etching process step, and the first drift oxide region and the second drift oxide region are formed in the high voltage N-type device region and the high voltage P-type device region respectively; a first gate and a second gate are formed by etching a polysilicon layer in the same etching process step, and the first gate and the second gate are formed in the high voltage N-type device region and the high voltage P-type device region respectively; an N-type source and an N-type drain are formed by the same ion implantation process step. A first gate is formed in the semiconductor layer of the high-voltage N-type device region by a process step, and the N-type source and the N-type drain are respectively located in the first high-voltage P-type well region and the first high-voltage N-type well region below the outside of the first gate; and a P-type source and a P-type drain are formed in the semiconductor layer of the high-voltage P-type device region by a same ion implantation process step, and the P-type source and the P-type drain are respectively located in the second high-voltage N-type well region and the second high-voltage P-type well region below the outside of the second gate.

In another aspect, the present invention provides a method for manufacturing a high-voltage complementary metal oxide semiconductor (CMOS) device, wherein the high-voltage CMOS device includes a high-voltage N-type device and a high-voltage P-type device. The method comprises: forming a semiconductor layer on a substrate; forming a plurality of insulating regions on the semiconductor layer to define a high-voltage N-type device region and a high-voltage P-type device region, wherein the high-voltage N-type device is formed in the high-voltage N-type device region, and the high-voltage P-type device is formed in the high-voltage P-type device region; forming a first high-voltage N-type well region in the high-voltage N-type device region by the same ion implantation process step; The semiconductor layer of the N-type device region and the second high-voltage N-type well region are formed in the semiconductor layer of the high-voltage P-type device region; a first high-voltage P-type well region is formed in the semiconductor layer of the high-voltage N-type device region and a second high-voltage P-type well region is formed in the semiconductor layer of the high-voltage P-type device region by the same ion implantation process step, wherein the first high-voltage N-type well region and the first high-voltage P-type well region are adjacent to each other in a channel direction, and the second high-voltage N-type well region and the second high-voltage P-type well region are adjacent to each other in the channel direction; a drift oxide layer is formed on the semiconductor layer, and the drift oxide layer covers the high-voltage N-type device region and the high-voltage The drift oxide layer is etched in the same etching process step to form a first drift oxide region in the high voltage N-type device region and a second drift oxide region in the high voltage P-type device region; after the first drift oxide region and the second drift oxide region are formed, a gate dielectric layer is formed on the semiconductor On the body layer, the gate dielectric layer covers the high voltage N-type device region and the high voltage P-type device region; a polysilicon layer is formed on the gate dielectric layer, the polysilicon layer covers the high voltage N-type device region and the high voltage P-type device region; the polysilicon layer is etched in the same etching process step to form a first gate on the high voltage N-type The semiconductor layer of the high-voltage N-type component region is provided with a second gate in the high-voltage P-type component region; an N-type source and an N-type drain are formed in the semiconductor layer of the high-voltage N-type component region by the same ion implantation process step, and the N-type source and the N-type drain are respectively located in the first high-voltage P-type well region and the first high-voltage N-type well region below the outside of the first gate; and a P-type source and a P-type drain are formed in the semiconductor layer of the high-voltage P-type component region by the same ion implantation process step, and the P-type source and the P-type drain are respectively located in the second high-voltage N-type well region and the second high-voltage P-type well region below the outside of the second gate.

In one embodiment, the high-voltage complementary metal oxide semiconductor device further includes: a first shallow trench isolation (STI) region and a second shallow trench isolation region, respectively formed in the high-voltage N-type device region and the high-voltage P-type device region using the same process steps, wherein the first STI region is located and connected to the first drift oxide region, and the second STI region is located and connected to the second drift oxide region.

In one embodiment, the high-voltage complementary metal oxide semiconductor device further includes: an N-type conductive region formed in the second high-voltage N-type well region by the same ion implantation process step as that used to form the N-type source and the N-type drain, wherein the N-type conductive region serves as an electrical contact to the second high-voltage N-type well region; and a P-type conductive region formed in the first high-voltage P-type well region by the same ion implantation process step as that used to form the P-type source and the P-type drain, wherein the P-type conductive region serves as an electrical contact to the first high-voltage P-type well region.

In one embodiment, the high-voltage complementary metal oxide semiconductor device further includes: a first N-type buried layer and a second N-type buried layer, respectively formed in the high-voltage N-type device region and the high-voltage P-type device region using the same process steps; wherein the first N-type buried layer is formed in and connected to the semiconductor layer and the substrate directly below the first high-voltage N-type well region and the first high-voltage P-type well region; wherein the second N-type buried layer is formed in and connected to the semiconductor layer and the substrate directly below the second high-voltage N-type well region and the second high-voltage P-type well region.

In one embodiment, the high voltage complementary metal oxide semiconductor device further comprises: a first high voltage N-type isolation region and a second high voltage N-type isolation region, formed by the same ion implantation process step as the first high voltage N-type well region and the second high voltage N-type well region; and a first high voltage P-type isolation region and a second high voltage P-type isolation region, formed by the same ion implantation process step as the first high voltage P-type well region and the second high voltage P-type well region; wherein the first high voltage N-type isolation region is adjacent to the first high voltage in the channel direction. The P-type well region is adjacent to the other side of the first high-voltage N-type well region; the second high-voltage N-type isolation region is adjacent to the other side of the second high-voltage P-type well region adjacent to the second high-voltage N-type well region in the channel direction; the first high-voltage P-type isolation region is adjacent to the other side of the first high-voltage N-type well region adjacent to the first high-voltage P-type well region in the channel direction; and the second high-voltage P-type isolation region is adjacent to the other side of the second high-voltage N-type well region adjacent to the second high-voltage N-type well region in the channel direction.

In one embodiment, the semiconductor layer is a P-type semiconductor epitaxial layer and has a volume resistivity of 45 Ohm-cm.

In one embodiment, the thickness of the drift oxide region is between 400 Å and 450 Å.

In one embodiment, the gate dielectric layer has a thickness between 80 Å and 100 Å.

In one embodiment, a gate driving voltage of a high voltage device in the high voltage device region is 3.3V.

In one embodiment, the minimum feature size of the HVCMOS device is 0.18 microns.

The advantage of the present invention is that the present invention can use the same process steps to simultaneously form different units in the high-voltage N-type device and the high-voltage P-type device of the high-voltage complementary metal oxide semiconductor device.

Another advantage of the present invention is that an isolation region is formed to electrically isolate a high voltage N-type device from a high voltage P-type device in a semiconductor layer.

The following detailed description is based on specific embodiments to make it easier to understand the purpose, technical content, features and effects achieved by the present invention.

The aforementioned technical contents, features, and functions of the present invention are clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings. The drawings in the present invention are schematic, primarily intended to illustrate the process steps and the sequential relationship between the layers. The shapes, thicknesses, and widths are not drawn to scale.

Please refer to FIG1, which shows a cross-sectional view of a high voltage complementary metal oxide semiconductor device 10 according to one embodiment of the present invention. As shown in FIG1, the high voltage complementary metal oxide semiconductor device 10 includes: a semiconductor layer 11', a plurality of insulating regions 12, a first high voltage N-type well region 14a and a second high voltage N-type well region 14b formed by the same ion implantation process step, a first high voltage P-type well region 15a and a second high voltage P-type well region 15b formed by the same ion implantation process step, b. A first drift oxide region 16a and a second drift oxide region 16b are formed by etching a drift oxide layer using the same etching process step; a first gate 17a and a second gate 17b, an N-type source 18a and an N-type drain 18b, and a P-type source 19a and a P-type drain 19b are formed by etching a polysilicon layer using the same etching process step.

Semiconductor layer 11' is formed on substrate 11. Semiconductor layer 11' has an upper surface 11a and a lower surface 11b in a vertical direction (as indicated by the solid arrows in FIG. 1 , and the same applies hereinafter). Substrate 11 is, for example, but not limited to, a P-type or N-type semiconductor substrate. Semiconductor layer 11' is formed on substrate 11, for example, by epitaxial deposition, or a portion of substrate 11 may serve as semiconductor layer 11'. Methods for forming semiconductor layer 11' are well known to those skilled in the art and will not be detailed here.

Continuing with FIG. 1 , a plurality of insulating regions 12 are formed on semiconductor layer 11′. These insulating regions 12 define a high-voltage N-type device region (HV-NMOS) and a high-voltage P-type device region (HV-PMOS). A high-voltage N-type device 10a is formed in the HV-NMOS region, and a high-voltage P-type device 10b is formed in the HV-PMOS region. Insulating regions 12 may be, for example but not limited to, a shallow trench isolation (STI) structure as shown in FIG. 1 .

In this embodiment, the high-voltage N-type device 10a includes a first high-voltage N-type well 14a, a first high-voltage P-type well 15a, a first drift oxide region 16a, a first gate 17a, an N-type source 18a, and an N-type drain 18b. The high-voltage P-type device 10b includes a second high-voltage N-type well 14b, a second high-voltage P-type well 15b, a second drift oxide region 16b, a second gate 17b, a P-type source 19a, and a P-type drain 19b.

Continuing with Figure 1, the first high-voltage N-type well region 14a and the second high-voltage N-type well region 14b are formed in the semiconductor layer 11' of the high-voltage N-type device region HV-NMOS and the semiconductor layer 11' of the high-voltage P-type device region HV-PMOS, respectively, using the same ion implantation process step. Both the first high-voltage N-type well region 14a and the second high-voltage N-type well region 14b are located below and connected to the upper surface 11a. A portion of the first high-voltage N-type well region 14a is located directly below and connected to the gate 17a to provide a drift current channel for the high-voltage N-type device 10a during the on-state operation; and a portion of the second high-voltage N-type well region 14b is located directly below the gate 17b to provide a reverse current channel for the high-voltage P-type device 10b during the on-state operation.

Continuing with FIG. 1 , the first high-voltage P-type well region 15a and the second high-voltage P-type well region 15b are formed in the semiconductor layer 11′ of the high-voltage N-type device region HV-NMOS and the semiconductor layer 11′ of the high-voltage P-type device region HV-PMOS, respectively, using the same ion implantation process step. The first high-voltage N-type well region 14a and the first high-voltage P-type well region 15a are adjacent in the channel direction (as indicated by the dotted arrows in FIG. 1 , and the same applies hereinafter), and the second high-voltage N-type well region 14b and the second high-voltage P-type well region 15b are adjacent in the channel direction.

Both the first high-voltage P-type well region 15a and the second high-voltage P-type well region 15b are located below and connected to the upper surface 11a. A portion of the first high-voltage P-type well region 15a is located directly below and connected to the gate 17a, providing a reverse current path for the high-voltage N-type device 10a during the on-state operation. Furthermore, a portion of the second high-voltage P-type well region 15b is located directly below the gate 17b, providing a drift current path for the high-voltage P-type device 10b during the on-state operation.

The first drift oxide region 16a and the second drift oxide region 16b are etched from the drift oxide layer using the same etching process step, forming the first drift oxide region 16a and the second drift oxide region 16b in the high-voltage N-type device region HV-NMOS and the high-voltage P-type device region HV-PMOS, respectively. The first drift oxide region 16a and the second drift oxide region 16b are formed on the semiconductor layer 11' and are located in the drift region of the high-voltage N-type device 10a and the drift region of the high-voltage P-type device 10b, respectively.

The first gate 17a and the second gate 17b are formed by etching a polysilicon layer in the same etching process step, and the first gate 17a and the second gate 17b are formed in the high voltage N-type device region HV-NMOS and the high voltage P-type device region HV-PMOS respectively.

The first gate 17a and the second gate 17b are formed on the upper surface 11a of the semiconductor layer 11'. The first gate 17a and the second gate 17b respectively include a conductive layer, a spacer layer and a dielectric layer, wherein the dielectric layer is located on the upper surface 11a and connected to the upper surface 11a. This is well known to those with ordinary knowledge in the art and will not be elaborated here.

The N-type source 18a and the N-type drain 18b are formed in the semiconductor layer 11' of the high-voltage N-type device region HV-NMOS using the same ion implantation process step. The N-type source 18a and the N-type drain 18b are respectively located in the first high-voltage P-type well region 15a and the first high-voltage N-type well region 14a below and outside the first gate 17a in the channel direction (as indicated by the dotted arrow in Figure 1, and the same applies below).

In the vertical direction, the N-type source 18a and the N-type drain 18b are formed below the upper surface 11a and connected to the upper surface 11a. In the channel direction, the drift region of the high-voltage N-type device 10a is located between the N-type drain 18b and the first high-voltage P-type well region 15a, separating the N-type drain 18b from the first high-voltage P-type well region 15a and located in the first high-voltage N-type well region 14a near the upper surface 11a, serving as a drift current channel for the high-voltage N-type device 10a during conduction operation.

The P-type source 19a and the P-type drain 19b are formed in the semiconductor layer 11' of the high-voltage P-type device region HV-PMOS using the same ion implantation process step, and the P-type source 19a and the P-type drain 19b are respectively located in the second high-voltage N-type well region 14b and the second high-voltage P-type well region 15b below the outside of the second gate 17b in the channel direction (as indicated by the direction of the dotted arrow in Figure 1, the same below).

In the vertical direction, the P-type source 19a and the P-type drain 19b are formed below the upper surface 11a and connected to the upper surface 11a, and in the channel direction, the drift region of the high-voltage P-type element 10b is located between the P-type drain 19b and the second high-voltage N-type well region 14b, and separates the P-type drain 19b from the second high-voltage N-type well region 14b, and is located in the second high-voltage P-type well region 15b close to the upper surface 11a, used as a drift current channel for the high-voltage P-type element 10b during the conduction operation.

In one embodiment, the semiconductor layer 11' is a P-type semiconductor epitaxial layer and has a volume resistivity of 45 Ohm-cm.

In one embodiment, the first drift oxide region 16a and the second drift oxide region 16b are chemical vapor deposition (CVD) oxide regions.

In one embodiment, the thickness of the first drift oxide region 16a and the second drift oxide region 16b is between 400Å and 450Å.

In one embodiment, the thickness of the dielectric layer of the first gate 17a and the dielectric layer of the second gate 17b is between 80Å and 100Å.

In one embodiment, the gate driving voltage of the high voltage N-type device 10a in the high voltage N-type device region HV-NMOS is 3.3V.

In one embodiment, the minimum feature size of the HVCMOS device 10 is 0.18 microns.

It should be noted that the so-called inversion current path refers to the region where, during the on-state operation of the high-voltage N-type device 10a/high-voltage P-type device 10b, an inversion layer is formed beneath the gate 17a/gate 17b due to the voltage applied to the gate 17a/gate 17b, allowing the on-state current to flow. This is well known in the art and will not be elaborated on here.

It should be noted that the so-called drift current channel refers to the region where the conduction current of the high-voltage N-type device 10a/high-voltage P-type device 10b drifts during conduction operation. This is well known in the art and will not be elaborated here.

It should be noted that the upper surface 11a does not refer to a completely flat plane, but rather refers to a surface of the semiconductor layer 11'. In this embodiment, for example, the portion of the upper surface 11a where the insulating region 12 contacts the upper surface 11a has a recessed portion.

It should be noted that gates 17a/17b include a conductive layer, a dielectric layer connected to upper surface 11a, and an electrically insulating spacer layer. The conductive layer serves as an electrical contact for gates 17a/17b and is formed on and connected to the dielectric layer. The spacer layer is formed on both sides of the conductive layer to serve as an electrically insulating layer between gates 17a/17b. This is well known in the art and will not be detailed here.

It should be noted that the aforementioned "N-type" and "P-type" refer to the semiconductor component regions (such as but not limited to the aforementioned first high-voltage N-type well region 14a and second high-voltage N-type well region 14b, first high-voltage P-type well region 15a and second high-voltage P-type well region 15b, N-type source 18a and N-type drain 18b, and P-type source 19a and P-type drain 19b) doped with impurities of different conductivity types in the high-voltage complementary metal oxide semiconductor device, making the semiconductor component regions N-type or P-type, wherein N-type and P-type are conductivity types with opposite electrical properties to each other.

It should also be noted that the so-called high-voltage complementary metal oxide semiconductor (HVMOS) device refers to a device whose drift region length is adjusted according to the operating voltage during normal operation, allowing it to operate at a higher specific voltage. This is well known to those skilled in the art and will not be elaborated on here.

FIG2 is a schematic cross-sectional view of a high voltage complementary metal oxide semiconductor device 20 according to another embodiment of the present invention. This embodiment differs from the embodiment of FIG. 1 in that the high-voltage complementary metal oxide semiconductor device 20 of this embodiment further includes a first shallow trench isolation (STI) region 22a, a second shallow trench isolation region 22b, a third shallow trench isolation region 22c, a fourth shallow trench isolation region 22d, an N-type conductive region 29c, a P-type conductive region 28c, a first N-type buried layer 23a, a second N-type buried layer 23b, a first high-voltage N-type isolation region 24c, a second high-voltage N-type isolation region 24d, a first high-voltage P-type isolation region 25c, and a second high-voltage P-type isolation region 25d.

The first shallow trench isolation region 22a, the second shallow trench isolation region 22b, the third shallow trench isolation region 22c, and the fourth shallow trench isolation region 22d are formed, for example, in the same process step as forming the insulating region 12. The first shallow trench isolation region 22a and the third shallow trench isolation region 22c are formed in the high-voltage N-type device region HV-NMOS, while the second shallow trench isolation region 22b and the fourth shallow trench isolation region 22d are formed in the high-voltage P-type device region HV-PMOS. The first shallow trench isolation region 22a is located and connected to the first drift oxide region 16a, and the second shallow trench isolation region 22b is located and connected to the second drift oxide region 16b.

The third shallow trench isolation region 22c is used to electrically isolate the N-type source 18a from the P-type conductive region 29c in the semiconductor layer 11'. The fourth shallow trench isolation region 22d is used to electrically isolate the P-type source 19a from the N-type conductive region 28c in the semiconductor layer 11'.

The P-type conductive region 29c is formed in the semiconductor layer 11' of the high-voltage N-type device region HV-NMOS by, for example, the same ion implantation process as the P-type source 19a and the P-type drain 19b, and serves as an electrical contact of the first high-voltage P-type well region 15a.

The N-type conductive region 28c is formed in the semiconductor layer 11' of the high-voltage P-type device region HV-PMOS by, for example, the same ion implantation process as the N-type source 18a and the N-type drain 18b, and serves as an electrical contact of the second high-voltage N-type well region 14b.

The first N-type buried layer 23a and the second N-type buried layer 23b are formed in the high-voltage N-type device region HV-NMOS and the high-voltage P-type device region HV-PMOS, respectively, using the same process steps. The first N-type buried layer 23a is formed in and connected to the semiconductor layer 11' and the substrate 11 directly below the first high-voltage N-type well region 14a and the first high-voltage P-type well region 15a. The second N-type buried layer 23b is formed in and connected to the semiconductor layer 11' and the substrate 11 directly below the second high-voltage N-type well region 14b and the second high-voltage P-type well region 15b.

The same ion implantation process used to form the first high-voltage N-type well region 14a and the second high-voltage N-type well region 14b forms the first high-voltage N-type isolation region 24c and the second high-voltage N-type isolation region 24d. The same ion implantation process used to form the first high-voltage P-type well region 15a and the second high-voltage P-type well region 15b forms the first high-voltage P-type isolation region 25c and the second high-voltage P-type isolation region 25d.

The first high-voltage N-type isolation region 24c is adjacent to the first high-voltage P-type well region 15a on the other side of the first high-voltage N-type well region 14a in the channel direction. The second high-voltage N-type isolation region 24d is adjacent to the second high-voltage P-type well region 15b on the other side of the second high-voltage N-type well region 14b in the channel direction. The first high-voltage P-type isolation region 25c is adjacent to the first high-voltage N-type well region 14a on the other side of the first high-voltage P-type well region 15a in the channel direction. The second high voltage P-type isolation region 25d is adjacent to the second high voltage N-type well region 14b on the other side of the second high voltage N-type well region 15b in the channel direction.

The first N-type buried layer 23a, the first high-voltage N-type isolation region 24c, and the first high-voltage P-type isolation region 25c cover the exterior of the high-voltage N-type device 20a in the semiconductor layer 11′, thereby electrically isolating the high-voltage N-type device 20a in the semiconductor layer 11′. The second N-type buried layer 23b, the second high-voltage N-type isolation region 24d, and the second high-voltage P-type isolation region 25d cover the exterior of the high-voltage P-type device 20b in the semiconductor layer 11′, thereby electrically isolating the high-voltage P-type device 20b in the semiconductor layer 11′.

The first N-type buried layer 23a and the second N-type buried layer 23b may be formed, for example but not limited to, by implanting N-type conductive impurities into the substrate 11 in the form of accelerated ions during an ion implantation process. The first N-type buried layer 23a and the second N-type buried layer 23b may be formed by thermal diffusion during or after the formation of the semiconductor layer 11'.

Please refer to Figures 3A-3L, which are schematic diagrams illustrating a method for manufacturing a high-voltage complementary metal oxide semiconductor (HVCMOS) device 20 according to one embodiment of the present invention. The HVCMOS device 20 includes a high-voltage N-type device 20a and a high-voltage P-type device 20b. As shown in Figure 3A, a substrate 11 is first provided. N-type conductive impurities are implanted into the substrate 11 in the form of accelerated ions, for example, but not limited to, by an ion implantation process. Subsequently, during or after the formation of the semiconductor layer 11' (as shown in Figure 3B), a first N-type buried layer 23a and a second N-type buried layer 23b are formed by thermal diffusion.

Next, please refer to Figure 3B to form a semiconductor layer 11' on the substrate 11. The semiconductor layer 11' is formed on the substrate 11 by, for example, an epitaxial step, or a portion of the substrate 11 is used as the semiconductor layer 11'. As described above, during or after the process of forming the semiconductor layer 11', the first N-type buried layer 23a and the second N-type buried layer 23b are formed by thermal diffusion. The semiconductor layer 11' has a relative upper surface 11a and a lower surface 11b in the vertical direction (as indicated by the direction of the solid arrow in Figure 3B, the same below). The method of forming the semiconductor layer 11' is well known to those having ordinary knowledge in this field and will not be elaborated here. The substrate 21 is, for example, but not limited to, a P-type or N-type semiconductor substrate.

Next, referring to FIG. 3C , the insulating region 12 , the first shallow trench isolation region 22 a , the second shallow trench isolation region 22 b , the third shallow trench isolation region 22 c , and the fourth shallow trench isolation region 22 d are formed, for example, in the same process step. The insulating region 12 , the first shallow trench isolation region 22 a , the second shallow trench isolation region 22 b , the third shallow trench isolation region 22 c , and the fourth shallow trench isolation region 22 d may be, for example but not limited to, a shallow trench isolation (STI) structure as shown in FIG. 3C .

The plurality of insulating regions 12 are used to define a high-voltage N-type device region (HV-NMOS) and a high-voltage P-type device region (HV-PMOS). A high-voltage N-type device 20a is formed in the HV-NMOS region, and a high-voltage P-type device 20b is formed in the HV-PMOS region. A first shallow trench isolation region 22a and a third shallow trench isolation region 22c are formed in the HV-NMOS region, while a second shallow trench isolation region 22b and a fourth shallow trench isolation region 22d are formed in the HV-PMOS region. The first shallow trench isolation region 22a is located and connected directly below the first drift oxide region 16a, and the second shallow trench isolation region 22b is located and connected directly below the second drift oxide region 16b. The third shallow trench isolation region 22c is used to electrically isolate the N-type source 18a from the P-type conductive region 29c in the semiconductor layer 11′. The fourth shallow trench isolation region 22d is used to electrically isolate the P-type source 19a from the N-type conductive region 28c in the semiconductor layer 11′.

Next, referring to FIG. 3D , a first high voltage N-type well region 14 a , a second high voltage N-type well region 14 b , a first high voltage N-type isolation region 24 c , and a second high voltage N-type isolation region 24 d are formed by the same ion implantation process.

A first high-voltage N-type well region 14a and a second high-voltage N-type well region 14b are formed in the semiconductor layer 11' of the high-voltage N-type device region HV-NMOS and the semiconductor layer 11' of the high-voltage P-type device region HV-PMOS, respectively. Both the first high-voltage N-type well region 14a and the second high-voltage N-type well region 14b are located below and connected to the upper surface 11a. A portion of the first high-voltage N-type well region 14a is located directly below and connected to the gate 17a to provide a drift current path for the high-voltage N-type device 10a during the on-state operation; and a portion of the second high-voltage N-type well region 14b is located directly below the gate 17b to provide a reverse current path for the high-voltage P-type device 10b during the on-state operation.

The first high-voltage N-type isolation region 24c is adjacent to the first high-voltage P-type well region 15a on the other side of the first high-voltage N-type well region 14a in the channel direction. The second high-voltage N-type isolation region 24d is adjacent to the second high-voltage P-type well region 15b on the other side of the second high-voltage N-type well region 14b in the channel direction.

3E , a first high-voltage P-type well region 15 a, a second high-voltage P-type well region 15 b, a first high-voltage P-type isolation region 25 c, and a second high-voltage P-type isolation region 25 d are formed by the same ion implantation process.

The first high-voltage P-type well region 15a and the second high-voltage P-type well region 15b are formed in the semiconductor layer 11' of the high-voltage N-type device region HV-NMOS and the semiconductor layer 11' of the high-voltage P-type device region HV-PMOS, respectively. The first high-voltage N-type well region 14a and the first high-voltage P-type well region 15a are adjacent to each other in the channel direction (as indicated by the dotted arrow in Figure 3E, the same below), and the second high-voltage N-type well region 14b and the second high-voltage P-type well region 15b are adjacent to each other in the channel direction.

Both the first high-voltage P-type well region 15a and the second high-voltage P-type well region 15b are located below and connected to the upper surface 11a. A portion of the first high-voltage P-type well region 15a is located directly below and connected to the gate 17a, providing a reverse current path for the high-voltage N-type device 10a during the on-state operation. Furthermore, a portion of the second high-voltage P-type well region 15b is located directly below the gate 17b, providing a drift current path for the high-voltage P-type device 10b during the on-state operation.

The first high-voltage P-type isolation region 25c is adjacent to the first high-voltage N-type well region 14a on the other side of the first high-voltage P-type well region 15a in the channel direction. The second high-voltage P-type isolation region 25d is adjacent to the second high-voltage N-type well region 14b on the other side of the second high-voltage N-type well region 15b in the channel direction.

The first N-type buried layer 23a, the first high-voltage N-type isolation region 24c, and the first high-voltage P-type isolation region 25c cover the exterior of the high-voltage N-type device 20a in the semiconductor layer 11′, thereby electrically isolating the high-voltage N-type device 20a in the semiconductor layer 11′. The second N-type buried layer 23b, the second high-voltage N-type isolation region 24d, and the second high-voltage P-type isolation region 25d cover the exterior of the high-voltage P-type device 20b in the semiconductor layer 11′, thereby electrically isolating the high-voltage P-type device 20b in the semiconductor layer 11′.

Next, referring to FIG. 3F , a drift oxide layer 16 is formed on the semiconductor layer 11′ by, for example but not limited to, a deposition process step, and the drift oxide layer 16 completely covers the high voltage N-type device region HV-NMOS and the high voltage P-type device region HV-PMOS.

Next, referring to FIG. 3G , the drift oxide layer 16 is etched using the same etching process step to form a first drift oxide region 16a in the high-voltage N-type device region (HV-NMOS) and a second drift oxide region 16b in the high-voltage P-type device region (HV-PMOS). The first drift oxide region 16a and the second drift oxide region 16b are formed on the semiconductor layer 11′ and are located in the drift region of the high-voltage N-type device 10a and the drift region of the high-voltage P-type device 10b, respectively.

Next, referring to FIG. 3H , after the first drift oxide region 16a and the second drift oxide region 16b are formed, a gate dielectric layer 17′ is formed on the semiconductor layer 11′. The gate dielectric layer 17′ covers the high-voltage N-type device region HV-NMOS and the high-voltage P-type device region HV-PMOS.

Next, referring to FIG. 3I , after the gate dielectric layer 17′ is formed, a polysilicon layer 17 is formed on the gate dielectric layer 17′, for example but not limited to, by a deposition process. The polysilicon layer 17 covers the high-voltage N-type device region HV-NMOS and the high-voltage P-type device region HV-PMOS.

3J , after the polysilicon layer 17 is formed, the polysilicon layer 17 is etched using the same etching process to form a first gate 17a in the high voltage N-type device region HV-NMOS and a second gate 17b in the high voltage P-type device region HV-PMOS.

It should be noted that the thickness of the gate dielectric layer 17' is significantly lower than that of the polysilicon layer 17. This serves as a dielectric layer for the first gate 17a and the second gate 17b after the first gate 17a and the second gate 17b are formed. This is well known to those skilled in the art and will not be further elaborated upon here.

The first gate 17a and the second gate 17b are formed on the upper surface 11a of the semiconductor layer 11'. The first gate 17a and the second gate 17b respectively include a conductive layer, a spacer layer and a dielectric layer, wherein the dielectric layer is located on the upper surface 11a and connected to the upper surface 11a. This is well known to those with ordinary knowledge in the art and will not be elaborated here.

Next, referring to FIG. 3K , an N-type source 18a, an N-type drain 18b, and an N-type conductive region 28c are formed using the same ion implantation process. The N-type source 18a and the N-type drain 18b are formed in the semiconductor layer 11′ of the high-voltage N-type device region HV-NMOS. The N-type source 18a and the N-type drain 18b are located, respectively, within the first high-voltage P-type well 15a and the first high-voltage N-type well 14a, below and outside the first gate 17a in the channel direction (as indicated by the dashed arrows in FIG. 3K , and the same applies hereinafter).

In the vertical direction, the N-type source 18a and the N-type drain 18b are formed below the upper surface 11a and connected to the upper surface 11a. In the channel direction, the drift region of the high-voltage N-type device 10a is located between the N-type drain 18b and the first high-voltage P-type well region 15a, separating the N-type drain 18b from the first high-voltage P-type well region 15a and located in the first high-voltage N-type well region 14a near the upper surface 11a, serving as a drift current channel for the high-voltage N-type device 10a during conduction operation.

The N-type conductive region 28c is formed in the semiconductor layer 11' of the high voltage P-type device region HV-PMOS and serves as an electrical contact of the second high voltage N-type well region 14b.

Next, referring to FIG. 3L , a P-type source 19a, a P-type drain 19b, and a P-type conductive region 29c are formed using the same ion implantation process. P-type source 19a and P-type drain 19b are located, respectively, within the second high-voltage N-type well 14b and second high-voltage P-type well 15b, located below and outside the second gate 17b in the channel direction (as indicated by the dashed arrows in FIG. 3L , and the same applies below).

In the vertical direction, the P-type source 19a and the P-type drain 19b are formed below the upper surface 11a and connected to the upper surface 11a, and in the channel direction, the drift region of the high-voltage P-type element 10b is located between the P-type drain 19b and the second high-voltage N-type well region 14b, and separates the P-type drain 19b from the second high-voltage N-type well region 14b, and is located in the second high-voltage P-type well region 15b close to the upper surface 11a, used as a drift current channel for the high-voltage P-type element 10b during the conduction operation.

The P-type conductive region 29c is formed in the semiconductor layer 11' of the high voltage N-type device region HV-NMOS and serves as an electrical contact of the first high voltage P-type well region 15a.

The present invention has been described above with respect to the preferred embodiments. However, the above description is only for those familiar with the present technology to easily understand the content of the present invention, and is not used to limit the scope of the rights of the present invention. Under the same spirit of the present invention, those familiar with the present technology can think of various equivalent changes. For example, other process steps or structures can be added without affecting the main characteristics of the component, such as lightly doped drain regions, etc.; for example, lithography technology is not limited to mask technology, but can also include electron beam lithography technology. All of these can be derived by analogy based on the teachings of the present invention. In addition, the various embodiments described are not limited to individual applications, but can also be applied in combination, for example, but not limited to using two embodiments together. Therefore, the scope of the present invention should cover the above and all other equivalent changes. Furthermore, any embodiment of the present invention does not necessarily need to achieve all objects or advantages, and thus, any of the claimed patent scopes should not be limited thereby.

10, 20: High-voltage complementary metal oxide semiconductor device 10a, 20a: High-voltage N-type device 10b, 20b: High-voltage P-type device 11: Substrate 11': Semiconductor layer 11a: Top surface 11b: Bottom surface 12: Insulating region 13a: First N-type buried layer 13b: Second N-type buried layer 14a: First high-voltage N-type well region 14b: Second high-voltage N-type well region 14c: First high-voltage N-type isolation region 14d: Second high-voltage N-type isolation region 15a: First high-voltage P-type well region 15b: Second high-voltage P-type well region 15c: First high-voltage P-type isolation region 15d: Second high-voltage P-type isolation region 16: Drift oxide layer 16a: First drift oxide region 16b: Second drift oxide region 17: Polysilicon layer 17a: First gate 17b: Second gate 17': Gate dielectric layer 18a: N-type source 18b: N-type drain 18c: N-type conductive region 19a: P-type source 19b: P-type drain 19c: P-type conductive region 22a: First shallow trench isolation 22b: Second shallow trench isolation 22c: Third shallow trench isolation region 22d: Fourth shallow trench isolation region 23a: First N-type buried layer 23b: Second N-type buried layer 24c: First high-voltage N-type isolation region 24d: Second high-voltage N-type isolation region 25c: First high-voltage P-type isolation region 25d: Second high-voltage P-type isolation region 28c: P-type conductive region 29c: N-type conductive region HV-NMOS: High-voltage N-type device region HV-PMOS: High-voltage P-type device region

FIG1 is a schematic cross-sectional view of a high-voltage complementary metal oxide semiconductor device according to one embodiment of the present invention.

FIG2 is a schematic cross-sectional view of a high-voltage complementary metal oxide semiconductor device according to an embodiment of the present invention.

3A-3L are cross-sectional schematic diagrams showing a method for manufacturing a high-voltage complementary metal oxide semiconductor device according to an embodiment of the present invention.

10: High voltage complementary metal oxide semiconductor device

10a: High voltage N-type device

10b: High voltage P-type device

11:Substrate

11’: Semiconductor layer

11a: Upper surface

11b: Lower surface

12: Insular Zone

14a: First high-voltage N-type well area

14b: Second high-voltage N-type well area

15a: First high-pressure P-type well area

15b: Second high-voltage P-type well area

16a: First drift oxidation zone

16b: Second drift oxide region

17a: First Gate

17b: Second gate

18a: N-type source

18b: N-type drain

19a: P-type source

19b: P-type drain

HV-NMOS: High Voltage N-Type MOSFET

HV-PMOS: High Voltage P-Type MOSFET

Claims (20)

A high-voltage complementary metal oxide semiconductor (CMOS) device comprises: A semiconductor layer formed on a substrate; A plurality of insulating regions formed on the semiconductor layer to define a high-voltage N-type device region and a high-voltage P-type device region, wherein a high-voltage N-type device is formed in the high-voltage N-type device region, and a high-voltage P-type device is formed in the high-voltage P-type device region; A first high-voltage N-type well region and a second high-voltage N-type well region are formed in the semiconductor layer in the high-voltage N-type device region and the semiconductor layer in the high-voltage P-type device region, respectively, using the same ion implantation process step; A first high-voltage P-type well region and a second high-voltage P-type well region are formed in the semiconductor layer of the high-voltage N-type device region and the semiconductor layer of the high-voltage P-type device region, respectively, using the same ion implantation process step, wherein the first high-voltage N-type well region and the first high-voltage P-type well region are adjacent to each other in a channel direction, and the second high-voltage N-type well region and the second high-voltage P-type well region are adjacent to each other in the channel direction; A first drift oxide region and a second drift oxide region are formed in the high-voltage N-type device region and the high-voltage P-type device region, respectively, by etching a drift oxide layer using the same etching process step; A first gate and a second gate are formed by etching a polysilicon layer using the same etching process step, and the first gate and the second gate are formed in the high-voltage N-type device region and the high-voltage P-type device region, respectively; An N-type source and an N-type drain are formed in the semiconductor layer of the high-voltage N-type device region using the same ion implantation process step, and the N-type source and the N-type drain are respectively located in the first high-voltage P-type well region and the first high-voltage N-type well region below the exterior of the first gate; and A P-type source and a P-type drain are formed in the semiconductor layer of the high-voltage P-type device region using the same ion implantation process step, and the P-type source and the P-type drain are respectively located in the second high-voltage N-type well region and the second high-voltage P-type well region below the exterior of the second gate. The high-voltage complementary metal oxide semiconductor device as described in claim 1 further includes: a first shallow trench isolation (STI) region and a second shallow trench isolation region, which are respectively formed in the high-voltage N-type device region and the high-voltage P-type device region using the same process steps, wherein the first shallow trench isolation region is located and connected to directly below the first drift oxide region, and the second shallow trench isolation region is located and connected to directly below the second drift oxide region. The high-voltage complementary metal oxide semiconductor device of claim 1 further comprises: An N-type conductive region formed in the second high-voltage N-type well region by the same ion implantation process step as that used to form the N-type source and the N-type drain, wherein the N-type conductive region is an electrical contact to the second high-voltage N-type well region; and A P-type conductive region formed in the first high-voltage P-type well region by the same ion implantation process step as that used to form the P-type source and the P-type drain, wherein the P-type conductive region is an electrical contact to the first high-voltage P-type well region. The high-voltage complementary metal oxide semiconductor device of claim 1 further comprises: A first N-type buried layer and a second N-type buried layer, formed in the high-voltage N-type device region and the high-voltage P-type device region, respectively, using the same process steps; The first N-type buried layer is formed in and connected to the semiconductor layer and the substrate directly below the first high-voltage N-type well region and the first high-voltage P-type well region; The second N-type buried layer is formed in and connected to the semiconductor layer and the substrate directly below the second high-voltage N-type well region and the second high-voltage P-type well region. The high-voltage complementary metal oxide semiconductor device as described in claim 1 further comprises: a first high-voltage N-type isolation region and a second high-voltage N-type isolation region formed by the same ion implantation process step as the first high-voltage N-type well region and the second high-voltage N-type well region; and a first high-voltage P-type isolation region and a second high-voltage P-type isolation region formed by the same ion implantation process step as the first high-voltage P-type well region and the second high-voltage P-type well region; wherein the first high-voltage N-type isolation region is adjacent to the other side of the first high-voltage P-type well region than to the first high-voltage N-type well region in the channel direction; The second high-voltage N-type isolation region is adjacent to the second high-voltage P-type well region on the other side thereof adjacent to the second high-voltage N-type well region in the channel direction. The first high-voltage P-type isolation region is adjacent to the first high-voltage N-type well region on the other side thereof adjacent to the first high-voltage P-type well region in the channel direction. The second high-voltage P-type isolation region is adjacent to the second high-voltage N-type well region on the other side thereof adjacent to the second high-voltage N-type well region in the channel direction. The high-voltage complementary metal oxide semiconductor device as claimed in claim 1, wherein the semiconductor layer is a P-type semiconductor epitaxial layer and has a volume resistivity of 45 Ohm-cm. The high-voltage complementary metal oxide semiconductor device as described in claim 1, wherein the thickness of the first drift oxide region and the second drift oxide region is between 400Å and 450Å. The high-voltage complementary metal oxide semiconductor device of claim 1, wherein the thickness of the dielectric layer of the first gate and the dielectric layer of the second gate are between 80Å and 100Å. A high-voltage complementary metal oxide semiconductor device as described in claim 1, wherein the gate drive voltage of the high-voltage N-type device is 3.3V. The high-voltage complementary metal oxide semiconductor device as claimed in claim 1, wherein the minimum feature size of the high-voltage complementary metal oxide semiconductor device is 0.18 microns. A method for fabricating a high-voltage complementary metal oxide semiconductor (CMOS) device, wherein the high-voltage complementary metal oxide semiconductor device includes a high-voltage N-type device and a high-voltage P-type device. The method comprises: forming a semiconductor layer on a substrate; forming a plurality of insulating regions on the semiconductor layer to define a high-voltage N-type device region and a high-voltage P-type device region, wherein the high-voltage N-type device is formed in the high-voltage N-type device region, and the high-voltage P-type device is formed in the high-voltage P-type device region; Forming a first high-voltage N-type well region in the semiconductor layer of the high-voltage N-type device region and a second high-voltage N-type well region in the semiconductor layer of the high-voltage P-type device region using the same ion implantation process step; Forming a first high-voltage P-type well region in the semiconductor layer of the high-voltage N-type device region and a second high-voltage P-type well region in the semiconductor layer of the high-voltage P-type device region using the same ion implantation process step, wherein the first high-voltage N-type well region and the first high-voltage P-type well region are adjacent to each other in a channel direction, and the second high-voltage N-type well region and the second high-voltage P-type well region are adjacent to each other in the channel direction; A drift oxide layer is formed on the semiconductor layer, the drift oxide layer covering the high-voltage N-type device region and the high-voltage P-type device region. The drift oxide layer is etched using the same etching process steps to form a first drift oxide region in the high-voltage N-type device region and a second drift oxide region in the high-voltage P-type device region. After the first drift oxide region and the second drift oxide region are formed, a gate dielectric layer is formed on the semiconductor layer, the gate dielectric layer covering the high-voltage N-type device region and the high-voltage P-type device region. Forming a polysilicon layer on the gate dielectric layer, the polysilicon layer covering the high-voltage N-type device region and the high-voltage P-type device region; Etching the polysilicon layer using a single etching process step to form a first gate in the high-voltage N-type device region and a second gate in the high-voltage P-type device region; Forming an N-type source and an N-type drain in the semiconductor layer of the high-voltage N-type device region using a single ion implantation process step, with the N-type source and the N-type drain being located in the first high-voltage P-type well region and the first high-voltage N-type well region, respectively, below the exterior of the first gate; and A P-type source and a P-type drain are formed in the semiconductor layer of the high-voltage P-type device region using the same ion implantation process step. The P-type source and the P-type drain are respectively located in the second high-voltage N-type well region and the second high-voltage P-type well region below the exterior of the second gate. The method for manufacturing a high-voltage complementary metal oxide semiconductor device as described in claim 11 further includes: forming a first shallow trench isolation (STI) region in the high-voltage N-type device region and a second shallow trench isolation region in the high-voltage P-type device region using the same process steps, wherein the first shallow trench isolation region is located and connected to directly below the first drift oxide region, and the second shallow trench isolation region is located and connected to directly below the second drift oxide region. The high-voltage complementary metal oxide semiconductor device manufacturing method of claim 11 further comprises: forming an N-type conductive region in the second high-voltage N-type well region by the same ion implantation process step as that used to form the N-type source and the N-type drain, wherein the N-type conductive region serves as an electrical contact to the second high-voltage N-type well region; and forming a P-type conductive region in the first high-voltage P-type well region by the same ion implantation process step as that used to form the P-type source and the P-type drain, wherein the P-type conductive region serves as an electrical contact to the first high-voltage P-type well region. The method for manufacturing a high-voltage complementary metal oxide semiconductor device as described in claim 11 further comprises: forming a first N-type buried layer and a second N-type buried layer in the same process step, wherein the first N-type buried layer is located in the high-voltage N-type device region, and the second N-type buried layer is located in the high-voltage P-type device region; wherein the first N-type buried layer is formed in the semiconductor layer and the substrate directly below the first high-voltage N-type well region and the first high-voltage P-type well region; wherein the second N-type buried layer is formed in the semiconductor layer and the substrate directly below the second high-voltage N-type well region and the second high-voltage P-type well region. The high-voltage complementary metal oxide semiconductor device manufacturing method of claim 11 further comprises: forming a first high-voltage N-type isolation region and a second high-voltage N-type isolation region by performing the same ion implantation process step as that used to form the first high-voltage N-type well region and the second high-voltage N-type well region; and forming a first high-voltage P-type isolation region and a second high-voltage P-type isolation region by performing the same ion implantation process step as that used to form the first high-voltage P-type well region and the second high-voltage P-type well region; wherein the first high-voltage N-type isolation region is adjacent to the other side of the first high-voltage P-type isolation region than to the first high-voltage N-type well region in the channel direction; The second high-voltage N-type isolation region is adjacent to the second high-voltage P-type well region on the other side thereof adjacent to the second high-voltage N-type well region in the channel direction. The first high-voltage P-type isolation region is adjacent to the first high-voltage N-type well region on the other side thereof adjacent to the first high-voltage P-type well region in the channel direction. The second high-voltage P-type isolation region is adjacent to the second high-voltage N-type well region on the other side thereof adjacent to the second high-voltage N-type well region in the channel direction. The method for manufacturing a high-voltage complementary metal oxide semiconductor device as described in claim 11, wherein the semiconductor layer is a P-type semiconductor epitaxial layer and has a volume resistivity of 45 Ohm-cm. The method for manufacturing a high-voltage complementary metal oxide semiconductor device as described in claim 11, wherein the thickness of the first drift oxide region and the second drift oxide region is between 400Å and 450Å. The method for manufacturing a high-voltage complementary metal oxide semiconductor device as described in claim 11, wherein the thickness of the dielectric layer of the first gate and the dielectric layer of the second gate are between 80Å and 100Å. A method for manufacturing a high-voltage complementary metal oxide semiconductor device as described in claim 11, wherein the gate drive voltage of the high-voltage N-type device is 3.3V. A method for manufacturing a high-voltage complementary metal oxide semiconductor device as described in claim 11, wherein the minimum feature size of the high-voltage complementary metal oxide semiconductor device is 0.18 microns.