TWI861496B - Nmos half-bridge power device and manufacturing method thereof - Google Patents

Abstract

The present invention provides an NMOS half-bridge power device and a manufacturing method thereof. The NMOS half-bridge power device includes: a semiconductor layer, a plurality of insulation regions, a first high voltage N-type well and a second high voltage N-type well, which are formed by one same ion implantation process step, a first high voltage P-type well and a second high voltage P-type well, which are formed by one same ion implantation process step, a first drift oxided region and a second oxide region, which are formed by one same etch process step by etching a drift oxide layer; a first gate and a second gate, which are formed by one same etch process step by etching a poly silicon layer, a first P-type body region and a second P-type body region, which are formed by one same ion implantation process step, a first N-type source and a first N-type drain, and a second N-type source and a second N-type drain.

Description

NMOS half-bridge power device and manufacturing method thereof

The present invention relates to an NMOS half-bridge power device and a manufacturing method thereof, and in particular to an NMOS half-bridge power device integrating an NMOS upper bridge device and an NMOS lower bridge device and a manufacturing method thereof.

It is known that a buck power stage circuit includes a half-bridge power element composed of an upper bridge power element and a lower bridge power element. The upper bridge power element and the lower bridge power element are formed by independent process steps, so that the application range is limited and there is a problem of high manufacturing cost.

In view of this, the present invention proposes a method for integrating an NMOS upper bridge element and an NMOS lower bridge element into a same substrate through an integration process to form an NMOS half-bridge power element and a manufacturing method thereof.

In one aspect, the present invention provides an NMOS half-bridge power device comprising: a semiconductor layer formed on a substrate; a plurality of insulating regions formed on the semiconductor layer to define an NMOS upper bridge device region and an NMOS lower bridge device region, wherein an NMOS upper bridge device is formed in the NMOS upper bridge device region, and an NMOS lower bridge device is formed in the NMOS lower bridge device region; a first N-type buried layer formed in the NMOS upper bridge device region; A first high voltage N-type isolation region and a second high voltage N-type isolation region are formed in the semiconductor layer of the NMOS upper bridge component region by the same ion implantation process step; a first high voltage N-type well region and a second high voltage N-type well region are formed in the semiconductor layer of the NMOS upper bridge component region and the NMOS lower bridge component region by the same ion implantation process step. a first high voltage P-type well region and a second high voltage P-type well region, respectively formed in the semiconductor layer of the NMOS upper bridge component region and the semiconductor layer of the NMOS lower bridge component region by the same ion implantation process step, wherein the first high voltage N-type well region and the first high voltage P-type well region are adjacent in a channel direction, and the second high voltage N-type well region is adjacent to the first high voltage P-type well region in a channel direction. The first drift oxide region and the second high voltage P-type well region are adjacent to each other in the channel direction; a first drift oxide region and a second drift oxide region are formed by etching a drift oxide layer in the same etching process step, and the first drift oxide region and the second drift oxide region are formed in the NMOS upper bridge component region and the NMOS lower bridge component region respectively; a first gate and a second gate are formed in the same The polysilicon layer is etched in an etching process step to form the first gate and the second gate in the NMOS upper bridge component region and the NMOS lower bridge component region respectively; a first P-type body region and a second P-type body region are formed in the semiconductor layer of the NMOS upper bridge component region and the semiconductor layer of the NMOS lower bridge component region respectively by the same ion implantation process step. In the conductor layer, part of the first P-type body region is located directly below the first gate, and the first P-type body region is adjacent to the first high-voltage N-type well region in the channel direction, part of the second P-type body region is located directly below the second gate, and the second P-type body region is adjacent to the second high-voltage N-type well region in the channel direction; a first N-type source and a first N The first N-type drain is formed in the semiconductor layer of the NMOS upper bridge element region by the same ion implantation process step, and the first N-type source and the first N-type drain are respectively located in the first P-type body region and the first high-voltage N-type well region below the outside of the first gate; and a second N-type source and a second N-type drain are connected to the first N-type source and the first The N-type drain is formed in the semiconductor layer of the NMOS lower bridge element region by the same ion implantation process step, and the second N-type source and the second N-type drain are respectively located in the second P-type body region and the second high-voltage N-type well region below the outside of the second gate; wherein the first N-type buried layer is formed in and connected to the first high-voltage N-type well region and the first high-voltage P The semiconductor layer and the substrate are directly below the first high-voltage N-type well region; wherein the first high-voltage N-type isolation region is adjacent to the other side of the first high-voltage N-type well region adjacent to the first high-voltage P-type well region in the channel direction; wherein the second high-voltage N-type isolation region is adjacent to the other side of the first high-voltage P-type well region adjacent to the first high-voltage N-type well region in the channel direction.

In another aspect, the present invention provides a method for manufacturing an NMOS half-bridge power device, wherein the NMOS half-bridge power device includes an NMOS upper bridge device and an NMOS lower bridge device, and the method for manufacturing the NMOS half-bridge power device includes: forming a semiconductor layer on a substrate; forming a plurality of insulating regions on the semiconductor layer to define an NMOS upper bridge device region and an NMOS lower bridge device region, wherein the NMOS upper bridge device is formed in the NMOS upper bridge device region, and the NMOS lower bridge device is formed in the NMOS lower bridge device region; forming a first N-type buried layer in the NMOS upper bridge device region; A first high voltage N-type isolation region and a second high voltage N-type isolation region are formed in the semiconductor layer of the NMOS upper bridge component region by the same ion implantation process step; a first high voltage N-type well region is formed in the semiconductor layer of the NMOS upper bridge component region and a second high voltage N-type well region is formed in the semiconductor layer of the NMOS lower bridge component region by the same ion implantation process step; A first high voltage P-type well region is formed in the semiconductor layer of the NMOS upper bridge element region, and a second high voltage P-type well region is formed in the semiconductor layer of the NMOS lower bridge element region, wherein the first high voltage N-type well region is adjacent to the first high voltage P-type well region in a channel direction, and the second high voltage N-type well region is adjacent to the second high voltage P-type well region in the channel direction; a drift oxide layer is formed in the semiconductor layer The drift oxide layer covers the NMOS upper bridge component region and the NMOS lower bridge component region; the drift oxide layer is etched by the same etching process step to form a first drift oxide region in the NMOS upper bridge component region and a second drift oxide region in the NMOS lower bridge component region; after the first drift oxide region and the second drift oxide region are formed, a gate dielectric layer is formed on the semiconductor layer. The gate dielectric layer covers the NMOS upper bridge component region and the NMOS lower bridge component region; a polysilicon layer is formed on the gate dielectric layer, the polysilicon layer covers the NMOS upper bridge component region and the NMOS lower bridge component region; the polysilicon layer is etched by the same etching process step to form a first gate in the NMOS upper bridge component region and a second gate in the NMOS lower bridge component region; The same ion implantation process step forms a first P-type body region and a second P-type body region in the semiconductor layer of the NMOS upper bridge component region and the semiconductor layer of the NMOS lower bridge component region, respectively, wherein a portion of the first P-type body region is located directly below the first gate, and the first P-type body region is adjacent to the first high-voltage N-type well region in the channel direction, and a portion of the second P-type body region is located in the first high-voltage N-type well region. The second gate is directly below the second P-type body region and the second high-voltage N-type well region is adjacent to the channel direction; a first N-type source and a first N-type drain are formed in the semiconductor layer of the NMOS bridge element region by the same ion implantation process step, and the first N-type source and the first N-type drain are respectively located in the first high-voltage P-type body region and the first high-voltage N-type well region below the outside of the first gate. and forming a second N-type source and a second N-type drain in the semiconductor layer of the NMOS lower bridge element region by the same ion implantation process step as the first N-type source and the first N-type drain, and the second N-type source and the second N-type drain are respectively located in the P-type body region and the second high-voltage N-type well region below the outside of the second gate, wherein the first N-type buried layer is formed in and connected to the The semiconductor layer and the substrate are directly below the first high-voltage N-type well region and the first high-voltage P-type well region; wherein the first high-voltage N-type isolation region is adjacent to the other side of the first high-voltage N-type well region in the channel direction relative to the first high-voltage P-type well region; wherein the second high-voltage N-type isolation region is adjacent to the other side of the first high-voltage P-type well region in the channel direction relative to the first high-voltage N-type well region.

In one embodiment, the NMOS half-bridge power element further includes: a first P-type conductive region formed in the first P-type body region, wherein the first P-type conductive region is an electrical contact of the first P-type body region; and a second P-type conductive region formed in the second P-type body region by the same ion implantation process step as that for forming the first P-type conductive region, wherein the second P-type conductive region is an electrical contact of the second P-type body region.

In one embodiment, the NMOS half-bridge power device further comprises: a second N-type buried layer formed in the NMOS lower bridge device region; and a third high-voltage N-type isolation region and a fourth high-voltage N-type isolation region formed in the semiconductor layer of the NMOS lower bridge device region by the same ion implantation process step as the first high-voltage N-type isolation region and the second high-voltage N-type isolation region; wherein the second N-type buried layer is formed in parallel The semiconductor layer and the substrate are connected to the second high voltage N-type well region and the second high voltage P-type well region directly below; wherein the third high voltage N-type isolation region is adjacent to the other side of the second high voltage N-type well region adjacent to the second high voltage P-type well region in the channel direction; wherein the fourth high voltage N-type isolation region is adjacent to the other side of the second high voltage P-type well region adjacent to the second high voltage N-type well region in the channel direction.

In one embodiment, in the NMOS half-bridge power device, the first N-type source, the first P-type conductive region and the second N-type drain are electrically connected.

In one embodiment, the first gate of the NMOS bridge element has a gate length of 0.75 μm, and the length of the portion of the first gate covering the first drift oxide region is 0.3 μm.

In one embodiment, the second gate of the NMOS bottom bridge element has a gate length of 0.6 μm, and the length of the portion of the second gate covering the second drift oxide region is 0.2 μm.

In one embodiment, the semiconductor layer is a P-type semiconductor epitaxial layer and has a volume resistivity of 45 Ohm-cm.

In one embodiment, the thickness of the first drift oxide region and the second drift oxide region is between 400Å and 450Å.

In one embodiment, the thickness of the first gate dielectric layer and the second gate dielectric layer is between 80Å and 100Å.

In one embodiment, the gate drive voltage of the NMOS bridge device region is 3.3V, and the first N-type drain is electrically connected to 12V to 16V.

In one embodiment, the minimum feature size of the NMOS half-bridge power device is 0.18 microns.

The advantage of the present invention is that the present invention can adopt the same process steps to simultaneously form different units in the NMOS upper bridge element and the NMOS lower bridge element of the NMOS half-bridge power element.

Another advantage of the present invention is to form an isolation region to electrically isolate the NMOS upper bridge element from the NMOS lower bridge element in the semiconductor layer.

The following detailed description is based on specific embodiments to make it easier to understand the purpose, technical content, features and effects of the present invention.

The above-mentioned other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the drawings. The drawings in the present invention are schematic, mainly intended to show the process steps and the upper and lower order relationship between the layers, and the shapes, thicknesses and widths are not drawn according to scale.

Please refer to FIG. 1, which shows a cross-sectional schematic diagram of an NMOS half-bridge power device 10 according to an embodiment of the present invention. As shown in FIG. 1, the NMOS half-bridge power device 10 includes: a semiconductor layer 11', a plurality of insulating regions 12, a first N-type buried layer 13a, a first high-voltage N-type isolation region 14c and a second high-voltage N-type isolation region 14d formed by the same ion implantation process step, a first high-voltage N-type well region 14a and a second high-voltage N-type well region 14b formed by the same ion implantation process step, a first high-voltage P-type well region 15a and a second high-voltage P-type well region 15b formed by the same ion implantation process step, 5b, a first drift oxide region 16a and a second drift oxide region 16b formed by etching a drift oxide layer using the same etching process step, a first gate 17a and a second gate 17b formed by etching a polysilicon layer using the same etching process step, a first P-type body region 19a and a second P-type body region 19b formed by the same ion implantation process step, a first N-type source 18a and a first N-type drain 18b, and a second N-type source 18c and a second N-type drain 18d formed by the same ion implantation process step.

The semiconductor layer 11' is formed on the substrate 11. The semiconductor layer 11' has an upper surface 11a and a lower surface 11b in a vertical direction (as indicated by the solid arrow in FIG. 1, the same below). The substrate 11 is, for example but not limited to, a P-type or N-type semiconductor substrate. The semiconductor layer 11' is formed on the substrate 11, for example, by an epitaxial step, or a portion of the substrate 11 is used as the semiconductor layer 11'. The method of forming the semiconductor layer 11' is well known to those having ordinary knowledge in the art and will not be described in detail here.

Please continue to refer to FIG. 1 . A plurality of insulating regions 12 are formed on the semiconductor layer 11 ′. The plurality of insulating regions 12 are used to define an NMOS upper bridge device region HS-NMOS and an NMOS lower bridge device region LS-NMOS, wherein an NMOS upper bridge device 10a is formed in the NMOS upper bridge device region HS-NMOS, and an NMOS lower bridge device 10b is formed in the NMOS lower bridge device region LS-NMOS. The insulating region 12 is, for example but not limited to, a shallow trench isolation (STI) structure as shown in FIG. 1 .

In this embodiment, the NMOS bridge element 10a includes: a first N-type buried layer 13a, a first high-voltage N-type isolation region 14c, a second high-voltage N-type isolation region 14d, a first high-voltage N-type well region 14a, a first high-voltage P-type well region 15a, a first drift oxide region 16a, a first gate 17a, a first N-type source 18a, a first N-type drain 18b, a first P-type body region 19a and a first P-type conductive region 19c. The NMOS lower bridge element 10b includes a second high voltage N-type well region 14b, a second high voltage P-type well region 15b, a second drift oxide region 16b, a second gate 17b, a second N-type source 18c, a second N-type drain 18d, a second P-type body region 19b and a second P-type conductive region 19d.

Please continue to refer to Figure 1. The first N-type buried layer 13a is formed in the NMOS bridge element region HS-NMOS. The first N-type buried layer 13a is formed in the semiconductor layer 11' and the substrate 11 directly below the first high-voltage N-type well region 14a and the first high-voltage P-type well region 15a. The first high-voltage N-type isolation region 14c and the second high-voltage N-type isolation region 14d are formed in the semiconductor layer of the NMOS bridge element region by the same ion implantation process step. The first high-voltage N-type isolation region 14c is adjacent to the other side of the first high-voltage N-type well region 14a in the channel direction relative to the side adjacent to the first high-voltage P-type well region 15a. The second high voltage N-type isolation region 14d is adjacent to the other side of the first high voltage P-type well region 15a in the channel direction relative to the side adjacent to the first high voltage N-type well region 14a. The first N-type buried layer 13a, the first high voltage N-type isolation region 14c and the second high voltage N-type isolation region 14d form a device isolation region, which completely surrounds the NMOS upper bridge component 10a below the upper surface 11a of the semiconductor layer 11', so as to electrically isolate the NMOS upper bridge component 10a from other components (such as the NMOS lower bridge component 10b) formed in the semiconductor layer 11' below the upper surface 11a.

Please continue to refer to FIG. 1. The first high-voltage N-type well region 14a and the second high-voltage N-type well region 14b are formed in the semiconductor layer 11' of the NMOS upper bridge component region HS-NMOS and the semiconductor layer 11' of the NMOS lower bridge component region LS-NMOS respectively by the same ion implantation process step. The first high-voltage N-type well region 14a and the second high-voltage N-type well region 14b are both located below the upper surface 11a and connected to the upper surface 11a. A portion of the first high voltage N-type well region 14a is located directly below the gate 17a and connected to the gate 17a to provide a drift current channel for the NMOS upper bridge element 10a during the conduction operation; and a portion of the second high voltage N-type well region 14b is located directly below the gate 17b to provide a drift current channel for the NMOS lower bridge element 10b during the conduction operation.

Please continue to refer to FIG. 1. The first high voltage P-type well region 15a and the second high voltage P-type well region 15b are formed in the semiconductor layer 11' of the NMOS upper bridge component region HS-NMOS and the semiconductor layer 11' of the NMOS lower bridge component region LS-NMOS respectively by the same ion implantation process step, wherein the first high voltage N-type well region 14a and the first high voltage P-type well region 15a are adjacent in the channel direction (as indicated by the dashed arrow direction in FIG. 1, the same below), and the second high voltage N-type well region 14b and the second high voltage P-type well region 15b are adjacent in the channel direction. The first high voltage P-type well region 15a and the second high voltage P-type well region 15b are both located below the upper surface 11a and connected to the upper surface 11a.

The first drift oxide region 16a and the second drift oxide region 16b are formed by etching the drift oxide layer in the same etching process step, and the first drift oxide region 16a and the second drift oxide region 16b are formed in the NMOS upper bridge device region HS-NMOS and the NMOS lower bridge device region LS-NMOS, respectively. The first drift oxide region 16a and the second drift oxide region 16b are formed on the semiconductor layer 11' and are located on the drift region of the NMOS upper bridge device 10a and the drift region of the NMOS lower bridge device 10b, respectively.

The first gate 17a and the second gate 17b are formed by etching a polysilicon layer in the same etching process step, and the first gate 17a and the second gate 17b are formed in the NMOS upper bridge device region HS-NMOS and the NMOS lower bridge device region LS-NMOS respectively.

The first gate 17a and the second gate 17b are formed on the upper surface 11a of the semiconductor layer 11'. The first gate 17a and the second gate 17b respectively include a conductive layer, a spacer layer and a dielectric layer, wherein the dielectric layer is located on the upper surface 11a and connected to the upper surface 11a. This is well known to those having ordinary knowledge in the art and will not be elaborated here.

Please continue to refer to Figure 1. The first P-type body region 19a and the second P-type body region 19b are respectively formed in the semiconductor layer 11' of the NMOS upper bridge component region HS-NMOS and the semiconductor layer 11' of the NMOS lower bridge component region LS-NMOS by the same ion implantation process steps, wherein the first P-type body region 19a is adjacent to the first high-voltage N-type well region 14a in the channel direction, and the second P-type body region 19b is adjacent to the second high-voltage N-type well region 14b in the channel direction.

A portion of the first P-type body region 19a is located directly below the first gate 17a and connected to the first gate 17a to provide a reverse current channel for the NMOS upper bridge element 10a during the conduction operation; and a portion of the second P-type body region 19b is located directly below the second gate 17b and connected to the second gate 17b to provide a reverse current channel for the NMOS lower bridge element 10b during the conduction operation.

The first N-type source 18a and the first N-type drain 18b are formed in the semiconductor layer 11' of the NMOS bridge element region HS-NMOS by the same ion implantation process step, and the first N-type source 18a and the first N-type drain 18b are respectively located in the first P-type body region 19a and the first high-voltage N-type well region 14a outside and below the first gate 17a in the channel direction (as indicated by the direction of the dotted arrow in FIG. 1 , the same below).

In the vertical direction, the first N-type source 18a and the first N-type drain 18b are formed under the upper surface 11a and connected to the upper surface 11a, and in the channel direction, the drift region of the NMOS bridge element 10a is located between the first N-type drain 18b and the first P-type body region 19a, and separates the first N-type drain 18b and the first P-type body region 19a, and is located in the first high-voltage N-type well region 14a close to the upper surface 11a, and is used as a drift current channel of the NMOS bridge element 10a in the conduction operation.

The second N-type source 18c and the second N-type drain 18d are formed in the semiconductor layer 11' of the NMOS lower bridge element region LS-NMOS by the same ion implantation process step, and the second N-type source 18c and the second N-type drain 18d are respectively located in the second P-type body region 19b and the second high-voltage N-type well region 14b outside and below the second gate 17b in the channel direction (as indicated by the direction of the dotted arrow in FIG. 1 , the same below).

In the vertical direction, the second N-type source 18c and the second N-type drain 18d are formed under the upper surface 11a and connected to the upper surface 11a, and in the channel direction, the drift region of the NMOS lower bridge element 10b is located between the second N-type drain 18d and the second P-type body region 19b, and separates the second N-type drain 18d and the second P-type body region 19b, and is located in the second high-voltage N-type well region 14b close to the upper surface 11a, and is used as a drift current channel for the NMOS lower bridge element 10b in the conduction operation.

As shown in Fig. 1, the first P-type conductive region 19c is formed in the first P-type body region 19a, wherein the first P-type conductive region 19c is an electrical contact of the first P-type body region 19a. The second P-type conductive region 19d is formed in the second P-type body region 19b by the same ion implantation process step as that for forming the first P-type conductive region 19c, wherein the second P-type conductive region 19d is an electrical contact of the second P-type body region 19b.

The first P-type conductive region 19c and the second P-type conductive region 19d are formed under the upper surface 11a and connected to the upper surface 11a, and in the channel direction, the first P-type conductive region 19c is adjacent to and electrically connected to the first N-type source 18a; and the second P-type conductive region 19d is adjacent to and electrically connected to the second N-type source 18c. As shown in FIG1 , the first P-type conductive region 19c, the first N-type source 18a, and the second N-type drain 18d are electrically connected to the switch node voltage SW; and the second P-type conductive region 19d and the second N-type source 18c are electrically connected to the ground potential; the first N-type drain 18b is electrically connected to the input voltage Vin. In the buck power stage circuit, the switch node is electrically connected to one end of the inductor, and the other end of the inductor is coupled to the output voltage. This is well known to those skilled in the art and will not be elaborated herein.

In one embodiment, the first gate 17a of the NMOS bridge element 10a has a gate length of 0.75µm, and the length of the portion of the first gate 17a covering the first drift oxide region 16a is 0.3µm.

In one embodiment, the second gate 17b of the NMOS low bridge element 10b has a gate length of 0.6µm, and the length of the portion of the second gate 17b covering the second drift oxide region 16b is 0.2µm.

In one embodiment, the semiconductor layer 11' is a P-type semiconductor epitaxial layer and has a volume resistivity of 45 Ohm-cm.

In one embodiment, the first drift oxide region 16a and the second drift oxide region 16b are chemical vapor deposition (CVD) oxide regions.

In one embodiment, the thickness of the first drift oxide region 16a and the second drift oxide region 16b is between 400Å and 450Å.

In one embodiment, the thickness of the dielectric layer of the first gate 17a and the dielectric layer of the second gate 17b is between 80Å and 100Å.

In one embodiment, the gate driving voltage of the NMOS high-pass device 10a of the NMOS high-pass device region HS-NMOS is 3.3V, and the first N-type drain is electrically connected to 12V to 16V.

In one embodiment, the minimum feature size of the NMOS half-bridge power device 10 is 0.18 microns.

It should be noted that the so-called inversion current channel refers to a region where an inversion layer is formed under the first gate 17a/the second gate 17b to allow the conduction current to flow due to the voltage applied to the first gate 17a/the second gate 17b during the conduction operation of the NMOS upper bridge element 10a/the NMOS lower bridge element 10b. This is well known in the art and will not be elaborated here.

It should be noted that the so-called drift current channel refers to the region where the conduction current of the N-type element 10a/NMOS lower bridge element 10b passes in a drifting manner during the conduction operation. This is well known in the art and will not be elaborated here.

It should be noted that the upper surface 11a does not refer to a completely flat plane, but refers to a surface of the semiconductor layer 11'. In this embodiment, for example, the portion of the upper surface 11a where the insulating region 12 contacts the upper surface 11a has a sunken portion.

It should be noted that the first gate 17a/the first gate 17b includes a conductive layer with conductivity, a dielectric layer connected to the upper surface 11a, and a spacer layer with electrical insulation properties, wherein the conductive layer is used as an electrical contact of the first gate 17a/the second gate 17b, formed on the dielectric layer and connected to the dielectric layer. The spacer layer is formed on both sides of the conductive layer to serve as an electrical insulation layer on both sides of the first gate 17a/the second gate 17b. This is well known to those skilled in the art and will not be elaborated here.

It should be noted that the aforementioned "N-type" and "P-type" refer to the semiconductor component region (such as but not limited to the aforementioned first high-voltage N-type well region 14a and the second high-voltage N-type well region 14b, the first high-voltage P-type well region 15a and the second high-voltage P-type well region 15b, the first N-type source 18a and the first N-type drain 18b, and the second N-type source 19a and the second N-type drain 19b) doped with impurities of different conductivity types in the NMOS half-bridge power element, so that the semiconductor component region becomes N or P type, wherein N type and P type are conductivity types with opposite electrical properties to each other.

In addition, it should be noted that the so-called NMOS half-bridge power element refers to the drift region length being adjusted according to the operating voltage it bears during normal operation, so that it can be operated at a higher specific voltage. This is well known to those with ordinary knowledge in this field and will not be elaborated here.

In addition, it should be noted that the so-called power device refers to a device used to transmit power. When a transistor is used to form a power device, a high-voltage device is usually used. During normal operation, the voltage applied to the drain is higher than a specific voltage, such as 5V.

FIG2 shows a cross-sectional schematic diagram of an NMOS half-bridge power device 20 according to another embodiment of the present invention. This embodiment is different from the embodiment of FIG1 in that the NMOS half-bridge power device 20 of this embodiment further includes: a second N-type buried layer 23a, a third high-voltage N-type isolation region 24c and a fourth high-voltage N-type isolation region 24d.

The second N-type buried layer 23a is formed in the NMOS lower bridge element region LS-NMOS in the same process step as the first N-type buried layer 23a. The second N-type buried layer 23b is formed in the semiconductor layer 11' and the substrate 11 directly below the second high voltage N-type well region 14b and the second high voltage P-type well region 15b.

The third high voltage N type isolation region 24c and the fourth high voltage N type isolation region 24d are formed in the semiconductor layer 11' of the NMOS lower bridge device region LS-NMOS by the same ion implantation process steps as the first high voltage N type isolation region 14c and the second high voltage N type isolation region 14d.

The third high voltage N-type isolation region 24c is adjacent to the other side of the second high voltage N-type well region 14b in the channel direction relative to the second high voltage P-type well region 15b. The fourth high voltage N-type isolation region 24d is adjacent to the other side of the second high voltage P-type well region 15b in the channel direction relative to the second high voltage N-type well region 14b.

Among them, the second N-type buried layer 23a, the third high-voltage N-type isolation region 24c and the fourth high-voltage N-type isolation region 24d form a device isolation region, which completely surrounds the NMOS bottom bridge device 10b below the upper surface 11a of the semiconductor layer 11', so as to electrically isolate the NMOS bottom bridge device 10b from other devices (such as the NMOS top bridge device 10a) formed in the semiconductor layer 11' below the upper surface 11a.

The first N-type buried layer 13a and the second N-type buried layer 23a are formed by, for example but not limited to, an ion implantation process step, implanting N-type conductive impurities into the substrate 11 in the form of accelerated ions, and forming the first N-type buried layer 13a and the second N-type buried layer 23a by thermal diffusion during or after the formation of the semiconductor layer 11'.

Please refer to Figures 3A-3N, which are schematic diagrams showing a method for manufacturing an NMOS half-bridge power device 20 according to an embodiment of the present invention. The NMOS half-bridge power device 20 includes an NMOS upper bridge device 20a and an NMOS lower bridge device 20b. As shown in Figure 3A, a substrate 11 is first provided, and N-type conductive impurities are implanted into the substrate 11 in the form of accelerated ions, for example but not limited to, by an ion implantation process step, and a first N-type buried layer 13a and a second N-type buried layer 23a are formed by thermal diffusion during or after the formation of the semiconductor layer 11' (as shown in Figure 3B).

Next, please refer to FIG. 3B , a semiconductor layer 11′ is formed on the substrate 11. The semiconductor layer 11′ is formed on the substrate 11, for example, by an epitaxial step, or a portion of the substrate 11 is used as the semiconductor layer 11′. As described above, during or after the process of forming the semiconductor layer 11′, a first N-type buried layer 13a and a second N-type buried layer 23a are formed by thermal diffusion. The semiconductor layer 11′ has a relative upper surface 11a and a lower surface 11b in a vertical direction (as indicated by the direction of the solid arrow in FIG. 3B , the same below). The method of forming the semiconductor layer 11′ is well known to those having ordinary knowledge in the field and will not be elaborated here. The substrate 21 is, for example but not limited to, a P-type or N-type semiconductor substrate.

Next, referring to FIG. 3C , an insulating region 12 is formed, for example, in the same process step. The insulating region 12 is, for example but not limited to, a shallow trench isolation (STI) structure as shown in FIG. 3C . The plurality of insulating regions 12 are used to define an NMOS upper bridge component region HS-NMOS and an NMOS lower bridge component region LS-NMOS, wherein an NMOS upper bridge component 20 a is formed in the NMOS upper bridge component region HS-NMOS, and an NMOS lower bridge component 20 b is formed in the NMOS lower bridge component region LS-NMOS.

Next, please refer to FIG. 3D , the first high voltage N-type isolation region 14c, the second high voltage N-type isolation region 14d, the third high voltage N-type isolation region 24c and the fourth high voltage N-type isolation region 24d are formed in the semiconductor layer 11' of the NMOS bridge element region HS-NMOS by the same ion implantation process step. The first high voltage N-type isolation region 14c is adjacent to the other side of the first high voltage N-type well region 14a in the channel direction relative to the side adjacent to the first high voltage P-type well region 15a. The second high voltage N-type isolation region 14d is adjacent to the other side of the first high voltage P-type well region 15a in the channel direction relative to the side adjacent to the first high voltage N-type well region 14a. Among them, the first N-type buried layer 13a, the first high-voltage N-type isolation region 14c and the second high-voltage N-type isolation region 14d form a device isolation region, which completely surrounds the NMOS upper bridge component 10a below the upper surface 11a of the semiconductor layer 11', so as to electrically isolate the NMOS upper bridge component 10a from other components (such as the NMOS lower bridge component 10b) formed in the semiconductor layer 11' below the upper surface 11a. Among them, the second N-type buried layer 23a, the third high-voltage N-type isolation region 24c and the fourth high-voltage N-type isolation region 24d form a device isolation region, which completely surrounds the NMOS bottom bridge device 10b below the upper surface 11a of the semiconductor layer 11', so as to electrically isolate the NMOS bottom bridge device 10b from other devices (such as the NMOS top bridge device 10a) formed in the semiconductor layer 11' below the upper surface 11a.

Next, please refer to FIG. 3E , the first high voltage N-type well region 14a and the second high voltage N-type well region 14b are formed by the same ion implantation process step. The first high voltage N-type well region 14a and the second high voltage N-type well region 14b are formed in the semiconductor layer 11' of the NMOS upper bridge component region HS-NMOS and the semiconductor layer 11' of the NMOS lower bridge component region LS-NMOS, respectively. The first high voltage N-type well region 14a and the second high voltage N-type well region 14b are both located below the upper surface 11a and connected to the upper surface 11a. A portion of the first high voltage N-type well region 14a is located directly below the gate 17a and connected to the gate 17a to provide a drift current channel for the NMOS upper bridge element 10a during the conduction operation; and a portion of the second high voltage N-type well region 14b is located directly below the gate 17b to provide a reverse current channel for the NMOS lower bridge element 10b during the conduction operation.

Next, please refer to FIG. 3F , the first high voltage P-type well region 15a and the second high voltage P-type well region 15b are formed by the same ion implantation process step. The first high voltage P-type well region 15a and the second high voltage P-type well region 15b are respectively formed in the semiconductor layer 11' of the NMOS upper bridge component region HS-NMOS and the semiconductor layer 11' of the NMOS lower bridge component region LS-NMOS, wherein the first high voltage N-type well region 14a and the first high voltage P-type well region 15a are adjacent to each other in the channel direction (as indicated by the direction of the dotted arrow in FIG. 3F , the same below), and the second high voltage N-type well region 14b and the second high voltage P-type well region 15b are adjacent to each other in the channel direction. The first high voltage P-type well region 15a and the second high voltage P-type well region 15b are both located below the upper surface 11a and connected to the upper surface 11a.

Next, please refer to FIG. 3G , for example but not limited to, a drift oxide layer 16 is formed on the semiconductor layer 11′ by a deposition process step, and the drift oxide layer 16 completely covers the NMOS upper bridge device region HS-NMOS and the NMOS lower bridge device region LS-NMOS.

Next, referring to FIG. 3H , the drift oxide layer 16 is etched by the same etching process step to form a first drift oxide region 16a in the NMOS upper bridge device region HS-NMOS and a second drift oxide region 16b in the NMOS lower bridge device region LS-NMOS. The first drift oxide region 16a and the second drift oxide region 16b are formed on the semiconductor layer 11′ and are respectively located on the drift region of the NMOS upper bridge device 10a and the drift region of the NMOS lower bridge device 10b.

Next, please refer to FIG. 3I , after the first drift oxide region 16a and the second drift oxide region 16b are formed, a gate dielectric layer 17′ is formed on the semiconductor layer 11′, and the gate dielectric layer 17′ covers the NMOS upper bridge component region HS-NMOS and the NMOS lower bridge component region LS-NMOS.

Next, referring to FIG. 3J , after the gate dielectric layer 17′ is formed, a polysilicon layer 17 is formed on the gate dielectric layer 17′, for example but not limited to, by a deposition process step. The polysilicon layer 17 covers the NMOS upper bridge component region HS-NMOS and the NMOS lower bridge component region LS-NMOS.

Next, referring to FIG. 3K , after the polysilicon layer 17 is formed, the polysilicon layer 17 is etched by the same etching process step to form a first gate 17a in the NMOS upper bridge device region HS-NMOS and a second gate 17b in the NMOS lower bridge device region LS-NMOS.

It should be noted that the thickness of the gate dielectric layer 17' is relatively lower than that of the polysilicon layer 17, and is used as a dielectric layer of the first gate 17a and the second gate 17b after the first gate 17a and the second gate 17b are formed. This is well known to those with ordinary knowledge in the field and will not be elaborated here.

It should be noted that the first gate 17a and the second gate 17b are on the upper surface 11a of the semiconductor layer 11'. The first gate 17a and the second gate 17b respectively include a conductive layer, a spacer layer and a dielectric layer, wherein the dielectric layer is located on the upper surface 11a and connected to the upper surface 11a. This is well known to those with ordinary knowledge in the field and will not be elaborated here.

Next, please refer to Figure 3L, in which the same ion implantation process steps are used to respectively form the first P-type body region 19a and the second P-type body region 19b in the semiconductor layer 11' of the NMOS upper bridge component region HS-NMOS and the semiconductor layer 11' of the NMOS lower bridge component region LS-NMOS, wherein the first P-type body region 19a is adjacent to the first high-voltage N-type well region 14a in the channel direction, and the second P-type body region 19b is adjacent to the second high-voltage N-type well region 14b in the channel direction.

A portion of the first P-type body region 19a is located directly below the first gate 17a and connected to the first gate 17a to provide a reverse current channel for the NMOS upper bridge element 10a during the conduction operation; and a portion of the second P-type body region 19b is located directly below the second gate 17b and connected to the second gate 17b to provide a reverse current channel for the NMOS lower bridge element 10b during the conduction operation.

Next, please refer to FIG. 3M , the first N-type source 18a, the first N-type drain 18b, the second N-type source 18c and the second N-type drain 18d are formed by the same ion implantation process step. The first N-type source 18a and the first N-type drain 18b are formed in the semiconductor layer 11' of the NMOS upper bridge element region HS-NMOS, and the first N-type source 18a and the first N-type drain 18b are respectively located in the first P-type body region 19a and the first high-voltage N-type well region 14a outside and below the first gate 17a in the channel direction (as indicated by the dotted arrow direction in FIG. 3M , the same below).

In the vertical direction, the first N-type source 18a and the first N-type drain 18b are formed under the upper surface 11a and connected to the upper surface 11a, and in the channel direction, the drift region of the NMOS bridge element 10a is located between the first N-type drain 18b and the first P-type body region 19a, and separates the first N-type drain 18b and the first P-type body region 19a, and is located in the first high-voltage N-type well region 14a close to the upper surface 11a, and is used as a drift current channel of the NMOS bridge element 10a in the conduction operation.

The second N-type source 18c and the second N-type drain 18d are respectively located in the second P-type body region 19b and the second high-voltage N-type well region 14b outside and below the second gate 17b in the channel direction (as indicated by the dotted arrow direction in FIG. 3M , the same below).

In the vertical direction, the second N-type source 18c and the second N-type drain 18d are formed under the upper surface 11a and connected to the upper surface 11a, and in the channel direction, the drift region of the NMOS lower bridge element 10b is located between the second N-type drain 18d and the second P-type body region 19b, and separates the second N-type drain 19b from the second P-type body region 19b, and is located in the second high-voltage N-type well region 14b close to the upper surface 11a, and is used as a drift current channel for the NMOS lower bridge element 10b in the conduction operation.

Next, please refer to FIG. 3N , the first P-type conductive region 19c and the second P-type conductive region 19d are formed by the same ion implantation process step. The first P-type conductive region 19c is formed in the first P-type body region 19a, wherein the first P-type conductive region 19c is an electrical contact of the first P-type body region 19a. The second P-type conductive region 19d is formed in the second P-type body region 19b, wherein the second P-type conductive region 19d is an electrical contact of the second P-type body region 19b.

The first P-type conductive region 19c and the second P-type conductive region 19d are formed under the upper surface 11a and connected to the upper surface 11a, and in the channel direction, the first P-type conductive region 19c is adjacent to and electrically connected to the first N-type source 18a; and the second P-type conductive region 19d is adjacent to and electrically connected to the second N-type source 18c. As shown in FIG1 , the first P-type conductive region 19c, the first N-type source 18a, and the second N-type drain 18d are electrically connected to the switch node voltage SW; and the second P-type conductive region 19d and the second N-type source 18c are electrically connected to the ground potential; the first N-type drain 18b is electrically connected to the input voltage Vin. In the buck power stage circuit, the switch node is electrically connected to one end of the inductor, and the other end of the inductor is coupled to the output voltage. This is well known to those skilled in the art and will not be elaborated herein.

In one embodiment, the first gate 17a of the NMOS bridge element 10a has a gate length of 0.75µm, and the length of the portion of the first gate 17a covering the first drift oxide region 16a is 0.3µm.

In one embodiment, the second gate 17b of the NMOS low bridge element 10b has a gate length of 0.6µm, and the length of the portion of the second gate 17b covering the second drift oxide region 16b is 0.2µm.

In one embodiment, the semiconductor layer 11' is a P-type semiconductor epitaxial layer and has a volume resistivity of 45 Ohm-cm.

In one embodiment, the first drift oxide region 16a and the second drift oxide region 16b are chemical vapor deposition (CVD) oxide regions.

In one embodiment, the thickness of the first drift oxide region 16a and the second drift oxide region 16b is between 400Å and 450Å.

In one embodiment, the thickness of the dielectric layer of the first gate 17a and the dielectric layer of the second gate 17b is between 80Å and 100Å.

In one embodiment, the gate driving voltage of the NMOS high-pass device 10a of the NMOS high-pass device region HS-NMOS is 3.3V, and the first N-type drain is electrically connected to 12V to 16V.

In one embodiment, the minimum feature size of the NMOS half-bridge power device 10 is 0.18 microns.

The present invention has been described above with respect to the preferred embodiments, but the above is only for those familiar with the art to easily understand the content of the present invention, and is not used to limit the scope of the present invention. Under the same spirit of the present invention, those familiar with the art can think of various equivalent changes. For example, other process steps or structures can be added without affecting the main characteristics of the component, such as lightly doped drain regions, etc.; for example, lithography technology is not limited to mask technology, but can also include electron beam lithography technology. All of these can be derived by analogy based on the teachings of the present invention. In addition, the various embodiments described are not limited to single applications, but can also be used in combination, for example but not limited to the use of two embodiments together. Therefore, the scope of the present invention should cover the above and all other equivalent changes. In addition, any embodiment of the present invention does not necessarily have to achieve all objects or advantages, and therefore, any of the claimed patent scope should not be limited thereto.

10, 20: NMOS half-bridge power element 10a, 20a: NMOS upper bridge element 10b, 20b: NMOS lower bridge element 11: substrate 11’: semiconductor layer 11a: upper surface 11b: lower surface 12: insulating region 13a: first N-type buried layer 14a: first high-voltage N-type well region 14b: second high-voltage N-type well region 14c: first high-voltage N-type isolation region 14d: second high-voltage N-type isolation region 15a: first high-voltage P-type well region 15b: second high-voltage P-type well region 16: drift oxide layer 16a: first drift oxide region 16b: second drift oxide region 17: polysilicon layer 17a: first gate 17b: second gate 17’: gate dielectric layer 18a: first N-type source 18b: first N-type drain 18c: second N-type source 18d: second N-type drain 19a: first P-type body region 19b: second P-type body region 19c: first P-type conductive region 19d: second P-type conductive region 23a: second N-type buried layer 24c: third high-voltage N-type isolation region 24d: fourth high-voltage N-type isolation region HV-NMOS: NMOS upper bridge component region HV-PMOS: NMOS lower bridge component region LG: Lower bridge gate voltage SW: Switching node voltage UG: Upper bridge gate voltage Vin: Input voltage

FIG. 1 is a cross-sectional schematic diagram showing an NMOS half-bridge power device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional schematic diagram showing an NMOS half-bridge power device according to an embodiment of the present invention.

3A-3N are cross-sectional schematic diagrams showing a method for manufacturing an NMOS half-bridge power device according to an embodiment of the present invention.

10: NMOS half-bridge power device

10a: NMOS bridge element

10b: NMOS lower bridge element

11: Substrate

11’: semiconductor layer

11a: Upper surface

11b: Lower surface

12: Isolation Zone

13a: First N-type buried layer

14a: The first high-voltage N-type well area

14b: The second high-voltage N-type well area

14c: The first high voltage N-type isolation area

14d: Second high voltage N-type isolation area

15a: The first high-pressure P-type well area

15b: The second high-pressure P-type well area

16a: First drift oxidation zone

16b: Second drift oxidation zone

17a: First gate

17b: Second gate

18a: First N-type source

18b: First N-type drain

18c: Second N-type source

18d: Second N-type drain

19a: The first P-type body region

19b: Second P-type body region

19c: First P-type conductive region

19d: Second P-type conductive region

HS-NMOS: NMOS bridge component area

LS-NMOS: NMOS lower bridge component area

LG: Lower bridge gate voltage

SW: switch node voltage

UG: Upper bridge gate voltage

Vin: Input voltage

Claims (22)

An NMOS half-bridge power device comprises: a semiconductor layer formed on a substrate; a plurality of insulating regions formed on the semiconductor layer to define an NMOS upper bridge device region and an NMOS lower bridge device region, wherein an NMOS upper bridge device is formed in the NMOS upper bridge device region, and an NMOS lower bridge device is formed in the NMOS lower bridge device region; a first N-type buried layer formed in the NMOS upper bridge device region; a first high voltage N-type isolation region and a second high voltage N-type isolation region, formed in the semiconductor layer of the NMOS upper bridge component region by the same ion implantation process step; a first high voltage N-type well region and a second high voltage N-type well region, respectively formed in the semiconductor layer of the NMOS upper bridge component region and the semiconductor layer of the NMOS lower bridge component region by the same ion implantation process step; a first high voltage P-type well region and a second high voltage P-type well region are respectively formed in the semiconductor layer of the NMOS upper bridge element region and the semiconductor layer of the NMOS lower bridge element region by the same ion implantation process step, wherein the first high voltage N-type well region and the first high voltage P-type well region are adjacent to each other in a channel direction, and the second high voltage N-type well region and the second high voltage P-type well region are adjacent to each other in the channel direction; a first drift oxide region and a second drift oxide region A drift oxide layer is etched in the same etching process step to form the first drift oxide region and the second drift oxide region in the NMOS upper bridge component region and the NMOS lower bridge component region respectively; a first gate and a second gate are etched in the same etching process step to form a polysilicon layer and the first gate and the second gate in the NMOS upper bridge component region and the NMOS lower bridge component region respectively; A first A P-type body region and a second P-type body region are formed in the semiconductor layer of the NMOS upper bridge element region and the semiconductor layer of the NMOS lower bridge element region respectively by the same ion implantation process step, wherein a portion of the first P-type body region is located directly below the first gate, and the first P-type body region is adjacent to the first high-voltage N-type well region in the channel direction, and a portion of the second P-type body region is located directly below the second gate. The second P-type body region and the second high-voltage N-type well region are adjacent to each other in the channel direction; a first N-type source and a first N-type drain are formed in the semiconductor layer of the NMOS bridge element region by the same ion implantation process step, and the first N-type source and the first N-type drain are respectively located in the first P-type body region and the first high-voltage N-type well region below the outside of the first gate; and a second N-type source and a first The second N-type drain is formed in the semiconductor layer of the NMOS lower bridge element region by the same ion implantation process step as the first N-type source and the first N-type drain, and the second N-type source and the second N-type drain are respectively located in the second P-type body region and the second high-voltage N-type well region below the outside of the second gate; wherein the first N-type buried layer is formed directly below the first high-voltage N-type well region and the first high-voltage P-type well region The semiconductor layer and the substrate are disposed in the direction of the channel; wherein the first high-voltage N-type isolation region is adjacent to the other side of the first high-voltage N-type well region adjacent to the first high-voltage P-type well region in the direction of the channel; wherein the second high-voltage N-type isolation region is adjacent to the other side of the first high-voltage P-type well region adjacent to the first high-voltage N-type well region in the direction of the channel; wherein the gate length of the first gate is greater than the gate length of the second gate. The NMOS half-bridge power device as described in claim 1 further comprises: a first P-type conductive region formed in the first P-type body region, wherein the first P-type conductive region is an electrical contact of the first P-type body region; and a second P-type conductive region formed in the second P-type body region by the same ion implantation process step as that for forming the first P-type conductive region, wherein the second P-type conductive region is an electrical contact of the second P-type body region. The NMOS half-bridge power device as described in claim 2 further comprises: a second N-type buried layer formed in the NMOS lower bridge device region; and a third high-voltage N-type isolation region and a fourth high-voltage N-type isolation region formed in the semiconductor layer of the NMOS lower bridge device region by the same ion implantation process step as the first high-voltage N-type isolation region and the second high-voltage N-type isolation region; wherein the second N-type buried layer is formed in In the semiconductor layer and the substrate directly below the second high voltage N-type well region and the second high voltage P-type well region; wherein the third high voltage N-type isolation region is adjacent to the other side of the second high voltage N-type well region in the channel direction relative to the second high voltage P-type well region; wherein the fourth high voltage N-type isolation region is adjacent to the other side of the second high voltage P-type well region in the channel direction relative to the second high voltage N-type well region. An NMOS half-bridge power device as described in claim 2 or 3, wherein the first N-type source, the first P-type conductive region and the second N-type drain are electrically connected. The NMOS half-bridge power device as described in claim 1, wherein the gate length of the first gate of the NMOS upper bridge device is 0.75μm, and the length of the portion of the first gate covering the first drift oxide region is 0.3μm. The NMOS half-bridge power device as described in claim 1, wherein the gate length of the second gate of the NMOS lower bridge device is 0.6μm, and the length of the portion of the second gate covering the second drift oxide region is 0.2μm. An NMOS half-bridge power device as described in claim 1, wherein the semiconductor layer is a P-type semiconductor epitaxial layer and has a volume resistivity of 45 Ohm-cm. The NMOS half-bridge power device as described in claim 1, wherein the thickness of the first drift oxide region and the second drift oxide region is between 400Å and 450Å. An NMOS half-bridge power device as described in claim 1, wherein the thickness of the dielectric layer of the first gate and the dielectric layer of the second gate is between 80Å and 100Å. The NMOS half-bridge power device as described in claim 1, wherein the gate drive voltage of the NMOS upper bridge device region is 3.3V, and the first N-type drain is electrically connected to 12V to 16V. An NMOS half-bridge power device as described in claim 1, wherein the minimum feature size of the NMOS half-bridge power device is 0.18 microns. A method for manufacturing an NMOS half-bridge power device, wherein the NMOS half-bridge power device includes an NMOS upper bridge device and an NMOS lower bridge device, and the method for manufacturing the NMOS half-bridge power device includes: forming a semiconductor layer on a substrate; forming a plurality of insulating regions on the semiconductor layer to define an NMOS upper bridge device region and an NMOS lower bridge device region, wherein the NMOS upper bridge device is formed in the NMOS upper bridge device region, and the NMOS lower bridge device is formed in the NMOS lower bridge device region. In the NMOS lower bridge component region; forming a first N-type buried layer in the NMOS upper bridge component region; forming a first high-voltage N-type isolation region and a second high-voltage N-type isolation region in the semiconductor layer of the NMOS upper bridge component region by the same ion implantation process step; forming a first high-voltage N-type well region in the semiconductor layer of the NMOS upper bridge component region and a second high-voltage N-type well region in the semiconductor layer of the NMOS lower ... The implantation process step forms a first high voltage P-type well region in the semiconductor layer of the NMOS upper bridge component region and a second high voltage P-type well region in the semiconductor layer of the NMOS lower bridge component region, wherein the first high voltage N-type well region and the first high voltage P-type well region are adjacent to each other in a channel direction, and the second high voltage N-type well region and the second high voltage P-type well region are adjacent to each other in the channel direction; a drift oxide layer is formed on the semiconductor layer, and the drift oxide layer covers the NMOS upper bridge component region and the semiconductor layer. The NMOS lower bridge component region; the drift oxide layer is etched in the same etching process step to form a first drift oxide region in the NMOS upper bridge component region and a second drift oxide region in the NMOS lower bridge component region; after the first drift oxide region and the second drift oxide region are formed, a gate dielectric layer is formed on the semiconductor layer, the gate dielectric layer covers the NMOS upper bridge component region and the NMOS lower bridge component region; a polysilicon layer is formed on the gate dielectric layer, the The polysilicon layer covers the NMOS upper bridge component region and the NMOS lower bridge component region; the polysilicon layer is etched by the same etching process step to form a first gate in the NMOS upper bridge component region and a second gate in the NMOS lower bridge component region; a first P-type body region and a second P-type body region are formed in the semiconductor layer of the NMOS upper bridge component region and the semiconductor layer of the NMOS lower bridge component region respectively by the same ion implantation process step, wherein a portion of the first The P-type body region is located directly below the first gate, and the first P-type body region is adjacent to the first high-voltage N-type well region in the channel direction, and a portion of the second P-type body region is located directly below the second gate, and the second P-type body region is adjacent to the second high-voltage N-type well region in the channel direction; a first N-type source and a first N-type drain are formed in the semiconductor layer of the NMOS upper bridge element region by the same ion implantation process step, and the first N-type source and the first N-type drain are respectively located at The first high voltage P-type body region and the first high voltage N-type well region are formed below the outside of the first gate; and a second N-type source and a second N-type drain are formed in the semiconductor layer of the NMOS lower bridge element region by the same ion implantation process step as the first N-type source and the first N-type drain, and the second N-type source and the second N-type drain are respectively located in the P-type body region and the second high voltage N-type well region below the outside of the second gate; wherein the first N-type buried layer is formed in the The semiconductor layer and the substrate are directly below the first high-voltage N-type well region and the first high-voltage P-type well region; Wherein the first high-voltage N-type isolation region is adjacent to the other side of the first high-voltage N-type well region in the channel direction relative to the first high-voltage P-type well region; wherein the second high-voltage N-type isolation region is adjacent to the other side of the first high-voltage P-type well region in the channel direction relative to the first high-voltage N-type well region; wherein the gate length of the first gate is greater than the gate length of the second gate. The method for manufacturing an NMOS half-bridge power device as described in claim 12 further includes: forming a first P-type conductive region in the first P-type body region, wherein the first P-type conductive region is an electrical contact of the first P-type body region; and forming a second P-type conductive region in the second P-type body region by the same ion implantation process step as that for forming the first P-type conductive region, wherein the second P-type conductive region is an electrical contact of the second P-type body region. The manufacturing method of the NMOS half-bridge power device as described in claim 13 further comprises: forming a second N-type buried layer in the NMOS lower bridge device region; and forming a third high-voltage N-type isolation region and a fourth high-voltage N-type isolation region in the semiconductor layer of the NMOS lower bridge device region by the same ion implantation process step as the first high-voltage N-type isolation region and the second high-voltage N-type isolation region; wherein the second N-type buried layer is formed In the semiconductor layer and the substrate directly below the second high voltage N-type well region and the second high voltage P-type well region; wherein the third high voltage N-type isolation region is adjacent to the other side of the second high voltage N-type well region in the channel direction relative to the second high voltage P-type well region; wherein the fourth high voltage N-type isolation region is adjacent to the other side of the second high voltage P-type well region in the channel direction relative to the second high voltage N-type well region. The method for manufacturing an NMOS half-bridge power device as described in claim 13 or 14, wherein the first N-type source, the first P-type conductive region and the second N-type drain are electrically connected. The method for manufacturing an NMOS half-bridge power device as described in claim 12, wherein the gate length of the first gate of the NMOS upper bridge device is 0.75μm, and the length of the portion of the first gate covering the first drift oxide region is 0.3μm. The method for manufacturing an NMOS half-bridge power device as described in claim 12, wherein the gate length of the second gate of the NMOS lower bridge device is 0.6μm, and the length of the portion of the second gate covering the second drift oxide region is 0.2μm. The method for manufacturing an NMOS half-bridge power device as described in claim 12, wherein the semiconductor layer is a P-type semiconductor epitaxial layer and has a volume resistivity of 45 Ohm-cm. The method for manufacturing an NMOS half-bridge power device as described in claim 12, wherein the thickness of the first drift oxide region and the second drift oxide region is between 400Å and 450Å. The method for manufacturing an NMOS half-bridge power device as described in claim 12, wherein the thickness of the dielectric layer of the first gate and the dielectric layer of the second gate is between 80Å and 100Å. The method for manufacturing an NMOS half-bridge power device as described in claim 12, wherein the gate drive voltage of the NMOS upper bridge device region is 3.3V, and the first N-type drain is electrically connected to 12V to 16V. A method for manufacturing an NMOS half-bridge power device as described in claim 12, wherein the minimum feature size of the NMOS half-bridge power device is 0.18 microns.

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