TWI889167B - Semiconductor structure and method of forming the same - Google Patents

Abstract

A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, a source electrode and a drain electrode. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer and includes a first portion and a second portion that are separated from each other. The gate electrode is disposed on the first portion of the compound semiconductor layer. The source electrode and the drain electrode are respectively disposed on the barrier layer and on opposite sides of the gate electrode. Wherein, the drain electrode covers the second portion of the compound semiconductor layer.

Description

Semiconductor structure and forming method

The present invention relates to a semiconductor structure and a method for forming the same, and more particularly to a semiconductor structure and a method for forming the same comprising a compound semiconductor layer covered by a drain electrode.

Gallium nitride materials are widely used due to their wide band-gap and strong polarization effect. For example, gallium nitride semiconductors are currently widely used in power devices, such as high electron mobility transistors (HEMTs) with heterojunction structures.

However, in high electron mobility transistors, there may be problems such as excessive concentration of electric field distribution, insufficient on-current, degradation of dynamic resistance characteristics, the need to apply a turn-on voltage to conduct, and complex processes and structures. Therefore, although existing semiconductor structures and their formation methods have gradually met their intended uses, they still do not fully meet the requirements in all aspects. Therefore, there are still some problems to be overcome regarding semiconductor structures and their formation methods.

The drain electrode disclosed herein forms an ohmic contact with the second portion of the compound semiconductor layer. Since the ohmic contact can be analogous to a resistor, the semiconductor structure can be turned on without applying a turn-on voltage. In detail, when no voltage is applied (or the turn-on voltage is substantially 0), the two-dimensional electron gas in the semiconductor structure can be un-fully depleted, which can enable the semiconductor structure to be turned on. In addition, the ohmic contact can provide more holes to neutralize the trapped charge captured by defects in each layer, thereby making the electric field distribution of the semiconductor structure uniform, increasing the turn-on current and/or improving the dynamic resistance characteristics. Among them, improving the dynamic resistance characteristics may include maintaining the dynamic on-resistance to avoid the problem that the on-resistance increases with the increase of voltage. Furthermore, by adjusting the shape, size and arrangement of the second part of the compound semiconductor layer, the regrowth process can be omitted, thereby reducing the process and structural complexity.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, a source electrode, and a drain electrode. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer and includes a first portion and a second portion separated from each other. The gate electrode is disposed on the first portion of the compound semiconductor layer. The source electrode and the drain electrode are respectively disposed on the barrier layer and are respectively disposed on opposite sides of the gate electrode. The drain electrode covers the second portion of the compound semiconductor layer.

In some embodiments, a method for forming a semiconductor structure is provided. The method for forming a semiconductor structure includes providing a substrate. Forming a channel layer on the substrate. Forming a barrier layer on the channel layer. Forming a compound semiconductor layer on the barrier layer, wherein the compound semiconductor layer includes a first portion and a second portion separated from each other. Forming a gate electrode on the first portion of the compound semiconductor layer. Forming a source electrode and a drain electrode on the barrier layer, and the source electrode and the drain electrode are respectively arranged on opposite sides of the gate electrode. Wherein, the drain electrode covers the second portion of the compound semiconductor layer.

The semiconductor structure of each embodiment of the present disclosure is described in detail below. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific elements and arrangements described below are only for simply and clearly describing some embodiments of the present disclosure. Of course, these are only used for exemplification and not for limiting the present disclosure. In addition, similar and/or corresponding element symbols may be used in different embodiments to indicate similar and/or corresponding elements to clearly describe the present disclosure. However, the use of these similar and/or corresponding element symbols is only for simply and clearly describing some embodiments of the present disclosure, and does not represent any correlation between the different embodiments and/or structures discussed.

It should be understood that relative terms may be used in various embodiments, such as "lower" or "bottom" or "higher" or "top" to describe the relative relationship of one element of the diagram to another element. It is understood that if the device in the diagram is turned upside down, the element described on the "lower" side will become the element on the "higher" side. The embodiments of the present disclosure can be understood in conjunction with the drawings, and the drawings of the present disclosure are also considered part of the disclosure.

Furthermore, when a first material layer is mentioned as being on or over a second material layer, it may include a situation where the first material layer and the second material layer are in direct contact, or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly on the second material layer, it means that the first material layer and the second material layer are in direct contact.

In addition, it should be understood that the ordinal numbers used in the specification and the patent application, such as "first", "second", etc., are used to modify the elements, and they themselves are not intended to imply or represent any previous ordinal numbers of the (or those) elements, nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The patent application and the specification may not use the same terms, for example, the first element in the specification may be the second element in the patent application.

In some embodiments of the present disclosure, terms related to bonding and connection, such as "connect", "interconnect", "bond", etc., unless otherwise specifically defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein other structures are disposed between the two structures. Such terms related to connection and bonding may also include situations where both structures are movable, or both structures are fixed. In addition, the terms "electrically connected" or "electrically coupled" include any direct and indirect electrical connection means.

In the text, the terms "approximate", "about", and "substantially" usually mean within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. The quantities given here are approximate quantities, that is, in the absence of specific description of "about", "approximately", and "substantially", the meanings of "about", "approximately", and "substantially" can still be implied. The term "ranging from a first value to a second value" or "a first value~a second value" means that the range includes the first value, the second value, and other values therebetween. Furthermore, any two values or directions used for comparison may have a certain error. If a first value is equal to a second value, it implies that there may be an error of about 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% between the first value and the second value.

Certain terms are used throughout the specification and patent applications in this disclosure to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same component by different names. This document is not intended to distinguish between components that have the same function but different names. In the following specification and patent applications, the words "comprise", "contain", "have" and the like are open-ended words, and therefore should be interpreted as "including but not limited to..." Therefore, when the terms "comprise", "contain" and/or "have" are used in the description of this disclosure, they specify the existence of corresponding parts, regions, steps, operations and/or elements, but do not exclude the existence of one or more corresponding parts, regions, steps, operations and/or elements.

It should be understood that the following embodiments may replace, reorganize, or combine components in different embodiments to implement other embodiments without departing from the spirit of the present disclosure. Components between embodiments may be combined and used in any manner as long as they do not violate the spirit of the invention or conflict with each other.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

In the present disclosure, each direction is not limited to the three axes of the rectangular coordinate system such as the X-axis, the Y-axis, and the Z-axis, and can be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, hereinafter, the X-axis direction is the first direction D1 (width direction), the Y-axis direction is the second direction D2 (length direction), and the Z-axis direction is the third direction D3 (thickness direction). In some embodiments, the top view schematic diagram described herein is a schematic diagram for observing the XY plane (the plane formed by the first direction D1 and the second direction D2), and the cross-sectional schematic diagram described herein is a schematic diagram for observing the XZ plane (the plane formed by the first direction D1 and the third direction D3).

In the following text, the current-to-voltage characteristic curve of an "Ohmic contact" is linear, and it is bidirectional and has no rectification characteristics.

Referring to FIG. 1, it is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor structure 1 according to an embodiment of the present disclosure. As shown in FIG. 1, in some embodiments, a substrate 100 may be provided. In some embodiments, the substrate 100 may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like. The semiconductor-on-insulator substrate includes a semiconductor layer formed on an insulator. For example, the insulating layer may include silicon oxide, silicon nitride, polysilicon, or a combination thereof, and the semiconductor substrate may include silicon, aluminum nitride (AlN), or the like.

In some embodiments, the substrate 100 may be an undoped or doped substrate, such as a substrate doped with p-type or n-type doping. In some embodiments, the substrate 100 may include a multi-layered substrate or a gradient substrate. In some embodiments, the substrate 100 may include a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride substrate, or a sapphire substrate. In some embodiments, the substrate 100 may be a silicon substrate.

As shown in FIG. 1 , in some embodiments, a buffer layer 200 may be formed on the substrate 100 to enhance the compatibility between the substrate 100 and other components disposed on the substrate 100, such as reducing the difference in thermal expansion coefficients and/or reducing the difference in lattice constants. In some embodiments, the buffer layer 200 may include a III-V compound semiconductor material, such as a III-nitride. For example, the buffer layer 200 may include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the buffer layer 200 may be formed by a deposition process. For example, the deposition process may be chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), similar processes or a combination thereof, but the present disclosure is not limited thereto.

In some embodiments, a nucleation layer may be further disposed between the substrate 100 and the buffer layer 200 to reduce the lattice difference between the substrate 100 and other layers disposed on the substrate 100, thereby improving the epitaxial quality and reliability. In some embodiments, the nucleation layer may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the nucleation layer may be formed by a deposition process. In other embodiments, the buffer layer 200 may be omitted.

As shown in FIG. 1 , in some embodiments, a channel layer 300 may be formed on a substrate 100. Specifically, the channel layer 300 may be formed on a buffer layer 200. In some embodiments, the channel layer 300 may include a III-V compound semiconductor material, such as a III-V nitride, but the present disclosure is not limited thereto. For example, the channel layer 300 may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), the like or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the channel layer 300 may be gallium nitride. In some embodiments, the channel layer 300 may be formed by a deposition process.

As shown in FIG. 1 , in some embodiments, a barrier layer 400 may be formed on the channel layer 300. In some embodiments, the barrier layer 400 may include a III-V compound semiconductor material, such as a III-V nitride, but the present disclosure is not limited thereto. For example, the barrier layer may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium aluminum gallium nitride (InAlGaN), the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the barrier layer 400 may be aluminum gallium nitride. In some embodiments, the barrier layer 400 may be formed by a deposition process. Due to the presence of a heterogeneous interface between the channel layer 300 and the barrier layer 400 and the difference in lattice constant between the channel layer 300 and the barrier layer 400, a two-dimensional electron gas (2DEG) 310 is formed near the top surface of the channel layer 300 and serves as a current path.

Referring to FIG. 2 , it is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor structure 1 according to an embodiment of the present disclosure. As shown in FIG. 2 , in some embodiments, a compound semiconductor layer 500 may be formed on the barrier layer 400. In some embodiments, the compound semiconductor layer 500 may be formed by a deposition process. In some embodiments, the compound semiconductor layer 500 may be a semiconductor material doped with a p-type dopant. For example, the compound semiconductor layer 500 may include p-doped gallium nitride (p-GaN). Therefore, the formation of the two-dimensional electron gas 310 located below the compound semiconductor layer 500 may be suppressed, so that the two-dimensional electron gas 310 located below the compound semiconductor layer 500 is depleted. In some embodiments, the compound semiconductor layer 500 may include a first portion 510 and a second portion 520 separated from each other.

Referring to FIG. 3 , it is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor structure 1 according to an embodiment of the present disclosure. In some embodiments, a gate electrode 600 may be formed on the first portion 510 of the compound semiconductor layer 500 so that the semiconductor structure 1 is a normally off structure. In some embodiments, the gate electrode 600 may include a conductive material. In some embodiments, the conductive material may include a metal, a metal nitride, a semiconductor material, the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), the like, or a combination thereof. In some embodiments, the metal nitride may include titanium nitride (TiN), tantalum nitride (TaN), the like, or a combination thereof. In some embodiments, the semiconductor material may include polycrystalline silicon or polycrystalline germanium, the like, or a combination thereof. In some embodiments, the conductive material may be formed by chemical vapor deposition, sputtering, resistive heating evaporation, electron beam evaporation, the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the gate electrode 600 and the first portion 510 of the compound semiconductor layer 500 may be in Schottky contact.

As shown in FIG. 3 , in some embodiments, a source electrode 620 and a drain electrode 640 may be formed on the barrier layer 400. In some embodiments, the source electrode 620 and the drain electrode 640 may be respectively disposed on opposite sides of the gate electrode 600. In some embodiments, the source electrode 620 may contact the barrier layer 400, and the drain electrode 640 may contact the barrier layer 400 and the second portion 520 of the compound semiconductor layer 500. In some embodiments, the materials and formation methods of the source electrode 620 and the drain electrode 640 may be the same as or different from the materials and formation methods of the gate electrode 600. In some embodiments, the source electrode 620 may be in ohmic contact with the barrier layer 400. In some embodiments, the drain electrode 640 may be in ohmic contact with the barrier layer 400, and the drain electrode 640 may be in ohmic contact with the second portion 520 of the compound semiconductor layer 500.

As shown in FIG. 3 , in some embodiments, the drain electrode 640 covers the second portion 520 of the compound semiconductor layer 500. In some embodiments, the drain electrode 640 is closer to the gate electrode 600 than the second portion 520 of the compound semiconductor layer 500. In some embodiments, a portion of the drain electrode 640 may be between the gate electrode 600 and the second portion 520 of the compound semiconductor layer 500. In some embodiments, the drain electrode 640 and the barrier layer 400 may together surround the second portion 520 of the compound semiconductor layer 500 without exposing the second portion 520 of the compound semiconductor layer 500. In some embodiments, the drain electrode 640 may cover the top surface and the side surface of the second portion 520 of the compound semiconductor layer 500 , and the barrier layer 400 may cover the bottom surface of the second portion 520 of the compound semiconductor layer 500 .

As shown in FIG. 3 , in some embodiments, in the first direction D1, the second portion 520 of the compound semiconductor layer 500 may have a width W520, and the drain electrode 640 may have a width W640. In some embodiments, the width W640 may be greater than the width W520. In some embodiments, the ratio of the width W520 to the width W640 (width W520/width W640) may be less than 1 and greater than or equal to 0.1. For example, the ratio of the width W520 to the width W640 may be 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, or any value or a range of values composed of any values therebetween, but the present disclosure is not limited thereto. Accordingly, the current path may be retained.

As shown in FIG. 3 , in some embodiments, a first dielectric layer 700 may be formed on the barrier layer 400. In some embodiments, the first dielectric layer 700 may be between the source electrode 620 and the gate electrode 600 and between the gate electrode 600 and the drain electrode 640. In some embodiments, the first dielectric layer 700 may be spaced a distance from the second portion 520 of the compound semiconductor layer 500. In some embodiments, the first dielectric layer 700 may be formed by a deposition process. In some embodiments, the first dielectric layer 700 may serve as a passivation layer or a planarization layer. In some embodiments, the first dielectric layer 700 may include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, the like, or a combination thereof, but the present disclosure is not limited thereto.

As shown in FIG. 3 , in some embodiments, a second dielectric layer 800 may be formed on the gate electrode 600, the source electrode 620, the drain electrode 640, and the first dielectric layer 700. In some embodiments, the material and the formation method of the second dielectric layer 800 may be the same as or different from the first dielectric layer 700. In some embodiments, the second dielectric layer 800 may serve as an interlayer dielectric layer. In some embodiments, connectors 820 and 840 may be formed in the second dielectric layer 800. In some embodiments, the connectors 820 and 840 may penetrate the second dielectric layer 800. In some embodiments, the connectors 820 and 840 may include a conductive material. In some embodiments, connector 820 may be electrically connected to source electrode 620, and connector 840 may be electrically connected to drain electrode 640. In some embodiments, connectors 820 and 840 may be formed by forming an opening (not shown) through second dielectric layer 800 and then depositing a conductive material in the opening.

As shown in FIG. 3 , in some embodiments, a source field plate 822 and a drain field plate 842 may be formed on the second dielectric layer 800 to obtain a semiconductor structure 1. In some embodiments, the source field plate 822 may be electrically connected to the source electrode 620 via a connector 820. In some embodiments, the drain field plate 842 may be electrically connected to the drain electrode 640 via a connector 840. In some embodiments, the source field plate 822 and the drain field plate 842 may be used to adjust the electric field distribution. In some embodiments, the source field plate 822 and the drain field plate 842 may include a conductive material. In some embodiments, the projection of the source electrode 620 on the substrate 100 may be located within the projection of the source field plate 822 on the substrate 100. In some embodiments, the projection of the gate electrode 600 on the substrate 100 may be located within the projection of the source field plate 822 on the substrate 100. Accordingly, the source field plate 822 may uniformly distribute the electric field adjacent to the source electrode 620 and the gate electrode 600. In some embodiments, the projection of the drain electrode 640 on the substrate 100 may be located within the projection of the drain field plate 842 on the substrate 100. Accordingly, the drain field plate 842 may uniformly distribute the electric field adjacent to the drain electrode 640.

Referring to FIG. 4, it is a schematic top view of a semiconductor structure 1 according to an embodiment of the present disclosure. For the convenience of explanation, some components are omitted in FIG. 4. The structure shown in the cross section I-I' of FIG. 4 is shown in FIG. 3.

In some embodiments, the projection of the second portion 520 of the compound semiconductor layer 500 on the substrate 100 may be within the projection of the drain electrode 640 on the substrate 100. In some embodiments, the projection area of the second portion 520 of the compound semiconductor layer 500 on the substrate 100 may be smaller than the projection area of the drain electrode 640 on the substrate 100. In some embodiments, the area ratio of the projection area of the second portion 520 of the compound semiconductor layer 500 on the substrate 100 to the projection area of the drain electrode 640 on the substrate 100 may be 0.1-0.95. For example, the ratio of the projection area of the second portion 520 on the substrate 100 to the projection area of the drain electrode 640 on the substrate 100 (projection area of the second portion 520 on the substrate 100/projection area of the drain electrode 640 on the substrate 100) can be 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95 or any value or a range of values composed of any values therebetween, but the present disclosure is not limited thereto. Accordingly, the ratio of the depleted region to the non-depleted region can be adjusted so that the two-dimensional electron gas in the semiconductor structure can be not completely depleted, thereby retaining the current path.

In some embodiments, the drain electrode 640 may have a pair of edges 640E1 facing each other in the extension direction of the gate electrode 600 (i.e., the second direction D2), and the drain electrode 640 may have a pair of edges 640E2 facing each other in a direction perpendicular to the extension direction of the gate electrode 600 (i.e., the first direction D1). The edge 640E1 and the edge 640E2 are adjacent to each other. In some embodiments, in the extension direction of the gate electrode 600 (i.e., the second direction D2), the second portion 520 of the compound semiconductor layer 500 is spaced apart from the edge 640E1 of the drain electrode 640 by a distance S1.

In some embodiments, the second portion 520 of the compound semiconductor layer 500 may include a plurality of sub-portions, and the plurality of sub-portions may be arranged at intervals. In some embodiments, the plurality of sub-portions may be arranged in an array. In some embodiments, each of the plurality of sub-portions may have a rectangular, triangular, polygonal, semicircular, semi-elliptical, bullet-shaped, teardrop-shaped, other suitable shapes or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the total width of the plurality of sub-portions of the second portion 520 of the compound semiconductor layer 500 may be a width W520.

In some embodiments, the second portion 520 of the compound semiconductor layer 500 may include a plurality of column sub-portions, and each column sub-portion of the plurality of column sub-portions may extend along the second direction D2 and may be arranged at intervals along the first direction D1. In some embodiments, each column of the plurality of column sub-portions may be arranged staggered. In some embodiments, the number of sub-portions of adjacent columns of the plurality of column sub-portions may be the same or different. In some embodiments, the number of odd-numbered column sub-portions may be greater than the number of even-numbered column sub-portions, based on the edge 640E2 of the drain electrode 640 away from the gate electrode 600.

In some embodiments, the second portion 520 of the compound semiconductor layer 500 may include a plurality of row sub-portions, each of which may extend along the first direction D1 and may be arranged at intervals along the second direction D2. In some embodiments, each row of the plurality of row sub-portions may be arranged staggered. In some embodiments, the number of sub-portions of adjacent rows in the plurality of row sub-portions may be the same or different. In some embodiments, the total width of the sub-portions of each row in the plurality of row sub-portions may be width W520. In some embodiments, the total width of the sub-portions of each row in the plurality of row sub-portions may be the same or different.

Accordingly, when no voltage is applied (for example, the on-voltage is approximately 0), a portion of the two-dimensional electron gas 310 is still continuous, thereby retaining the current path. For example, when the on-voltage is approximately 0, the two-dimensional electron gas 310 under the barrier layer 400 that is not covered by the second portion 520 of the compound semiconductor layer 500 is continuous, so that a current path still exists between the source electrode 620 and the drain electrode 640. In some embodiments, the second portion 520 of the compound semiconductor layer 500 may not be disposed on a virtual connection between the gate electrode 600 and the drain electrode 640 to retain the current path. For example, the current path may flow in the gaps between the sub-portions of the second portion 520 of the compound semiconductor layer 500.

Hereinafter, the same or similar element symbols and descriptions may be omitted.

Referring to FIG. 5 and FIG. 6, they are a cross-sectional schematic diagram and a top view schematic diagram of a semiconductor structure 2 according to an embodiment of the present disclosure. For the convenience of explanation, some elements are omitted in FIG. 6. Among them, the structure shown in the cross section II-II' of FIG. 6 is shown in FIG. 5. In some embodiments, the second portion 520 of the compound semiconductor layer 500 may include a plurality of sub-portions, and each of the plurality of sub-portions may extend along the first direction D1 and may be arranged at intervals along the second direction D2. In some embodiments, in the first direction D1, the width W640 of the drain electrode 640 may be greater than the width W520 of the second portion 520 of the compound semiconductor layer 500. In some embodiments, the ratio of the width W520 to the width W640 (width W520/width W640) may be less than 1 and greater than or equal to 0.5. For example, the ratio of the width W520 to the width W640 may be 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, or any value or a range of values consisting of any values therebetween, but the present disclosure is not limited thereto. Accordingly, a current path may be retained. For example, the current path may flow in the gap between the sub-portions of the second portion 520 of the compound semiconductor layer 500.

Referring to FIG. 7 and FIG. 8 , they are a cross-sectional schematic diagram and a top schematic diagram of a semiconductor structure 3 according to an embodiment of the present disclosure. For the convenience of explanation, some elements are omitted in FIG. 8 . Among them, the structure shown in the cross section III-III′ of FIG. 8 is shown in FIG. 7 . In some embodiments, the drain electrode 640 may cover a portion of the top surface of the second portion 520 of the compound semiconductor layer 500 and expose the remaining portion of the top surface of the second portion 520 of the compound semiconductor layer 500. In some embodiments, the first dielectric layer 700 may contact the second portion 520 of the compound semiconductor layer 500. In some embodiments, the second portion 520 of the compound semiconductor layer 500 may be closer to the gate electrode 600 than the drain electrode 640. Even though the second portion 520 of the compound semiconductor layer 500 may be closer to the gate electrode 600, the current path can still be retained because the second portions 520 of the compound semiconductor layer 500 are spaced apart from each other in the second direction D2.

In some embodiments, the ratio of the width W520 to the width W640 may be less than or equal to 1.2 and greater than or equal to 0.1. For example, the ratio of the width W520 to the width W640 may be 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, or any value or a range of values consisting of any values therebetween, but the present disclosure is not limited thereto. For example, the current path may flow in the gap between the sub-portions of the second portion 520 of the compound semiconductor layer 500. Furthermore, the process margin for forming the second portion 520 of the compound semiconductor layer 500 may be improved.

In some embodiments, the projection of the second portion 520 of the compound semiconductor layer 500 on the substrate 100 may be outside the projection of the drain electrode 640 on the substrate 100, and the projection of the second portion 520 of the compound semiconductor layer 500 on the substrate 100 may be within the projection of the drain field plate 842 on the substrate 100. Accordingly, the drain field plate 842 can make the electric field adjacent to the drain electrode 640 uniformly distributed.

Referring to FIG. 9 and FIG. 10, they are a cross-sectional schematic diagram and a top view schematic diagram of a semiconductor structure 4 according to an embodiment of the present disclosure. For the convenience of explanation, some elements are omitted in FIG. 10. The structure shown in the cross section IV-IV' of FIG. 10 is shown in FIG. 9. In some embodiments, in a top view, the second portion 520 of the compound semiconductor layer 500 may be a grid shape, a tic-tac-toe shape, a fennec shape, or other suitable shapes, but the present disclosure is not limited thereto.

In some embodiments, the second portion 520 of the compound semiconductor layer 500 may include a plurality of first extensions and a plurality of second extensions that are arranged alternately with each other. In some embodiments, each of the plurality of first extensions may extend along a first extension direction, and each of the plurality of second extensions may extend along a second extension direction having an angle of 15 to 90 degrees with the first extension direction, but the present disclosure is not limited thereto. For example, the plurality of first extensions may be horizontal extensions, and each of the plurality of first extensions may extend along a first direction D1, and the plurality of second extensions may be vertical extensions, and each of the plurality of second extensions may extend along a second direction D2. Accordingly, a current path may be retained. For example, the current path may flow along the outer edge of the second portion 520 of the compound semiconductor layer 500 having a grid-like shape.

In some embodiments, the semiconductor structures 1-4 disclosed herein can be used in any combination and can be used as a high electron mobility transistor. In other embodiments, any one of the semiconductor structures 1-4 can be further processed to form a high electron mobility transistor.

Accordingly, the present disclosure allows the drain electrode to cover the second portion of the compound semiconductor layer, so that the drain electrode and the second portion of the compound semiconductor layer are in ohmic contact. Therefore, the drain electrode in ohmic contact can provide holes, thereby making the electric field distribution uniform, increasing the conduction current and/or improving the dynamic resistance characteristics. In addition, the drain electrode in ohmic contact can be turned on when the conduction voltage is approximately 0, and the process and structural complexity can be reduced.

The scope of protection of this disclosure is not limited to the processes, machines, manufactures, material compositions, devices, methods, and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the relevant technical field can understand from the content of this disclosure that the processes, machines, manufactures, material compositions, devices, methods, and steps currently or in the future can be used according to this disclosure as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufactures, material compositions, devices, methods, and steps. Any embodiment or claim of this disclosure does not need to achieve all the purposes, advantages, and/or features described in this disclosure.

Several embodiments are summarized above so that those with ordinary knowledge in the art to which the present disclosure belongs can better understand the perspectives of the embodiments of the present disclosure. Those with ordinary knowledge in the art to which the present disclosure belongs should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and/or advantages as the embodiments herein. Those with ordinary knowledge in the art to which the present disclosure belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure.

1,2,3,4: semiconductor structure 100: substrate 200: buffer layer 300: channel layer 310: two-dimensional electron gas 400: barrier layer 500: compound semiconductor layer 510: first part 520: second part 600: gate electrode 620: source electrode 640: drain electrode 640E1,640E2: edge 700: first dielectric layer 800: second dielectric layer 820,840: connector 822: source field plate 842: drain field plate D1: first direction D2: second direction D3: third direction I-I’, II-II’, III-III’, IV-IV’: profile S1: distance W520, W640: width

The present disclosure can be more fully understood from the following detailed description when read together with the drawings. It is worth noting that, in accordance with standard practice in the industry, the components are not drawn to scale. In fact, the sizes of the components may be arbitrarily enlarged or reduced for clarity. Figures 1 to 3 are cross-sectional schematic diagrams of different stages of a method for forming a semiconductor structure according to an embodiment of the present disclosure. Figure 4 is a schematic top view of a semiconductor structure according to an embodiment of the present disclosure. Figure 5 is a schematic cross-sectional diagram of a semiconductor structure according to an embodiment of the present disclosure. Figure 6 is a schematic top view of a semiconductor structure according to an embodiment of the present disclosure. Figure 7 is a schematic cross-sectional diagram of a semiconductor structure according to an embodiment of the present disclosure. FIG. 8 is a schematic top view of a semiconductor structure according to an embodiment of the present disclosure. FIG. 9 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure. FIG. 10 is a schematic top view of a semiconductor structure according to an embodiment of the present disclosure.

1:Semiconductor structure

100:Substrate

200: Buffer layer

300: Channel layer

310: Two-dimensional electron gas

400: Barrier layer

500: Compound semiconductor layer

510: Part 1

520: Part 2

600: Gate electrode

620: Source electrode

640: Drain electrode

700: First dielectric layer

800: Second dielectric layer

820,840: Connectors

822: Source field plate

842: Drain field plate

D1: First direction

D2: Second direction

D3: Third direction

W520,W640:Width

Claims (9)

A semiconductor structure, comprising: a substrate; a channel layer, disposed on the substrate; a barrier layer, disposed on the channel layer; a compound semiconductor layer, disposed on the barrier layer, comprising a first portion and a second portion separated from each other; a gate electrode, disposed on the first portion of the compound semiconductor layer; and a source electrode and a drain electrode, respectively disposed on the barrier layer and respectively disposed on opposite sides of the gate electrode, wherein the drain electrode covers the second portion of the compound semiconductor layer, The gate electrode is in Schottky contact with the first part of the compound semiconductor layer, the drain electrode is in ohmic contact with the second part of the compound semiconductor layer, and the drain electrode is in ohmic contact with the barrier layer, wherein the two-dimensional electron gas below the second part of the compound semiconductor layer is completely depleted. A semiconductor structure as described in claim 1, wherein a projection area of the second portion of the compound semiconductor layer on the substrate is smaller than a projection area of the drain electrode on the substrate. A semiconductor structure as described in claim 1, wherein in an extension direction of the gate electrode, the second portion of the compound semiconductor layer is spaced a distance from an edge of the drain electrode. A semiconductor structure as described in claim 1, wherein the second portion of the compound semiconductor layer is closer to the gate electrode than to the drain electrode. The semiconductor structure as described in claim 1, wherein the drain electrode and the barrier layer surround the second portion of the compound semiconductor layer. A semiconductor structure as described in claim 1, wherein in an extension direction of the gate electrode, the second portion of the compound semiconductor layer includes a plurality of sub-portions, and the plurality of sub-portions are arranged at intervals. A semiconductor structure as described in claim 1, wherein the second portion of the compound semiconductor layer includes a plurality of rows of sub-portions, and each row of the plurality of rows of sub-portions is arranged in an alternating manner. A semiconductor structure as described in claim 1, wherein in a top view, the second portion of the compound semiconductor layer is in a grid shape. A method for forming a semiconductor structure, comprising: providing a substrate; forming a channel layer on the substrate; forming a barrier layer on the channel layer; forming a compound semiconductor layer on the barrier layer, wherein the compound semiconductor layer includes a first portion and a second portion separated from each other; forming a gate electrode on the first portion of the compound semiconductor layer; and forming a source electrode and a drain electrode on the barrier layer, wherein the source electrode and the drain electrode are respectively arranged on opposite sides of the gate electrode, wherein the drain electrode covers the second portion of the compound semiconductor layer, The gate electrode is in Schottky contact with the first part of the compound semiconductor layer, the drain electrode is in ohmic contact with the second part of the compound semiconductor layer, and the drain electrode is in ohmic contact with the barrier layer, wherein the two-dimensional electron gas below the second part of the compound semiconductor layer is completely depleted.

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