TWI880604B - Semiconductor device and method of forming the same - Google Patents

Abstract

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a channel layer, a barrier layer, a gate electrode, a source electrode, and a drain electrode. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate electrode is disposed on the barrier layer. The gate electrode includes a first gate portion and a second gate portion connected to each other. The source electrode is disposed on the barrier layer. The drain electrode is disposed on the barrier layer. Wherein, a first threshold voltage of the first gate portion between the source electrode and the drain electrode is smaller than a second threshold voltage of the second gate portion between the source electrode and the drain electrode.

Description

Semiconductor device and method of forming the same

The present invention relates to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device including a first gate portion and a second gate portion and a method for forming the same.

Gallium nitride materials are widely used due to their wide band-gap and strong polarization effect. For example, gallium nitride semiconductors are currently widely used in power devices, such as high electron mobility transistors (HEMTs) with heterojunction structures.

However, in high electron mobility transistors, there may be excessive concentration of electric field distribution, which may generate hot carriers, resulting in uneven electric field distribution, insufficient reliability, and degradation of semiconductor devices. Therefore, although existing semiconductor devices and their formation methods have gradually met their intended uses, they still do not fully meet the requirements in all aspects. Therefore, there are still some problems to be overcome regarding semiconductor devices and their formation methods.

The present disclosure adjusts the electric field distribution in a semiconductor device by setting a first gate portion and a second gate portion between a source electrode and a drain electrode. For example, by making the first critical voltage (Vt1) of the first gate portion smaller than the second critical voltage (Vt2) of the second gate portion, the generation of hot carriers at the second gate portion is avoided or the concentration of hot carriers at the second gate portion is reduced. Thus, making the two portions in the gate electrode have different critical voltages can reduce excessive concentration of the electric field distribution and reduce hot carriers, thereby making the electric field distribution more uniform, improving reliability and/or avoiding degradation of the semiconductor device.

In some embodiments, the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a channel layer, a barrier layer, a gate electrode, a source electrode, and a drain electrode. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate electrode is disposed on the barrier layer. The gate electrode includes a first gate portion and a second gate portion connected to each other. The source electrode is disposed on the barrier layer. The drain electrode is disposed on the barrier layer. The first critical voltage of the first gate portion between the source electrode and the drain electrode is less than the second critical voltage of the second gate portion between the source electrode and the drain electrode.

In some embodiments, the present disclosure provides a method for forming a semiconductor device. The method for forming a semiconductor device includes providing a substrate. Forming a channel layer on the substrate. Forming a barrier layer on the channel layer. Forming a gate electrode on the barrier layer, and wherein the gate electrode includes a first gate portion and a second gate portion connected to each other. Forming a source electrode on the barrier layer. Forming a drain electrode on the barrier layer. Wherein, a first critical voltage of the first gate portion between the source electrode and the drain electrode is less than a second critical voltage of the second gate portion between the source electrode and the drain electrode.

The semiconductor device and the method for forming the same disclosed herein can be applied to various types of electronic devices and the methods for forming the same. To make the components and advantages of the present disclosure more clearly understandable, various embodiments are specifically cited below and described in detail with the accompanying drawings.

The following is a detailed description of the semiconductor devices of each embodiment of the present disclosure. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific components and arrangements described below are only for simple and clear description of some embodiments of the present disclosure. Of course, these are only used for exemplification and not for limitation of the present disclosure. In addition, similar and/or corresponding component symbols may be used in different embodiments to indicate similar and/or corresponding components to clearly describe the present disclosure. However, the use of these similar and/or corresponding component symbols is only for simple and clear description of some embodiments of the present disclosure, and does not represent any correlation between the different embodiments and/or structures discussed.

It should be understood that relative terms may be used in various embodiments, such as "lower" or "bottom" or "higher" or "top" to describe the relative relationship of one element of the diagram to another element. It is understood that if the device in the diagram is turned upside down, the element described on the "lower" side will become the element on the "higher" side. The embodiments of the present disclosure can be understood in conjunction with the drawings, and the drawings of the present disclosure are also considered part of the disclosure.

Furthermore, when a first material layer is mentioned as being on or over a second material layer, it may include a situation where the first material layer and the second material layer are in direct contact, or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly on the second material layer, it means that the first material layer and the second material layer are in direct contact.

In addition, it should be understood that the ordinal numbers used in the specification and the patent application, such as "first", "second", etc., are used to modify the elements, and they themselves are not intended to imply or represent any previous ordinal numbers of the (or those) elements, nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The patent application and the specification may not use the same terms, for example, the first element in the specification may be the second element in the patent application.

In some embodiments of the present disclosure, terms related to bonding and connection, such as "connect", "interconnect", "bond", etc., unless otherwise specifically defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein other structures are disposed between the two structures. Such terms related to connection and bonding may also include situations where both structures are movable, or both structures are fixed. In addition, the terms "electrically connected" or "electrically coupled" include any direct and indirect electrical connection means.

In the text, the terms "approximate", "about", and "substantially" usually mean within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. The quantities given here are approximate quantities, that is, in the absence of specific description of "about", "approximately", and "substantially", the meanings of "about", "approximately", and "substantially" can still be implied. The term "ranging from a first value to a second value" or "a first value~a second value" means that the range includes the first value, the second value, and other values therebetween. Furthermore, any two values or directions used for comparison may have a certain error. If a first value is equal to a second value, it implies that there may be an error of about 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% between the first value and the second value.

Certain terms are used throughout the specification and patent applications in this disclosure to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same component by different names. This document is not intended to distinguish between components that have the same function but different names. In the following specification and patent applications, the words "comprise", "contain", "have" and the like are open-ended words, and therefore should be interpreted as "including but not limited to..." Therefore, when the terms "comprise", "contain" and/or "have" are used in the description of this disclosure, they specify the existence of corresponding parts, regions, steps, operations and/or elements, but do not exclude the existence of one or more corresponding parts, regions, steps, operations and/or elements.

It should be understood that the following embodiments may replace, reorganize, or combine components in different embodiments to implement other embodiments without departing from the spirit of the present disclosure. Components between embodiments may be combined and used in any manner as long as they do not violate the spirit of the invention or conflict with each other.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

In the present disclosure, each direction is not limited to the three axes of the rectangular coordinate system such as the X-axis, the Y-axis and the Z-axis, and can be interpreted in a broader sense. For example, the X-axis, the Y-axis and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following, the X-axis direction is the first direction D1 (length direction), the Y-axis direction is the second direction D2 (width direction), and the Z-axis direction is the third direction D3 (thickness direction). In some embodiments, the top view schematic diagram described herein is a schematic diagram for observing the XY plane (the plane formed by the first direction D1 and the second direction D2), and the cross-sectional schematic diagram described herein is a schematic diagram for observing the XZ plane (the plane formed by the first direction D1 and the third direction D3). In some embodiments, the normal direction of the substrate described herein is the third direction D3.

Referring to FIG. 1 , it is a schematic top view of a semiconductor device 1 according to an embodiment of the present disclosure. For the sake of convenience, some components may be omitted in FIG. 1 . As shown in FIG. 1 , the semiconductor device 1 may include a substrate 100 , a gate electrode 500 , a source electrode 520 , and a drain electrode 540 .

In some embodiments, the gate electrode 500 may include a first gate portion 500a and a second gate portion 500b connected to each other. In some embodiments, the gate electrode 500 may have an S-shaped structure when viewed from a top view. In some embodiments, the gate electrode 500 may include a straight line portion and an arc portion. In some embodiments, the first gate portion 500a may include a plurality of straight line portions and a plurality of first arc portions, and the second gate portion 500b may include a plurality of second arc portions. In some embodiments, one end of the straight line portion may be connected to the first arc portion, and the other end of the straight line portion may be connected to the second arc portion. In some embodiments, the radius of curvature of the second arc portion may be greater than the radius of curvature of the first arc portion.

In some embodiments, the source electrode 520 may include a first source portion 520a and a second source portion 520b connected to each other. In some embodiments, the first source portion 520a may extend along the second direction D2, and the second source portion 520b may extend along the first direction D1 different from the second direction D2. In some embodiments, a plurality of second source portions 520b may be connected to the same side of the first source portion 520a. In some embodiments, the source end portion 521 of the second source portion 520b far from the first source portion 520a may be close to the virtual center of the first arc portion of the first gate portion 500a. In some embodiments, the source end portion 521 may have an arc profile to make the electric field distribution more uniform.

In some embodiments, the drain electrode 540 may include a first drain portion 540a and a second drain portion 540b connected to each other. In some embodiments, the first drain portion 540a may extend along the second direction D2, and the second drain portion 540b may extend along the first direction D1. In some embodiments, the first drain portion 540a may be disposed in parallel with the first source portion 520a, and the gate electrode 500 may be disposed between the first drain portion 540a and the first source portion 520a. In some embodiments, a plurality of second drain portions 540b may be connected to the same side of the first drain portion 540a. In some embodiments, the drain end 541 of the second drain portion 540b, which is far from the first drain portion 540a, may be close to the virtual center of the second arc portion of the second gate portion 500b. In some embodiments, the drain end 541 may have an arc profile to make the electric field distribution more uniform. In some embodiments, the source electrode 520 and the drain electrode 540 may be interdigitated electrodes, respectively, and the interdigitated portions of the source electrode 520 and the drain electrode 540 may be arranged corresponding to each other.

In some embodiments, the first gate portion 500a may be located between the second source portion 520b and the second drain portion 540b, and the second gate portion 500b may be located between the first source portion 520a and the second drain portion 540b. Since the gate electrode 500 is used to control whether the semiconductor device is turned on, and the source electrode 520 may be a ground terminal (but the present disclosure is not limited thereto, and the drain electrode 540 may also be a ground terminal), the electric field is often excessively concentrated at the drain electrode 540. Furthermore, since the drain end 541 of the drain electrode 540 is smaller in size and is the boundary of the drain electrode 540 , the electric field is often excessively concentrated at the drain end 541 of the second drain portion 540 b of the drain electrode 540 .

Accordingly, in the present disclosure, by making the first critical voltage (Vt1) of the first gate portion 500a smaller than the second critical voltage (Vt2) of the second gate portion 500b, the second gate portion 500b is less likely to be turned-on than the first gate portion 500a, thereby avoiding or reducing the generation of hot carriers at the drain end 541 of the second drain portion 540b. That is, the carrier concentration of the two-dimensional electron gas (2DEG) under the first gate portion 500a is greater than the carrier concentration of the two-dimensional electron gas under the second gate portion 500b, so that the second gate portion 500b is less likely to be turned on than the first gate portion 500a.

In some embodiments, the semiconductor device of the present disclosure may substantially include two high electron mobility transistors (HEMTs) electrically connected to each other. The two HEMTs may be located in the cross section A-A' and the cross section B-B' of FIG. 1, respectively, and the combination of the two HEMTs may be as shown in Table 1. For example, the cross section A-A' of FIG. 1 may capture a cross section showing a flat region of the semiconductor device, and the cross section B-B' of FIG. 1 may capture a cross section showing a tip region of the semiconductor device.

Table 1 Example Section A-A' Section B-B' Critical voltage relationship Semiconductor devices 1~4 Depletion Type HEMT (Vt1＜0) Enhanced HEMT (Vt2＞0) Vt2＞Vt1 Semiconductor device 5 Depletion type MIS-HEMT (Vt1＜0) Depletion type HEMT (Vt2＜0) Vt2＞Vt1 (|Vt2|＜|Vt1|) Semiconductor device 6 Enhanced HEMT (Vt1＞0) Enhanced HEMT (Vt2＞0) Vt2＞Vt1 Semiconductor device 7 Enhanced HEMT (Vt1＞0) Enhanced MIS-HEMT (Vt2＞0) Vt2＞Vt1

In some embodiments, the HEMT may include a depletion-mode HEMT (D mode HEMT); a depletion-mode MIS-HEMT (depletion-mode metal-insulating layer-semiconductor layer high electron mobility transistor, D mode MIS-HEMT); an enhancement-mode HEMT (E mode HEMT); and an enhancement-mode MIS-HEMT (enhanced metal-insulating layer-semiconductor layer high electron mobility transistor, E mode MIS-HEMT). The critical voltages of the depletion-mode HEMT and the depletion-mode MIS-HEMT are both less than 0, and the critical voltage of the depletion-mode MIS-HEMT is less than the critical voltage of the depletion-mode HEMT. The critical voltages of the enhanced HEMT and the enhanced MIS-HEMT are both greater than 0, and the critical voltage of the enhanced MIS-HEMT is greater than the critical voltage of the enhanced HEMT. As shown in Table 1, in the above combination, the semiconductor structure including the first gate portion 500a shown in the cross section A-A' has a first critical voltage (Vt1), and the semiconductor structure including the second gate portion 500b shown in the cross section B-B' has a second critical voltage (Vt2). The second critical voltage (Vt2) is greater than the first critical voltage (Vt1) to make the electric field uniformly distributed.

In some embodiments, a gate voltage (Vg) may be applied to the first gate portion 500a and the second gate portion 500b. It should be particularly noted that since the first gate portion 500a and the second gate portion 500b may be substantially different portions of the same gate electrode 500, the gate voltage (Vg) applied to the first gate portion 500a and the gate voltage (Vg) applied to the second gate portion 500b are the same. When the gate voltage is greater than or equal to the critical voltage, the HEMT may be turned on. When the gate voltage is less than the critical voltage, the HEMT is turned off. In addition, whether the depletion-type HEMT and the depletion-type MIS-HEMT are electrically connected to another transistor as a cascode or in a direct drive form, they can satisfy the relationship that the second critical voltage (Vt2) is greater than the first critical voltage (Vt1) in both the on and off states.

Furthermore, the enhanced HEMT and enhanced MIS-HEMT can also satisfy the relationship that the second critical voltage (Vt2) is greater than the first critical voltage (Vt1) in both the on state and the off state. In the case where the gate voltage (Vg)> the second critical voltage (Vt2)> the first critical voltage (Vt1), the hot carriers in the second gate portion 500b can be reduced. In the case where the second critical voltage (Vt2)> the gate voltage (Vg)> the first critical voltage (Vt1), the hot carriers at the drain end 541 can be substantially non-existent or less.

For ease of explanation, the following FIGS. 2A to 8A and FIGS. 2B to 8B show the two-dimensional electron gas distribution when the gate voltage is 0 (Vg=0).

2A and 2B are cross-sectional schematic diagrams of a semiconductor device 1 according to an embodiment of the present disclosure. The semiconductor device 1 can be regarded as a whole semiconductor device 1 in which the semiconductor structures shown in the cross-section A-A' and the cross-section B-B' are electrically connected to each other.

As shown in FIG. 2A and FIG. 2B, in some embodiments, a substrate 100 may be provided. In some embodiments, the substrate 100 may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like. The semiconductor-on-insulator substrate includes a semiconductor layer formed on an insulator. For example, the insulating layer may include silicon oxide, silicon nitride, polysilicon, or a combination thereof, and the semiconductor substrate may include silicon, aluminum nitride (AlN), or the like. The substrate 100 may be an undoped or doped substrate, such as a substrate doped with p-type or n-type doping. In some embodiments, the substrate 100 may include a multi-layered substrate or a gradient substrate. In some embodiments, the substrate 100 may include a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride substrate, or a sapphire substrate. In some embodiments, the substrate 100 may be a silicon substrate.

As shown in FIG. 2A and FIG. 2B , in some embodiments, a buffer layer 200 may be formed on the substrate 100 to enhance the compatibility between the substrate 100 and other components disposed on the substrate 100, such as reducing the difference in thermal expansion coefficients and/or reducing the difference in lattice constants. In some embodiments, the buffer layer 200 may include a III-V compound semiconductor material, such as a III-nitride. For example, the buffer layer 200 may include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the buffer layer 200 may be formed by a deposition process. For example, the deposition process may be chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), similar processes or a combination thereof, but the present disclosure is not limited thereto.

In some embodiments, a nucleation layer may be further disposed between the substrate 100 and the buffer layer 200 to reduce the lattice difference between the substrate 100 and other layers disposed on the substrate 100, thereby improving the epitaxial quality and reliability. In some embodiments, the nucleation layer may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the nucleation layer may be formed by a deposition process. In other embodiments, the buffer layer 200 may be omitted.

As shown in FIG. 2A and FIG. 2B , in some embodiments, a channel layer 300 may be formed on the substrate 100. Specifically, the channel layer 300 may be formed on the buffer layer 200. In some embodiments, the channel layer 300 may include a III-V compound semiconductor material, such as a III-V nitride, but the present disclosure is not limited thereto. For example, the channel layer 300 may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), the like or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the channel layer 300 may be gallium nitride. In some embodiments, the channel layer 300 may be formed by a deposition process.

As shown in FIG. 2A and FIG. 2B , in some embodiments, a barrier layer 400 may be formed on the channel layer 300. In some embodiments, the barrier layer 400 may include a III-V compound semiconductor material, such as a III-V nitride, but the present disclosure is not limited thereto. For example, the barrier layer may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium aluminum gallium nitride (InAlGaN), the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the barrier layer 400 may be aluminum gallium nitride. In some embodiments, the barrier layer 400 may be formed by a deposition process. Due to the presence of a heterogeneous interface between the channel layer 300 and the barrier layer 400 and the difference in lattice constant between the channel layer 300 and the barrier layer 400, a two-dimensional electron gas (2DEG) 301 is formed near the top surface of the channel layer 300 and serves as a current path.

As shown in FIG. 2A and FIG. 2B , in some embodiments, a gate electrode 500 may be formed on the barrier layer 400, and the gate electrode 500 may include a first gate portion 500a and a second gate portion 500b. In some embodiments, the gate electrode 500 may include a conductive material. For example, the conductive material may include a metal, a metal nitride, a semiconductor material, the like, or a combination thereof, but the present disclosure is not limited thereto. The metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), the like, or a combination thereof, but the present disclosure is not limited thereto. The semiconductor material may include polysilicon or polycrystalline germanium. The conductive material may be formed by chemical vapor deposition, sputtering, resistive thermal evaporation, electron beam evaporation, similar processes or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the materials of the first gate portion 500a and the second gate portion 500b are the same and are formed in the same process.

As shown in FIGS. 2A and 2B , in some embodiments, the first gate portion 500a may directly contact the barrier layer 400, and the second gate portion 500b may also directly contact the barrier layer 400. In some embodiments, the bottom surface of the first gate portion 500a may be flush with the top surface of the barrier layer 400, and the bottom surface of the second gate portion 500b may be lower than the top surface of the barrier layer 400.

In some embodiments, a source electrode 520 may be formed on the barrier layer 400. The material and the forming method of the source electrode 520 may be the same as or different from the material and the forming method of the gate electrode 500. In some embodiments, a drain electrode 540 may be formed on the barrier layer 400. The material and the forming method of the drain electrode 540 may be the same as or different from the material and the forming method of the gate electrode 500. Therefore, the semiconductor device 1 may be obtained.

As shown in FIG. 2A and FIG. 2B , in some embodiments, in the third direction D3, the barrier layer 400 may have a thickness t400. In some embodiments, a first thickness t1 of the barrier layer 400 located below the first gate portion 500a may be greater than a second thickness t2 of the barrier layer 400 located below the second gate portion 500b. In some embodiments, the first thickness t1 may be substantially the same as the thickness t400, and the second thickness t2 may be less than the thickness t400. Therefore, the two-dimensional electron gas below the first gate portion 500a may be continuous, and the two-dimensional electron gas below the second gate portion 500b may be discontinuous, that is, depleted.

Accordingly, in the semiconductor device 1, the semiconductor structure including the first gate portion 500a is a depletion-type HEMT (Vt1<0), and the semiconductor structure including the second gate portion 500b is an enhancement-type HEMT (Vt2>0), and Vt2>Vt1 is satisfied, thereby making the electric field distribution more uniform, improving reliability and/or avoiding degradation of the semiconductor device.

In the following, the same or similar element symbols and descriptions are omitted. In addition, the subsequent FIGS. 3A to 8A respectively show schematic cross-sectional views of semiconductor devices 2 to 7 taken along the cross section A-A' shown in FIG. 1, and FIGS. 3B to 8B respectively show schematic cross-sectional views of semiconductor devices 2 to 7 taken along the cross section B-B' shown in FIG. 1. The semiconductor devices 2 to 7 can be respectively regarded as the semiconductor structures shown in the cross sections A-A' and B-B' being electrically connected to each other, as an integral semiconductor device 2 to 7.

Refer to FIG. 3A and FIG. 3B, which are respectively cross-sectional schematic diagrams of a semiconductor device 2 according to an embodiment of the present disclosure. The semiconductor structure shown in FIG. 3A may be substantially the same as that in FIG. 2A. As shown in FIG. 3A and FIG. 3B, in some embodiments, the semiconductor device 2 may include an adjustment structure disposed below the second gate portion 500b to adjust the distribution of the two-dimensional electron gas. In some embodiments, when observed in a top view, the shape of the adjustment structure may correspond to the shape of the second gate portion 500b. In some embodiments, the projection range of the adjustment structure on the substrate 100 may be substantially the same as the projection range of the second gate portion 500b on the substrate 100.

As shown in FIG. 3B , in some embodiments, the first compound semiconductor layer 501 may be used as a trimming structure and may be disposed between the second gate portion 500 b and the barrier layer 400 . In some embodiments, the first compound semiconductor layer 501 may be formed by a deposition process, and the first compound semiconductor layer 501 may be a p-type doped compound semiconductor material. For example, the first compound semiconductor layer 501 may include p-type doped gallium nitride (p-GaN). Accordingly, since the first compound semiconductor layer 501 may suppress the formation of the two-dimensional electron gas 301 at a position corresponding to the first compound semiconductor layer 501 , the two-dimensional electron gas is depleted. For example, the first compound semiconductor layer 501 can suppress the two-dimensional electron gas 301 located below (as shown in FIG. 3B ) or above (as shown in FIG. 4B ) the first compound semiconductor layer 501 . Therefore, the semiconductor device can be in a normally-off state. In some embodiments, the depletion range of the two-dimensional electron gas 301 can correspond to the projection range of the first compound semiconductor layer 501 on the two-dimensional electron gas 301 .

Accordingly, in the semiconductor device 2, the semiconductor structure including the first gate portion 500a is a depletion-type HEMT (Vt1 < 0), and the semiconductor structure including the second gate portion 500b is an enhancement-type HEMT (Vt2 > 0), and Vt2 > Vt1 is satisfied, thereby making the electric field distribution more uniform, improving reliability and/or avoiding degradation of the semiconductor device.

Referring to FIG. 4A and FIG. 4B, they are cross-sectional schematic diagrams of a semiconductor device 3 according to an embodiment of the present disclosure. The semiconductor structure shown in FIG. 4A may be substantially the same as FIG. 2A. As shown in FIG. 4A and FIG. 4B, in some embodiments, the semiconductor device 3 may include an adjustment structure disposed below the second gate portion 500b to adjust the distribution of the two-dimensional electron gas 301. As shown in FIG. 4B, in some embodiments, the first compound semiconductor layer 501 may be disposed in the channel layer 300. Accordingly, in the semiconductor device 3, the semiconductor structure including the first gate portion 500a is a depletion-type HEMT (Vt1 < 0), and the semiconductor structure including the second gate portion 500b is an enhancement-type HEMT (Vt2 > 0), and Vt2 > Vt1 is satisfied, thereby making the electric field distribution more uniform, improving reliability and/or avoiding degradation of the semiconductor device.

Referring to FIG. 5A and FIG. 5B, they are schematic cross-sectional views of a semiconductor device 4 according to an embodiment of the present disclosure. The semiconductor structure shown in FIG. 5A may be substantially the same as FIG. 2A. As shown in FIG. 5A and FIG. 5B, in some embodiments, the semiconductor device 4 may include an adjustment structure disposed below the second gate portion 500b to adjust the distribution of the two-dimensional electron gas. As shown in FIG. 5B, in some embodiments, the second compound semiconductor layer 502 may serve as the adjustment structure and may be disposed between the second gate portion 500b and the barrier layer 400. In some embodiments, the second compound semiconductor layer 502 may be disposed at the top surface of the barrier layer 400. In some embodiments, the second compound semiconductor layer 502 may include a halogen doped compound semiconductor. In some embodiments, the halogen element may include fluorine (F), chlorine (Cl), bromine (Br), iodine (I), or a combination thereof. In some embodiments, the second compound semiconductor layer 502 may be a fluorine doped compound semiconductor. In some embodiments, since the barrier layer 400 may include aluminum gallium nitride, the second compound semiconductor layer 502 may include fluorine doped aluminum gallium nitride (F doped AlGaN).

In some embodiments, in the third direction D3, the second compound semiconductor layer 502 may have a thickness t502. In some embodiments, the thickness t502 may be greater than 0 and less than or equal to the thickness t400. In other words, the second compound semiconductor layer 502 may penetrate the barrier layer 400 and contact the channel layer 300, or the second compound semiconductor layer 502 may not penetrate the barrier layer 400 and be spaced apart from the channel layer 300.

Since the second compound semiconductor layer 502 can provide holes, and the carriers in the channel region are electrons (i.e., electrons in the two-dimensional electron gas 301), the holes provided by the second compound semiconductor layer 502 can be used to neutralize the electrons in the channel region, thereby making the carriers in the channel region depleted. Therefore, the electric field distribution can be made more uniform by using a material that provides holes.

Accordingly, in the semiconductor device 4, the semiconductor structure including the first gate portion 500a is a depletion-type HEMT (Vt1 < 0), and the semiconductor structure including the second gate portion 500b is an enhancement-type HEMT (Vt2 > 0), and Vt2 > Vt1 is satisfied, thereby making the electric field distribution more uniform, improving reliability and/or avoiding degradation of the semiconductor device.

6A and 6B, they are schematic cross-sectional views of a semiconductor device 5 according to an embodiment of the present disclosure. As shown in FIG. 6A and FIG. 6B, in some embodiments, an insulating layer 503 may be disposed between the barrier layer 400 and the first gate portion 500a to adjust the distance between the conduction band and the Fermi level. In some embodiments, the insulating layer 503 is not disposed between the barrier layer 400 and the second gate portion 500b. In some embodiments, the bottom surface of the first gate portion 500a may be higher than the top surface of the barrier layer 400. In some embodiments, the second gate portion 500 b may directly contact the barrier layer 400 .

Accordingly, in the semiconductor device 5, the semiconductor structure including the first gate portion 500a is a depletion-type MIS-HEMT (Vt1＜0), and the semiconductor structure including the second gate portion 500b is a depletion-type HEMT (Vt2＜0), and Vt2＞Vt1 is satisfied, thereby making the electric field distribution more uniform, improving reliability and/or avoiding degradation of the semiconductor device.

7A and 7B are cross-sectional views of a semiconductor device 6 according to an embodiment of the present disclosure. As shown in FIG. 7A and FIG. 7B, in some embodiments, in the third direction D3, the barrier layer 400 may have a thickness t400. In some embodiments, the first thickness t1 of the barrier layer 400 located below the first gate portion 500a may be greater than the second thickness t2 of the barrier layer 400 located below the second gate portion 500b. In some embodiments, the thickness t400 may be greater than the first thickness t1 and the second thickness t2. Therefore, when the two-dimensional electron gas 301 under the first gate portion 500a and the second gate portion 500b are both discontinuous, the carrier concentration of the two-dimensional electron gas 301 under the first gate portion 500a can still be greater than the carrier concentration of the two-dimensional electron gas 301 under the second gate portion 500b.

Accordingly, in the semiconductor device 6, the semiconductor structure including the first gate portion 500a is an enhancement type HEMT (Vt1>0), and the semiconductor structure including the second gate portion 500b is an enhancement type HEMT (Vt2>0), and Vt2>Vt1 is satisfied, thereby making the electric field distribution more uniform, improving reliability and/or avoiding degradation of the semiconductor device.

8A and 8B, they are schematic cross-sectional views of a semiconductor device 7 according to an embodiment of the present disclosure. As shown in FIG. 8A and FIG. 8B, in some embodiments, an insulating layer 503 may be disposed between the barrier layer 400 and the second gate portion 500b. In some embodiments, the bottom surface of the first gate portion 500a and the bottom surface of the second gate portion 500b may be lower than the top surface of the barrier layer 400. In some embodiments, the insulating layer 503 may not be disposed between the barrier layer 400 and the first gate portion 500a.

Accordingly, in the semiconductor device 7, the semiconductor structure including the first gate portion 500a is an enhanced HEMT (Vt1>0), and the semiconductor structure including the second gate portion 500b is an enhanced MIS-HEMT (Vt2>0), and Vt2>Vt1 is satisfied, thereby making the electric field distribution more uniform, improving reliability and/or avoiding degradation of the semiconductor device.

In some embodiments, any of the semiconductor devices 1-7 may be further processed to form a power device array. In some embodiments, the semiconductor devices 1-7 disclosed herein may be used in any combination. In some embodiments, the top view of the semiconductor device may be combined with the cross-sectional view of the semiconductor device in any combination.

Accordingly, the present disclosure adjusts the electric field distribution in the semiconductor device by making the first critical voltage of the first gate portion smaller than the second critical voltage of the second gate portion. For example, in a top view, there is a problem of excessive electric field intensity and over-concentration at the tip of the drain electrode (e.g., the second drain portion), which results in excessive hot carrier concentration at the tip of the drain electrode. Therefore, the present disclosure allows the two portions in the gate electrode to have different critical voltages, which can reduce excessive concentration of the electric field distribution and reduce hot carriers, thereby making the electric field distribution more uniform, improving reliability and/or avoiding degradation of the semiconductor device.

In detail, when the first gate portion may be disposed between the second source portion and the second drain portion, and the second gate portion may be disposed between the first source portion and the second drain portion, the critical voltage may be adjusted by adjusting the two-dimensional electron gas concentrations below the first gate portion and below the second gate portion. For example, the critical voltages of the first gate portion and the second gate portion may be adjusted by adjusting a combination of types of HEMTs (depletion-type HEMT, depletion-type MIS-HEMT, enhancement-type HEMT, enhancement-type MIS-HEMT). For example, the type of HEMT can be adjusted by adjusting the thickness of the barrier layer, setting an adjustment structure, setting an insulating layer, etc.

The scope of protection of this disclosure is not limited to the processes, machines, manufactures, material compositions, devices, methods, and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the relevant technical field can understand from the content of this disclosure that the processes, machines, manufactures, material compositions, devices, methods, and steps currently or in the future can be used according to this disclosure as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufactures, material compositions, devices, methods, and steps. Any embodiment or claim of this disclosure does not need to achieve all the purposes, advantages, and/or features described in this disclosure.

Several embodiments are summarized above so that those with ordinary knowledge in the art to which the present disclosure belongs can better understand the perspectives of the embodiments of the present disclosure. Those with ordinary knowledge in the art to which the present disclosure belongs should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and/or advantages as the embodiments herein. Those with ordinary knowledge in the art to which the present disclosure belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure.

1, 2, 3, 4, 5, 6, 7: semiconductor device 100: substrate 200: buffer layer 300: channel layer 301: two-dimensional electron gas 400: barrier layer 500: gate electrode 500a: first gate portion 500b: second gate portion 501: first compound semiconductor layer 502: first compound semiconductor layer 503: insulating layer 520: source electrode 520a: first source portion 520b: second source portion 521: source end portion 540: drain electrode 541: drain end portion 540a: first drain part 540b: second drain part A-A’, B-B’: cross section D1: first direction D2: second direction D3: third direction t400, t502: thickness t1: first thickness t2: second thickness

The present disclosure may be more fully understood from the following detailed description when read in conjunction with the drawings. It is noteworthy that, in accordance with standard practice in the industry, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily enlarged or reduced for clarity. FIG. 1 is a schematic top view of a semiconductor device according to an embodiment of the present disclosure. FIG. 2A and FIG. 2B are schematic cross-sectional views of a semiconductor device according to an embodiment of the present disclosure, respectively. FIG. 3A and FIG. 3B are schematic cross-sectional views of a semiconductor device according to an embodiment of the present disclosure, respectively. FIG. 4A and FIG. 4B are schematic cross-sectional views of a semiconductor device according to an embodiment of the present disclosure, respectively. FIG. 5A and FIG. 5B are schematic cross-sectional views of a semiconductor device according to an embodiment of the present disclosure, respectively. FIG. 6A and FIG. 6B are schematic cross-sectional views of a semiconductor device according to an embodiment of the present disclosure. FIG. 7A and FIG. 7B are schematic cross-sectional views of a semiconductor device according to an embodiment of the present disclosure. FIG. 8A and FIG. 8B are schematic cross-sectional views of a semiconductor device according to an embodiment of the present disclosure.

1:Semiconductor devices

100: Substrate

500: Gate electrode

500a: First gate part

500b: Second gate part

520: Source electrode

521: Source end

520a: first source portion

520b: Second source portion

540: Drain electrode

541: Drain end

540a: First drain part

540b: Second drain part

A-A’, B-B’: Section

D1: First direction

D2: Second direction

D3: Third direction

Claims (10)

A semiconductor device comprises: a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a gate electrode disposed on the barrier layer and comprising a first gate portion and a second gate portion connected to each other; a source electrode disposed on the barrier layer; and a drain electrode disposed on the barrier layer, wherein a first critical voltage of the first gate portion between the source electrode and the drain electrode is less than a second critical voltage of the second gate portion between the source electrode and the drain electrode, In a top view, the first gate portion includes a straight line portion and a first arc portion, and the second gate portion includes a second arc portion, a first end of the straight line portion is connected to the first arc portion, and a second end of the straight line portion is connected to the second arc portion. A semiconductor device as described in claim 1, wherein the carrier concentration of the two-dimensional electron gas located below the first gate portion is greater than the carrier concentration of the two-dimensional electron gas located below the second gate portion. A semiconductor device as described in claim 1, wherein the source electrode comprises: a first source portion extending along a first direction; and a second source portion connected to the first source portion and extending along a second direction different from the first direction, and the first gate portion is located between the second source portion and the drain electrode, and the second gate portion is located between the first source portion and the drain electrode. A semiconductor device as described in claim 3, wherein the drain electrode comprises: a first drain portion extending along the first direction; and a second drain portion connected to the first drain portion and extending along the second direction, and the first gate portion is located between the second source portion and the second drain portion, and the second gate portion is located between the first source portion and the second drain portion. A semiconductor device as described in claim 1, wherein a first thickness of the barrier layer located below the first gate portion is greater than a second thickness of the barrier layer located below the second gate portion. The semiconductor device as described in claim 1 further includes: an adjustment structure disposed below the second gate portion and including a P-type doped compound semiconductor or a halogen-doped compound semiconductor, wherein the first gate portion contacts the barrier layer. The semiconductor device as described in claim 1 further comprises: an insulating layer disposed between the barrier layer and the first gate portion, wherein the second gate portion contacts the barrier layer. A semiconductor device as described in claim 7, wherein a bottom surface of the first gate portion is higher than a top surface of the barrier layer. The semiconductor device as described in claim 1 further comprises: an insulating layer disposed between the barrier layer and the second gate portion, wherein the bottom surface of the first gate portion is lower than the top surface of the barrier layer. A method for forming a semiconductor device, comprising: providing a substrate; forming a channel layer on the substrate; forming a barrier layer on the channel layer; forming a gate electrode on the barrier layer, wherein the gate electrode comprises a first gate portion and a second gate portion connected to each other; forming a source electrode on the barrier layer; and forming a drain electrode on the barrier layer, wherein a first critical voltage of the first gate portion between the source electrode and the drain electrode is less than a second critical voltage of the second gate portion between the source electrode and the drain electrode, In a top view, the first gate portion includes a straight line portion and a first arc portion, and the second gate portion includes a second arc portion, a first end of the straight line portion is connected to the first arc portion, and a second end of the straight line portion is connected to the second arc portion.

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