TWI889081B - Wiring substrate and manufacturing method thereof - Google Patents

Abstract

A wiring substrate according to the present disclosure includes: a first insulating layer having a first surface; a second insulating layer located on the first surface and having a second surface; a first groove having a first inner surface and a second groove having a second inner surface which are recessed from the second surface to the side of the first insulating layer; a first wiring conductor including a wide width pattern having a width of 150 μm or more and located from the first groove to the first surface; and a second wiring conductor including a narrow width pattern having a width of 15 μm or less and located in the second groove. The first wiring conductor includes: a first base metal layer located on the first surface; a first electrolytic plating layer located on the first base metal layer with a side surface becoming one part of a first inner surface; a second base metal layer located on the first inner surface and connected to the side surface of the first electrolytic plating layer; and a second electrolytic plating layer located on the second base metal layer and filled in the first groove. The second wiring conductor includes: a third base metal layer located on the second inner surface; and a third electrolytic plating layer located on the third base metal layer and filled in the second groove.

Description

Wiring board and manufacturing method thereof

This disclosure relates to a wiring board and a method for manufacturing the same.

The method for forming wiring conductors on wiring substrates has always been a semi-additive process. The semi-additive process is a method for forming wiring conductors in the following steps. First, a thin base metal layer is formed on the exposed surface of the insulating layer by electroless plating or sputtering. Then, an anti-plating layer having an opening corresponding to the pattern of the wiring conductor is formed on the base metal layer. Then, an electrolytic plating layer is formed on the base metal layer exposed in the opening of the anti-plating layer. Then, after the anti-plating layer is peeled off and removed, the base metal layer not covered by the electrolytic plating layer is etched away.

However, the wiring conductors of wiring substrates are becoming increasingly miniaturized. In recent years, there is even a demand for wiring substrates where the width of the wiring conductor is less than 15μm, and the spacing between adjacent wiring conductors is less than 15μm. As a result, on wiring substrates with narrower wiring conductor widths (e.g., less than 15μm), the bonding area between the insulating layer and the wiring conductor through the base metal layer becomes smaller. Therefore, the wiring conductor is easily peeled off from the insulating layer. As a result, the reliability of electrical insulation between adjacent wiring conductors is reduced.

Therefore, as described in Patent Document 1, a method for forming a wiring conductor is proposed, wherein the wiring conductor is composed of a base metal layer and an electrolytic coating layer remaining in a groove. First, a groove of a predetermined depth corresponding to the pattern of the wiring conductor is formed on the surface of the insulating layer by laser processing. Then, a thin base metal layer is formed on the surface of the insulating layer including the inner surface of the groove by electroless plating or sputtering. Then, an electrolytic coating layer of a thickness that will fill the groove is formed on the base metal layer. Finally, the base metal layer and the electrolytic coating layer on the insulating layer are polished and removed by chemical mechanical polishing.

According to the method disclosed in Patent Document 1, trenches for wiring conductors with a narrow width (e.g., less than 15 μm) can be well filled by electrolytic coating. However, it is difficult to well fill trenches for wiring conductors with a wider width (e.g., more than 150 μm) by electrolytic coating. As a result, in the case of a wiring conductor with a wider width, the upper surface of the wiring conductor will be greatly depressed and lack flatness. If the thickness of the electrolytic coating is formed thicker in order to eliminate the depression, the stress generated when the electrolytic coating is formed will increase. Therefore, a greater stress will act between the wider wiring conductor and the inner wall of the groove through the base metal layer, making the wider wiring conductor easy to peel off.

[Prior Art Literature]

[Patent Literature]

[Patent document 1] Japanese Patent Publication No. 2004-149926

The subject of this disclosure is to provide a wiring substrate in which both narrow-width wiring conductors and wide-width wiring conductors are not easily peeled off and have high relative positional accuracy.

The wiring substrate disclosed in the present invention comprises: a first insulating layer having a first upper surface; a second insulating layer located on the first upper surface and having a second upper surface; a first base metal layer located on the first upper surface; a first electrolytically plated layer located on the first base metal layer; a first trench recessed from the second upper surface along the side surface of the first electrolytically plated layer toward the side of the first insulating layer and having a first inner surface. The first inner surface includes the side surface of the first electrolytic coating layer as a part of the inner surface; the second trench has a second inner surface that is recessed from the second upper surface toward the first insulating layer side; the first wiring conductor is configured to extend from the first trench to the first upper surface and include a wide pattern with a width of more than 150 μm; and the second wiring conductor is located in the second trench and includes a narrow pattern with a width of less than 15 μm. The first wiring conductor includes: a second base metal layer located on the first inner surface and connected to the side surface of the first electrolytic coating layer; and a second electrolytic coating layer located on the second base metal layer and filled in the first trench. The second wiring conductor includes: a third base metal layer located on the second inner surface; and a third electrolytic coating layer located on the third base metal layer and filled in the second trench.

The manufacturing method of the wiring board disclosed in the present invention comprises: forming a first insulating layer having a first upper surface; forming a first base metal layer and a first electrolytic coating layer on the first base metal layer and having a width of 150 μm or more on the first upper surface; forming a second insulating layer covering the first upper surface and the wide pattern and having a second upper surface; ; forming a first trench recessed from the second upper surface along the side of the first electrolytic coating layer toward the side of the first insulating layer and having a first inner surface including the side of the first electrolytic coating layer as a part of the inner surface, and a second trench having a second inner surface separated from the side of the first electrolytic coating layer; forming a second base metal layer covering the first inner surface, and a second base metal layer covering the second inner surface; a third base metal layer, a fourth base metal layer continuous with the second base metal layer and the third base metal layer and covering the second upper surface, a second electrolytic coating layer located on the second base metal layer and filling the thickness of the first trench, a third electrolytic coating layer located on the third base metal layer and filling the thickness of the second trench, and a fourth electrolytic coating layer continuous with the second electrolytic coating layer and the third electrolytic coating layer The step of forming a fourth electrolytically plated layer on the fourth base metal layer; and the step of removing at least the fourth base metal layer and the fourth electrolytically plated layer on the second upper surface, thereby forming a first wiring conductor configured to extend from the first trench to the first upper surface and include a wide pattern, and forming a second wiring conductor located in the second trench and including a narrow pattern with a width of less than 15μm.

The wiring substrate disclosed in the present invention has a structure as described in the above-mentioned [Means for Solving the Problem], so both the narrow-width wiring conductor and the wide-width wiring conductor are not easy to be peeled off, and the mutual position accuracy is also high.

10: Core substrate

11: Core insulation layer

11a: Filling with resin

12: Core conductor

12a: Core conductor layer

12b: Through-hole conductor

20: Additional floor

21: Add insulation layer

21a: First insulating layer

21b: Second insulating layer

21c: The third insulating layer

21d: Fourth insulation layer

21e: Fifth insulation layer

22: Add conductor layer

22a: First base metal layer

22b: First electrolytic coating

22c: Second base metal layer

22d: Second electrolytic coating

22e: Third base metal layer

22f: The third electrolytic coating

22g: Fourth base metal layer

22h: Fourth electrolytic coating

23: First wiring conductor

24: Second wiring conductor

25: Third wiring conductor

26: Electrode

30: Solder resist layer

100,200,300,400:Wiring substrate

121b: First through-hole conductor

122b: Second through-hole conductor

f1: first upper surface

f2: Second upper surface

f3: The third upper surface

f4: the fourth upper surface

G1: First groove

G2: Second groove

G3: The third groove

n1: first inner surface

n2: Second inner surface

NP: Narrow pattern

R: Resistors

TH:Through hole

TH2: Second perforation

V1, V2: through hole

W1: Width

W2: Width

WP: Wide Image

WP2: Second widest pattern

FIG1 is an explanatory diagram showing a cross section of a wiring substrate of the first embodiment of the present disclosure.

FIG2 is an explanatory diagram for explaining the manufacturing steps of the wiring substrate of the first embodiment of the present disclosure.

FIG3 is an explanatory diagram for explaining the manufacturing steps of the wiring substrate of the first embodiment of the present disclosure.

FIG4 is an explanatory diagram for explaining the manufacturing steps of the wiring substrate of the first embodiment of the present disclosure.

FIG5 is an explanatory diagram for explaining the manufacturing steps of the wiring substrate of the first embodiment of the present disclosure.

FIG6 is an explanatory diagram for explaining the manufacturing steps of the wiring substrate of the first embodiment of the present disclosure.

FIG. 7 is an explanatory diagram showing a cross section of a wiring substrate of the second embodiment of the present disclosure.

FIG8 is an explanatory diagram showing a cross section of a wiring substrate of the third embodiment of the present disclosure.

FIG. 9 is an explanatory diagram showing a cross section of a wiring substrate of the fourth embodiment of the present disclosure.

FIG10 is a schematic three-dimensional diagram showing only the conductor portion of the wiring substrate shown in FIG9.

FIG. 11 is an explanatory diagram for explaining the manufacturing steps of the wiring substrate of the fourth embodiment of the present disclosure.

FIG. 12 is an explanatory diagram for explaining the manufacturing steps of the wiring substrate of the fourth embodiment of the present disclosure.

FIG. 13 is an explanatory diagram for explaining the manufacturing steps of the wiring substrate of the fourth embodiment of the present disclosure.

FIG. 14 is an explanatory diagram for explaining the manufacturing steps of the wiring substrate of the fourth embodiment of the present disclosure.

FIG. 15 is an explanatory diagram for explaining the manufacturing steps of the wiring substrate of the fourth embodiment of the present disclosure.

The wiring substrate of the present disclosure is described according to the drawings. FIG. 1 is a schematic diagram showing a portion of a cross section of a wiring substrate 100 of the first embodiment of the present disclosure. The wiring substrate 100 of the first embodiment includes a core substrate 10, a build-up layer 20 located on the surface of the core substrate 10, and a solder resist layer 30 located on the surface of the build-up layer 20. In FIG. 1, only a portion of the upper surface side of the wiring substrate 100 is shown.

樹脂、聚醯亞胺樹脂、聚苯醚樹脂及液晶聚合物等樹脂所形成。此等樹脂可單獨使用，亦可併用兩種以上。核心絕緣層11中，可加入玻纖纖維布(glass cloth)等補強材，亦可使絕緣粒子分散於核心絕緣層11中。絕緣粒子並沒有限制，舉例來說有例如二氧化矽(silica)、氧化鋁(alumina)、硫酸鋇、滑石、黏土、玻璃、碳酸鈣及氧化鈦等無機絕緣性填料。核心絕緣層11具有例如0.1mm以上2.0mm以下的厚度。 The core substrate 10 includes a core insulating layer 11 and a core conductor 12. The core insulating layer 11 is made of, for example, epoxy resin, dimaleimide-tris

The core insulating layer 11 is formed of resins such as resins such as polyimide resins, polyphenylene ether resins and liquid crystal polymers. These resins can be used alone or in combination of two or more. Reinforcing materials such as glass cloth can be added to the core insulating layer 11, and insulating particles can also be dispersed in the core insulating layer 11. There is no limitation on the insulating particles, and examples include inorganic insulating fillers such as silica, alumina, barium sulfate, talc, clay, glass, calcium carbonate and titanium oxide. The core insulating layer 11 has a thickness of, for example, more than 0.1 mm and less than 2.0 mm.

The core conductor 12 includes a core conductor layer 12a and a through hole conductor 12b. The core conductor layer 12a is located on the upper and lower surfaces of the core insulating layer 11. The core conductor layer 12a is formed by a conductor such as copper, such as copper foil or copper plating. The thickness of the core conductor layer 12a is not particularly limited, for example, it can be greater than 5μm and less than 50μm.

The through-hole conductor 12b is located in the through-hole TH, which penetrates the core insulating layer 11 from top to bottom. The through-hole conductor 12b electrically connects the core conductor layers 12a located on the upper and lower surfaces of the core insulating layer 11. The through-hole conductor 12b is formed, for example, by a conductor plated with a metal such as copper plating. The through-hole conductor 12b is integrally connected to the core conductor layers 12a on both sides of the core insulating layer 11. The through-hole conductor 12b may be formed only on the inner wall surface of the through-hole TH, or may be filled in the through-hole TH.

樹脂、聚醯亞胺樹脂、聚苯醚樹脂及液晶聚合物等樹脂所形成。此等樹脂可單獨使用，亦可併用兩種以上。第一絕緣層21a中亦可絕緣粒子分散於第一絕緣層21a中。絕緣粒子並沒有限制，舉例來說有例如二氧化矽、氧化鋁、硫酸鋇、滑石、黏土、玻璃、碳酸鈣及氧化鈦等無機絕緣性填料。第一絕緣層21a具有例如10μm以上50μm以下的厚度。 The built-up layer 20 includes a built-up insulating layer 21 and a built-up conductive layer 22. The built-up insulating layer 21 includes: a first insulating layer 21a and a second insulating layer 21b; the first insulating layer 21a has a first upper surface f1; the second insulating layer 21b is located on the first upper surface f1 of the first insulating layer 21a and has a second upper surface f2. The first insulating layer 21a is made of, for example, epoxy resin, dimaleimide-trifluoroethylene, or polytetrafluoroethylene.

The first insulating layer 21a is formed of resins such as polyimide resin, polyphenylene ether resin and liquid crystal polymer. These resins can be used alone or in combination of two or more. Insulating particles can also be dispersed in the first insulating layer 21a. There is no limitation on the insulating particles, and examples include inorganic insulating fillers such as silicon dioxide, aluminum oxide, barium sulfate, talc, clay, glass, calcium carbonate and titanium oxide. The first insulating layer 21a has a thickness of, for example, more than 10 μm and less than 50 μm.

The second insulating layer 21b is located on the first upper surface f1 of the first insulating layer 21a. The second insulating layer 21b is made of the same resin as the resin forming the first insulating layer 21a, and one type can be used alone or two or more types can be used in combination. In addition, in the second insulating layer 21b, the same insulating particles as those in the first insulating layer 21a can be dispersed in the second insulating layer 21b. The thickness of the second insulating layer 21b is not limited, and for example, it can be formed to be thinner than the thickness of the first insulating layer 21a. The second insulating layer 21b has a thickness of, for example, 5 μm or more and 25 μm or less.

The core insulating layer 11, the first insulating layer 21a and the second insulating layer 21b may be formed of the same resin or different resins. In addition, when insulating particles are dispersed in the core insulating layer 11, the first insulating layer 21a and the second insulating layer 21b, the insulating particles may be the same or different.

The additional conductive layer 22 includes a first base metal layer 22a, a first electrolytically plated layer 22b, a second base metal layer 22c, a second electrolytically plated layer 22d, a third base metal layer 22e, and a third electrolytically plated layer 22f. The first base metal layer 22a is located on the first upper surface f1 of the first insulating layer 21a. The first base metal layer 22a is formed of a metal such as copper. The first base metal layer 22a has a thickness of, for example, 0.1 μm or more and 0.5 μm or less. As shown in FIG. 1 , the first base metal layer 22a can be disposed on the inner surface of a via hole V1 penetrating the first insulating layer 21a. The first base metal layer 22a has the function of improving the coating fixation of the first electrolytic coating layer 22b.

The first electrolytic coating layer 22b is located on the first base metal layer 22a. If the first electrolytic coating layer 22b is formed by electrolytic coating, there is no other limitation, for example, it is formed by metal such as copper. The first electrolytic coating layer 22b has a thickness of, for example, more than 5μm and less than 25μm.

The second base metal layer 22c is located on the first inner surface n1 of the first trench G1 which is recessed from the second upper surface f2 of the second insulating layer 21b to the side of the first insulating layer 21a. The first trench G1 is connected to the side surface of the first electrolytic coating layer 22b. That is, the side surface of the first electrolytic coating layer 22b becomes a part of the first inner surface n1 of the first trench G1. The second base metal layer 22c is formed of a metal such as copper. The second base metal layer 22c has a thickness of, for example, 0.1 μm or more and 0.5 μm or less. The second base metal layer 22c has the function of improving the coating fixation of the second electrolytic coating layer 22d.

The second electrolytic coating layer 22d is filled in the first trench G1 formed with the second base metal layer 22c. If the second electrolytic coating layer 22d is formed by electrolytic coating, there is no other limitation, and it can be formed of metals such as copper. The side and bottom surfaces of the second electrolytic coating layer 22d are located in the first trench G1 through the second base metal layer 22c. Therefore, good adhesion can be exerted to reduce the peeling of the second electrolytic coating layer 22d.

The third base metal layer 22e is located on the second inner surface n2 of the second groove G2 which is recessed from the second upper surface f2 of the second insulating layer 21b to the first insulating layer 21a. The third base metal layer 22e is formed of a metal such as copper. The third base metal layer 22e has a thickness of, for example, 0.1 μm to 0.5 μm. As shown in FIG. 1 , the third base metal layer 22e can be located on the inner surface of the through hole V2 penetrating the first insulating layer 21a. The third base metal layer 22e has the function of improving the coating fixation of the third electrolytic coating layer 22f.

The third electrolytic coating layer 22f is filled in the second trench G2 formed with the third base metal layer 22e. If the third electrolytic coating layer 22f is formed by electrolytic coating, there is no other limitation, and it can be formed by metals such as copper. The side and bottom surfaces of the third electrolytic coating layer 22f are located in the second trench G2 through the third base metal layer 22e. Therefore, good adhesion can be exerted to reduce the peeling of the third electrolytic coating layer 22f.

The additional conductor layer 22 includes a first wiring conductor 23 and a second wiring conductor 24 having different widths. The first wiring conductor 23 includes a wide pattern WP having a width W1 of 150 μm or more. On the other hand, the first wiring conductor 23 does not include a pattern having a width of less than 15 μm. The first wiring conductor 23 is composed of a first base metal layer 22a and a first electrolytic coating layer 22b on the first insulating layer 21a, and a second base metal layer 22c and a second electrolytic coating layer 22d of the first trench G1. The first wiring conductor 23 mainly has the functions of grounding and power supply. The width W1 can be defined as the length between two opposite sides of the first wiring conductor 23, for example.

The second base metal layer 22c and the second electrolytic coating layer 22d of the first trench G1 of the first wiring conductor 23 are located between the side surface of the first electrolytic coating layer 22b and the second insulating layer 21b. That is, the side surface of the first electrolytic coating layer 22b constituting the first wiring conductor 23 does not contact the second insulating layer 21b. Therefore, the side surface of the first electrolytic coating layer 22b does not contact the second insulating layer 21b, thereby eliminating the stress directly acting on the second insulating layer 21b between the side surface of the first electrolytic coating layer 22b and the second insulating layer 21b. As a result, peeling of the first electrolytic coating layer 22b can be reduced.

The arithmetic average roughness Ra of the side surface of the first electrolytic coating layer 22b is not limited, for example, it can be greater than 150nm and less than 300nm. If the arithmetic average roughness Ra of the side surface of the first electrolytic coating layer 22b is greater than 150nm and less than 300nm, the side surface of the first electrolytic coating layer 22b can be firmly coated on the second base metal layer 22c of the first inner surface n1 of the first groove G1, and the peeling of the first electrolytic coating layer 22b can be further reduced.

The second base metal layer 22c and the second electrolytic coating layer 22d of the first trench G1 have the function of preventing the first electrolytic coating layer 22b from peeling off and improving the positional accuracy between the first wiring conductor 23 and the second wiring conductor 24. The width of the first trench G1 is not limited, and can be, for example, 5 μm to 100 μm. The depth of the first trench G1 is not limited, and can be, for example, 5 μm to 75 μm. The width of the first trench G1 can be defined, for example, as the length between two opposing edges of the second insulating layer 21b at the opening of the first trench G1. The depth of the first trench G1 can be defined, for example, as the length from a position at the same height as the second upper surface f2 where the opening of the first trench G1 is located to a position of the first trench G1 closest to the core substrate 10.

In the first inner surface n1 of the first trench G1, the arithmetic mean roughness Ra of the surface other than the side surface of the first electrolytic coating layer 22b is not limited, and can be, for example, 50 nm or more and 100 nm or less. In the first inner surface n1 of the first trench G1, if the arithmetic mean roughness Ra of the surface other than the side surface of the first electrolytic coating layer 22b is 50 nm or more and 100 nm or less, the second base metal layer 22c can be firmly coated on the first inner surface n1 of the first trench G1, and the peeling of the second base metal layer 22c can be further reduced.

The second wiring conductor 24 is composed of the third base metal layer 22e and the third electrolytic coating layer 22f of the second groove G2. The second wiring conductor 24 includes a narrow pattern NP having a width W2 of less than 15μm. On the other hand, the second wiring conductor 24 does not include a pattern with a width of more than 150μm. There is no limit to the depth of the second groove G2, for example, it can be more than 5μm and less than 25μm. The second wiring conductor 24 mainly has the function of transmitting signals. In Figure 1, a second wiring conductor 24 that appears to be relatively wide is shown. However, the second wiring conductor 24 that appears to be relatively wide is shown in a cross-section cut in the long side direction. The width W2 can be defined as the shortest length between two opposite sides in the second wiring conductor 24, for example. The depth of the second trench G2 can be defined as the length from the position at the same height as the second upper surface f2 where the opening of the second trench G2 is located to the position of the second trench G2 closest to the core substrate 10, for example.

The arithmetic mean roughness Ra of the second inner surface n2 of the second trench G2 is not limited, for example, it can be 50nm or more and 100nm or less. If the arithmetic mean roughness Ra of the second inner surface n2 of the second trench G2 is 50nm or more and 100nm or less, the third base metal layer 22e can be firmly coated on the second inner surface n2 of the second trench G2, and the peeling of the third base metal layer 22e can be further reduced. The second wiring conductor 24 has a surface roughness with an arithmetic mean roughness Ra of 50nm or more and 100nm or less corresponding to the roughness of the second inner surface n2 of the second trench G2. The smaller the roughness, the lower the transmission loss when the second wiring conductor 24 transmits a high-frequency signal, which is beneficial.

A solder resist layer 30 is provided on the build-up layer 20. The solder resist layer 30 is formed of, for example, an acrylic modified epoxy resin. The solder resist layer 30 has a function of protecting the conductor layer from solder when, for example, mounting electronic components or connecting to a motherboard, etc. The solder resist layer 30 is formed with an opening portion for exposing a portion of the first wiring conductor 23 or the second wiring conductor 24 located on the surface of the build-up layer 20. The portion of the first wiring conductor 23 or the second wiring conductor 24 exposed from the opening portion functions as a pad when, for example, mounting a semiconductor element, etc.

Next, the method for manufacturing the wiring substrate disclosed in the present invention is described. The method for manufacturing the wiring substrate disclosed in the present invention includes the following steps (a) to (f).

(a) A step of forming a first insulating layer having a first upper surface.

(b) On the first upper surface, a step of forming a wide pattern having a width W1 of 150 μm or more and including a first base metal layer and a first electrolytic coating layer located on the first base metal layer.

(c) A step of forming a second insulating layer covering the first upper surface and the wide pattern and having a second upper surface.

(d) forming a first trench recessed from the second upper surface toward the side of the first insulating layer and having a first inner surface connected to the side surface of the wide pattern and a second trench having a second inner surface separated from the wide pattern.

(e) forming a second base metal layer covering the first inner surface, a third base metal layer covering the second inner surface, and a fourth base metal layer continuous with the second base metal layer and the third base metal layer and covering the second upper surface; and forming a second electrolytic coating layer located on the second base metal layer and filling the thickness of the first trench, a third electrolytic coating layer filling the thickness of the second trench, and a fourth electrolytic coating layer continuous with the second electrolytic coating layer and the third electrolytic coating layer and located on the fourth base metal layer.

(f) At least the fourth base metal layer and the fourth electrolytic coating layer located on the second upper surface are removed to form a first wiring conductor configured to extend from the first trench to the first upper surface and include a wide pattern, and a second wiring conductor located in the second trench and including a narrow pattern of a width W2 of less than 15 μm.

The manufacturing method of the wiring substrate disclosed in the present invention is described based on Figures 2 to 6. Figures 2 to 6 are explanatory diagrams used to illustrate the manufacturing steps of the wiring substrate 100 of the first embodiment.

First, as shown in FIG2(A), prepare a core substrate 10. The core substrate 10 includes a core insulating layer 11 and a core conductor 12. The core insulating layer 11 and the core conductor 12 are as described above, and their detailed description is omitted here.

Next, the step of forming the first insulating layer (step (a)) is described. As shown in FIG2(B), the first insulating layer 21a is formed into a core insulating layer 11 and a core conductor 12 covering the core substrate 10. The first insulating layer 21a is as described above, and its detailed description is omitted here. The first insulating layer 21a is formed, for example, by stacking a thermosetting resin sheet for the first insulating layer 21a on the core substrate 10 and applying pressure and heat from top and bottom to thermally cure it. As shown in FIG2(C), a through hole V1 is formed in the first insulating layer 21a as needed. The through hole V1 is formed by laser processing such as CO ₂ laser, UV-YAG laser, and excimer laser.

Next, the step of forming a wide pattern including a first base metal layer and a first electrolytic plating layer located on the first base metal layer and having a width of 150 μm or more is described (step (b)). As shown in FIG. 2 (D), a first base metal layer 22a such as copper is deposited on the upper surface of the first insulating layer 21a and the inner surface of the through hole V1 by electroless plating. Palladium can be used as a catalyst during the electroless plating. The deposited first base metal layer 22a has a thickness of, for example, 0.1 μm or more and 0.5 μm or less.

After the first base metal layer 22a of copper or the like is deposited by electroless plating, as shown in FIG3(A), the portion where the first electrolytic plating layer 22b is not to be formed is coated with a resist R. After coating with the resist R, as shown in FIG3(B), the first electrolytic plating layer 22b of copper or the like is deposited by electrolytic plating. The first electrolytic plating layer 22b has a thickness of, for example, 5 μm to 25 μm. A wide pattern can be formed by making the width of the portion where the first electrolytic plating layer 22b is deposited to be 150 μm or more. Then, as shown in FIG3(C), the resist R is removed, and then, as shown in FIG3(D), the portion of the first base metal layer 22a previously covered by the resist R is removed.

In this way, a wide pattern WP is formed on the first insulating layer 21a. The wide pattern WP is composed of the first base metal layer 22a and the first electrolytic coating layer 22b located on the first base metal layer 22a and has a width W1 of more than 150μm.

The side surface of the first electrolytic coating 22b can be roughened to make the arithmetic average roughness Ra between 150nm and 300nm. By performing such a roughening treatment, the second base metal layer 22c described later can be firmly coated on the side surface of the first electrolytic coating 22b, and the peeling of the first electrolytic coating 22b can be further reduced.

Next, the step of forming a second insulating layer covering the upper surface and the wide pattern of the first insulating layer (step (c)) is described. As shown in FIG. 4(A), the second insulating layer 21b is formed to cover the first upper surface f1 and the wide pattern WP of the first insulating layer 21a. The second insulating layer 21b is formed, for example, by stacking a thermosetting resin sheet for the second insulating layer 21b on the first upper surface f1 and the wide pattern WP of the first insulating layer 21a and applying pressure and heat from top and bottom to thermally cure it.

Next, the step of forming a first trench recessed from the upper surface of the second insulating layer toward the side of the first insulating layer and having a first inner surface connected to the side surface of the wide pattern and a second trench having a second inner surface separated from the wide pattern (step (d)) is described. As shown in FIG. 4(B), a first trench G1 having a first inner surface n1 is formed at a position of the second insulating layer 21b connected to the side surface of the wide pattern WP; and a second trench G2 having a second inner surface n2 is formed at a position where the second wiring conductor 24 is to be formed. There is no limitation on the method of forming the first trench G1 and the second trench G2, and they can be formed by laser processing such as excimer laser, _CO2 laser and UV-YAG laser. From the point of being easier to form the first trench G1 and the second trench G2 of uniform depth, it is better to use excimer laser. There is no limitation on the depth of the first trench G1 and the second trench G2, for example, it can be more than 5μm and less than 25μm. As shown in FIG. 4(C), a through hole V2 can be formed in the first insulating layer 21a as needed. The through hole V2 can be formed by laser processing such as excimer laser, _CO2 laser and UV-YAG laser.

When forming the first trench G1 and the second trench G2, a trench forming process can be performed to make the roughness of the first inner surface n1 of the first trench G1 and the second inner surface n2 of the second trench G2, excluding the side surface of the wide pattern WP, become an arithmetic average roughness Ra of 50nm or more and 100nm or less. In this case, it is easier to form the inner surface to a predetermined roughness by using an excimer laser. By forming the first trench G1 and the second trench G2 in this way, the second base metal layer 22c and the third base metal layer 22e can be firmly covered on the first insulating layer 21a and the second insulating layer 21b, and the peeling of the second base metal layer 22c and the third base metal layer 22e can be further reduced.

Next, the steps of forming: a second base metal layer covering the first inner surface, a third base metal layer covering the second inner surface, and a fourth base metal layer continuous with the second base metal layer and covering the second upper surface; and forming: a second electrolytically plated layer located on the second base metal layer and filling the thickness of the first trench, a third electrolytically plated layer located on the third base metal layer and filling the thickness of the second trench, and a fourth electrolytically plated layer continuous with the second electrolytically plated layer and the third electrolytically plated layer and located on the fourth base metal layer (step (e)) are described.

As shown in FIG. 5(A), a second base metal layer 22c covering the first inner surface n1, a third base metal layer 22e covering the second inner surface n2, and a fourth base metal layer 22g continuous with the second base metal layer 22c and the third base metal layer 22e and covering the second upper surface f2 are formed. The second base metal layer 22c, the third base metal layer 22e, and the fourth base metal layer 22g are formed simultaneously, for example, by depositing a metal such as copper by electroless plating. In other words, the second base metal layer 22c, the third base metal layer 22e, and the fourth base metal layer 22g are metal layers formed by the same electroless plating process. When performing electroless plating, palladium can be used as a catalyst. The second base metal layer 22c, the third base metal layer 22e and the fourth base metal layer 22g have a thickness of, for example, 0.1 μm to 0.5 μm, and are also formed on the inner surface of the through hole V2.

After forming the second base metal layer 22c, the third base metal layer 22e and the fourth base metal layer 22g, as shown in Figure 5(B), a second electrolytic coating 22d located on the second base metal layer 22c and filling the thickness of the first groove G1, a third electrolytic coating 22f arranged on the third base metal layer 22e and filling the thickness of the second groove G2, and a fourth electrolytic coating 22h continuous with the second electrolytic coating 22d and the third electrolytic coating 22f and located on the fourth base metal layer 22g are formed. The second electrolytic coating 22d, the third electrolytic coating 22f, and the fourth electrolytic coating 22h are formed simultaneously by metals such as copper. In other words, the second electrolytic coating 22d, the third electrolytic coating 22f, and the fourth electrolytic coating 22h are coatings formed by the same electrolytic coating process.

Next, the step of removing at least the fourth base metal layer and the fourth electrolytic coating layer located on the second insulating layer to form a first wiring conductor configured to extend from the first trench to the first upper surface f1 and include a wide pattern, and forming a second wiring conductor located in the second trench and including a narrow pattern with a width of less than 15μm (step (f)) is described.

As shown in FIG. 5(C), at least the fourth base metal layer 22g and the fourth electrolytic coating layer 22h located on the second insulating layer 21b are removed. In this removal step, a portion of the second insulating layer 21b may be removed as needed. For example, in the case where the width near the opening of the second trench G2 exceeds 15μm, not only the fourth base metal layer 22g and the fourth electrolytic coating layer 22h located on the second insulating layer 21b may be removed, but also a portion of the second insulating layer 21b may be removed until the width of the second trench G2 is less than 15μm. In this way, a first wiring conductor 23 including a wide pattern WP, a second base metal layer 22c and a second electrolytic coating layer 22d remaining in the first trench G1 is formed, and a second wiring conductor 24 including a narrow pattern NP with a width of less than 15 μm is formed, and the narrow pattern NP includes a third base metal layer 22e and a third electrolytic coating layer 22f remaining in the second trench G2.

As described above, the first trench G1 connected to the side surface of the wide pattern WP constituting the first wiring conductor 23 and the second trench G2 separated from the wide pattern WP are formed in the same step (step (d)). After the second electrolytic coating layer 22d having a thickness filling the first trench G1 and the third electrolytic coating layer 22f having a thickness filling the second trench G2 are formed in step (e), at least the fourth base metal layer 22g and the fourth electrolytic coating layer 22h located on the second insulating layer 21b are removed in step (f). In this way, a first wiring conductor 23 is formed which is configured to extend from the first groove G1 to the first upper surface f1 and includes a wide pattern WP, and a second wiring conductor 24 is formed which is located in the second groove G2 and includes a narrow pattern NP with a width W2 of 15μm or less. As a result, the positional accuracy between the first wiring conductor 23 and the second wiring conductor 24 can be improved.

Steps (a) to (f) are repeated, and as shown in FIG. 6 , a build-up layer 20 having a desired number of layers is formed on the core substrate 10 . As described above, the build-up layer 20 includes: a first insulating layer 21a; a second insulating layer 21b, which is located on the first upper surface f1 of the first insulating layer 21a; a first trench G1 and a second trench G2, which are recessed from the second upper surface f2 of the second insulating layer 21b to the side of the first insulating layer 21a; a first wiring conductor 23, which is configured to extend from the first trench G1 to the first upper surface f1 of the first insulating layer 21a and includes a wide pattern WP with a width W1 of 150μm or more; and a second wiring conductor 24, which is located in the second trench G2 and includes a narrow pattern NP with a width W2 of 15μm or less.

Finally, the solder resist layer 30 is formed on the surface of the build-up layer 20, and the wiring board 100 shown in FIG. 1 is obtained. The solder resist layer 30 is formed by coating the surface of the build-up layer with a thin film such as acrylic modified epoxy resin and hardening it. The solder resist layer 30 is as described above, and its detailed description is omitted here.

Next, other wiring substrates disclosed in the present invention are described based on FIG. 7 . FIG. 7 is an explanatory diagram showing a cross section of a wiring substrate 200 of the second embodiment of the present invention. In the wiring substrate 200 shown in FIG. 7 , the same components as the wiring substrate 100 of the first embodiment are marked with the same symbols, and their detailed descriptions are omitted.

In the wiring substrate 100 of the first embodiment, the bottom surface of the second wiring conductor 24 (bottom surface of the third base metal layer 22e) is in contact with the first insulating layer 21a. In the wiring substrate 200 of the second embodiment, the bottom surface of the second wiring conductor 24 (bottom surface of the third base metal layer 22e) is not in contact with the first insulating layer 21a. That is, the second wiring conductor 24 (third base metal layer 22e and third electrolytic coating layer 22f) falls within the second insulating layer 21b. In other words, the depth of the second groove G2 is smaller than the thickness of the second insulating layer 21b. The wiring substrate 200 of the second embodiment is different from the wiring substrate 100 of the first embodiment in the configuration of the second wiring conductor 24.

When the first base metal layer 22a, the second base metal layer 22c, the third base metal layer 22e, and the fourth base metal layer 22g are formed by electroless plating, palladium may remain if palladium is used as a catalyst. If palladium remains, it is easy to migrate between the adjacent second wiring conductors 24 (third base metal layer 22e), between the second wiring conductors 24 and the first wiring conductors 23, or near the boundary between the first insulating layer 21a and the second insulating layer 21b. If the wiring substrate 200 of the second embodiment makes the second wiring conductor 24 fall into the second insulating layer 21b, the third base metal layer 22e will be far away from the boundary between the first insulating layer 21a and the second insulating layer 21b. As a result, the migration near the boundary can be reduced and the insulation reliability will be further improved.

The method for manufacturing the wiring substrate 200 of the second embodiment is to adjust the depth of the second trench G2 in the step of forming the first trench G1 and the second trench G2 (step (d)) so that the bottom surface of the second trench G2 falls within the second insulating layer 21b. That is, the depth of the second trench G2 is formed to be smaller than the thickness of the second insulating layer 21b. The depth of the second trench G2 is appropriately set according to the thickness of the second insulating layer 21b.

Next, another wiring substrate of the present disclosure is described based on FIG8. FIG8 is an explanatory diagram showing a cross section of a wiring substrate 300 of the third embodiment of the present disclosure. In the wiring substrate 300 shown in FIG8, the same components as the wiring substrate 100 of the first embodiment are marked with the same symbols, and their detailed descriptions are omitted.

In the wiring substrate 100 of the first embodiment, the upper surface of the first wiring conductor 23 (the upper surface of the first electrolytic coating layer 22b) is not covered by the second insulating layer 21b. In the wiring substrate 300 of the third embodiment, at least a portion of the upper surface of the first wiring conductor 23 (the upper surface of the first electrolytic coating layer 22b) is covered by the second insulating layer 21b without being exposed from the second insulating layer 21b. The wiring substrate 300 of the third embodiment is different from the wiring substrate 100 of the first embodiment in the configuration of the first wiring conductor 23.

For example, there may be a slight gap near the boundary between the second insulating layer 21b and the insulating layer located above it, and adjacent wiring conductors may be exposed at the boundary and migration may occur. In other words, migration is likely to occur near the boundary between the first wiring conductor 23 (first electrolytic coating layer 22b) and the second insulating layer 21b. For example, in the wiring substrate 300 of the third embodiment, at least a portion of the upper surface of the first wiring conductor 23 is covered by the second insulating layer 21b, and the upper surface of the first electrolytic coating layer 22b is away from the boundary between the upper surface of the second insulating layer 21b and the insulating layer located above it. As a result, the migration between the upper surface of the first electrolytic coating layer 22b and the upper surface of the second insulating layer 21b can be reduced, and the insulation reliability will be further improved.

The method for manufacturing the wiring substrate 300 of the third embodiment is to remove at least the fourth base metal layer 22g and the fourth electrolytic coating layer 22h located on the second insulating layer 21b in a manner such that at least a portion of the upper surface of the first wiring conductor 23 is not exposed in the step of forming the second wiring conductor (step (f)). If necessary, only the upper surface of the second insulating layer 21b may be removed.

Next, another wiring substrate of the present disclosure is described based on Figures 9 and 10. Figure 9 is an explanatory diagram showing a cross section of a wiring substrate 400 of the fourth embodiment of the present disclosure. Figure 10 is a three-dimensional diagram schematically showing only the conductor portion of the wiring substrate shown in Figure 9. In the wiring substrate 400 shown in Figure 9, the same components as the wiring substrate 100 of the first embodiment are marked with the same symbols, and their detailed descriptions are omitted.

In the wiring substrate 100 of the first embodiment, the bottom surface of the first wiring conductor 23 located in the first groove G1 (the bottom surface of the second base metal layer 22c) is located near the first upper surface f1 of the first insulating layer 21a. In the wiring substrate 400 of the fourth embodiment, the bottom surface of the first wiring conductor 23 located in the first groove G1 (the bottom surface of the second base metal layer 22c) is connected to the lower conductor (equivalent to the core conductor layer 12a in the wiring substrate 400 shown in FIG. 9). The wiring substrate 400 of the fourth embodiment is different from the wiring substrate 100 of the first embodiment in the configuration of the first wiring conductor 23.

In the wiring substrate 400 of the fourth embodiment, the bottom surface of the first wiring conductor 23 located in the first groove G1 is connected to the lower conductor, so the shielding property of the second wiring conductor 24 that functions as a wiring conductor for signals is improved. That is, the second wiring conductor 24 is shielded by the first wiring conductor 23 located on both sides of the second wiring conductor 24.

To connect the bottom surface of the first wiring conductor 23 located in the first trench G1 to the lower conductor, the above-mentioned manufacturing method (steps (a) to (f)) only needs to further include a step of forming a lower conductor layer on the surface of the first insulating layer 21a opposite to the first surface (step (g)). The lower conductor layer is equivalent to the core conductor layer 12a in the wiring substrate 400 shown in FIG. 9. After the lower conductor layer is formed in step (g), the first trench G1 can be formed to a depth reaching the lower conductor layer, and then a conductor that will become the first wiring conductor 23 can be formed in the first trench G1.

The wiring substrate 400 of the fourth embodiment may be further provided with a third insulating layer 21c, a fourth insulating layer 21d, a third trench G3 and a third wiring conductor 25 as shown in FIG9. The third insulating layer 21c is located on the second upper surface f2 of the second insulating layer 21b and has a third upper surface f3. The fourth insulating layer 21d is located on the third upper surface f3 of the third insulating layer 21c and has a fourth upper surface f4. The third trench G3 has a third inner surface that is recessed from the fourth upper surface f4 of the fourth insulating layer 21d toward the third insulating layer 21c. The third wiring conductor 25 is configured to extend from the third groove G3 to the third upper surface and includes a second wide pattern WP2 having a width of 150 μm or more.

The third insulating layer 21c and the fourth insulating layer 21d are made of the same resin as the resin forming the first insulating layer 21a. The resin may be used alone or in combination of two or more. In addition, the same insulating particles as those of the first insulating layer 21a may be dispersed in the third insulating layer 21c and the fourth insulating layer 21d. There is no limitation on the thickness of the third insulating layer 21c and the thickness of the fourth insulating layer 21d. For example, the thickness of the fourth insulating layer 21d may be thinner than the thickness of the third insulating layer 21c. The third insulating layer 21c has a thickness of, for example, more than 10 μm and less than 50 μm. The fourth insulating layer 21d has a thickness of, for example, 5 μm or more and 25 μm or less.

The third wiring conductor 25 is the same as the first wiring conductor 23 described above, and has a base metal layer and an electrolytic coating layer. In the description of each layer described above, the first insulating layer 21a is equivalent to the third insulating layer 21c, the first upper surface f1 is equivalent to the third upper surface, the first trench G1 is equivalent to the third trench G3, and the first inner surface n1 is equivalent to the third inner surface.

The third wiring conductor 25 located in the third groove G3 is connected to the first wiring conductor 23. In the cross-sectional view in the thickness direction of the wiring substrate, a portion of the second wiring conductor 24 is surrounded by the lower conductor (equivalent to the core conductor layer 12a in the wiring substrate 400 shown in FIG. 9), the first wiring conductor 23, and the third wiring conductor 25. That is, a coaxial wiring structure is formed in the build-up layer 20. Since the wiring substrate 400 of the fourth embodiment is formed with such a coaxial wiring structure, the shielding property of the second wiring conductor 24 that functions as a wiring conductor for signals is further improved.

To further provide the third insulating layer 21c, the fourth insulating layer 21d, the third trench G3 and the third wiring conductor 25, it is sufficient to include the following steps (h) to (l) in addition to the above-mentioned manufacturing method (steps (a) to (f)).

(h) A step of forming a third insulating layer 21c having a third upper surface on the second upper surface f2.

(i) On the third upper surface, a step of forming a second wide pattern WP2 having a width of 150 μm or more.

(j) A step of forming a fourth insulating layer 21d covering the third upper surface and the second wide pattern WP2 and having a fourth upper surface.

(k) A step of forming a third groove G3 that is recessed from the fourth upper surface toward the third insulating layer 21c side and that is connected to the side surface of the second wide pattern WP2 and reaches the first wiring conductor 23 through both sides of the second wiring conductor 24 when viewed from a top perspective.

(l) A step of forming a third wiring conductor 25 extending from the third groove G3 to the third upper surface and including the second wide pattern WP2 and partially connected to the first wiring conductor 23, across both sides of the second wiring conductor 24 when viewed from above.

The method for forming the third insulating layer 21c, the fourth insulating layer 21d, the second wide pattern WP2, the third trench G3 and the third wiring conductor 25 (steps (h) to (l)) can be carried out according to the method (steps) for forming the first insulating layer 21a, the second insulating layer 21b, the wide pattern WP, the first trench G1 and the first wiring conductor 23 described above.

As shown in FIG. 9 , the wiring substrate 400 of the fourth embodiment may further include a fifth insulating layer 21e having a plurality of electrodes 26 on the first upper surface f1 side. The fifth insulating layer 21e is made of the same resin as the resin forming the first insulating layer 21a described above. The resin may be used alone or in combination of two or more. In addition, the same insulating particles as those in the first insulating layer 21a described above may be dispersed in the fifth insulating layer 21e. The thickness of the fifth insulating layer 21e is not limited. For example, the fifth insulating layer 21e has a thickness of, for example, 5 μm or more and 25 μm or less.

As shown in FIG9 , in the wiring substrate 400 of the fourth embodiment, the lower conductor (equivalent to the core conductor layer 12a) may further include: a first through-hole conductor 121b having a cylindrical shape, and a second through-hole conductor 122b which is separated from the first through-hole conductor 121b and arranged on the inner side of the first through-hole conductor 121b when viewed from above. The first through-hole conductor 121b and the second through-hole conductor 122b are the same as the through-hole conductor 12b described above, and are located in the through-hole TH penetrating the core insulating layer 11 from top to bottom. The first through-hole conductor 121b and the second through-hole conductor 122b electrically connect the core conductor layer 12a and the additional conductor layer 22 located on the upper and lower surfaces of the core insulating layer 11. The first through-hole conductor 121b and the second through-hole conductor 122b are also formed by conductors composed of metal plating such as copper plating, similar to the through-hole conductor 12b mentioned above.

The first through-hole conductor 121b has a cylindrical shape and is formed on the inner wall surface of the through-hole TH. The second through-hole conductor 122b is located inside the first through-hole conductor 121b in a state surrounded by the first through-hole conductor 121b. The second through-hole conductor 122b has a columnar shape such as a cylinder. The first through-hole conductor 121b and the second through-hole conductor 122b have such a structure, so when, for example, the first through-hole conductor 121b is a grounding conductor and the second through-hole conductor 122b is a signal conductor, the first through-hole conductor 121b can be used to shield the second through-hole conductor 122b, and the signal transmission characteristics will be improved.

樹脂、聚醯亞胺樹脂、聚苯醚樹脂、液晶聚合物等。 A filling resin 11a is filled between the first through-hole conductor 121b and the second through-hole conductor 122b. The resin used as the filling resin 11a is not limited, and examples thereof include epoxy resin, dimaleimide-tris-butylene glycol, and the like.

Resin, polyimide resin, polyphenylene ether resin, liquid crystal polymer, etc.

The first through-hole conductor 121b is electrically connected to the first wiring conductor 23 and the third wiring conductor 25. At least one electrode 26 among the plurality of electrodes 26 is electrically connected to the second through-hole conductor 122b via the second wiring conductor 24. The electrode 26 is a portion of the additional conductor layer 22 exposed from the opening of the solder resist layer 30. Alternatively, at least two electrodes 26 among the plurality of electrodes 26 may be electrically connected via the second wiring conductor 24.

Below, an embodiment of the manufacturing method of the wiring substrate 400 of the fourth embodiment is described based on Figures 11 to 15. Figures 11 to 15 are explanatory diagrams used to illustrate the manufacturing steps of the wiring substrate of the fourth embodiment of the present disclosure.

First, prepare the core substrate 10. As shown in FIG11(A), prepare a laminate of a core insulating layer 11 and a core conductor 12. Then, form a through hole TH as shown in FIG11(B). The through hole TH is formed by general methods such as drilling and laser processing. Then, as shown in FIG11(C), electroless copper plating is deposited on the surface of the core conductor 12 and the inner wall surface of the through hole TH, and then, as shown in FIG11(D), electrolytic copper plating is deposited. The deposition of electrolytic copper plating does not fill the through hole TH.

Next, as shown in FIG. 11(E), the filling resin 11a is filled into the through hole TH, and as shown in FIG. 11(F), the filling resin 11a that exceeds the through hole TH is removed. The excess filling resin 11a is removed by, for example, grinding. When removing the filling resin 11a, the electroless copper plating and the electrolytic copper plating formed outside the inner wall surface of the through hole TH may also be removed, or may not be removed. In this way, the first through hole conductor 121b is formed on the inner wall surface of the through hole TH.

Next, as shown in FIG. 12(A), a second through hole TH2 is formed in the center of the filling resin 11a, penetrating the upper and lower surfaces in the thickness direction. Next, as shown in FIG. 12(B), electroless copper plating is deposited on the surface of the core conductor 12 and the inner wall surface of the second through hole TH2, and then, as shown in FIG. 12(C), electrolytic copper plating is deposited. The deposition of electrolytic copper plating is performed until the second through hole TH2 is filled. Next, as shown in FIG. 12(D), the electroless copper plating and electrolytic copper plating on the surface of the core conductor 12 are removed by, for example, grinding. In this way, the second through hole conductor 122b is formed in the second through hole TH2, and the core substrate 10 is completed.

Next, as shown in FIG. 12(E), a first insulating layer 21a is formed on the surface of the core substrate 10, and as shown in FIG. 12(F), a through hole V1 penetrating the first insulating layer 21a is formed at a desired position. The through hole V1 is formed by laser processing as described above.

Next, as shown in FIG13(A), electroless copper plating is deposited on the surface of the first insulating layer 21a and the inner wall surface of the through hole V1. This electroless copper plating is equivalent to the first base metal layer 22a. Next, as shown in FIG13(B), the portion where electrolytic copper plating is not to be formed (equivalent to the first electrolytic plating layer 22b) is coated with a resist R, and then as shown in FIG13(C), electrolytic copper plating is deposited to form the first electrolytic plating layer 22b. Next, as shown in FIG13(D), the resist R is removed.

Next, as shown in FIG. 14(A), the electroless copper plating (first base metal layer 22a) of the portion originally covered by the resist R after the resist R is removed is removed. The first base metal layer 22a is removed by, for example, etching. Next, as shown in FIG. 14(B), a second insulating layer 21b is formed covering the surface of the first insulating layer 21a and the first electrolytic plating layer 22b.

Next, as shown in FIG. 14(C), the first trench G1 and the second trench G2 are formed. The first trench G1 is formed to penetrate the lower conductor (core conductor layer 12a) located on the opposite side of the first upper surface f1 of the first insulating layer 21a. The second trench G2 is formed so that its bottom surface is located near the first upper surface f1 of the first insulating layer 21a. From the point of view of insulation reliability, the bottom surface of the second trench G2 is preferably separated from the lower conductor by, for example, 10 μm or more. The first trench G1 and the second trench G2 are formed by laser processing as described above. The first trench G1 and the second trench G2 are formed by, for example, changing the number of laser shots.

Next, as shown in FIG. 14(D), electroless copper plating is deposited on the surface of the second insulating layer 21b, the inner wall surface of the first trench G1, and the inner wall surface of the second trench G2. This electroless copper plating is equivalent to the second base metal layer 22c and the third base metal layer 22e. That is, the electroless copper plating located on the inner wall surface of the first trench G1 is equivalent to the second base metal layer 22c, and the electroless copper plating located on the inner wall surface of the second trench G2 is equivalent to the third base metal layer 22e.

Next, as shown in FIG. 15(A), electrolytic copper plating is deposited in such a manner as to fill the first trench G1 and the second trench G2. The electrolytic copper plating located in the first trench G1 is equivalent to the second electrolytic plating layer 22d, and the electrolytic copper plating located in the second trench G2 is equivalent to the third electrolytic plating layer 22f. Next, as shown in FIG. 15(B), the excess electrolytic copper plating and electroless plating beyond the first trench G1 and the second trench G2 are removed. The electrolytic copper plating and electroless plating can be removed by, for example, grinding. In this way, the first wiring conductor 23 is formed in the first trench G1, and the second wiring conductor 24 is formed in the second trench G2.

Repeat the steps from FIG. 12(E) to FIG. 15(B) as many times as required, and then form a solder resist layer having an opening on the surface where the electrode 26 is to be exposed, and the wiring board 400 of the fourth embodiment shown in FIG. 15(C) is obtained.

The wiring substrate 100 of the first embodiment, the wiring substrate 200 of the second embodiment, the wiring substrate 300 of the third embodiment, and the wiring substrate 400 of the fourth embodiment all have the build-up layer 20 disposed on the upper surface side of the core substrate 10. In the wiring substrate disclosed herein, the build-up layer 20 may also be located on the lower surface side of the core substrate 10. In the build-up layer 20 located on the lower surface side of the core substrate 10, the upper surfaces such as "the first upper surface f1" and "the second upper surface f2" are equivalent to the lower surface. However, if the wiring substrate is turned upside down 180 degrees, the upper surface side and the lower surface side of the core substrate 10 will be reversed, so they are recorded as upper surfaces such as "the first upper surface f1" and "the second upper surface f2". That is, in this specification, the surface of each layer of the build-up layer 20 that is farther from the core substrate 10 is referred to as the "upper surface".

Furthermore, the invention disclosed herein is not limited to the above-mentioned implementation forms, but various changes and improvements can be made within the scope of the invention disclosed herein as described in (1) and (10) below.

(1) The wiring substrate disclosed in the present invention comprises: a first insulating layer having a first upper surface; a second insulating layer located on the first upper surface and having a second upper surface; a first trench having a first inner surface recessed from the second upper surface toward the side of the first insulating layer; a second trench having a second inner surface recessed from the second upper surface toward the side of the first insulating layer; a first wiring conductor configured to extend from the first trench to the first upper surface and include a wide pattern having a width of 150 μm or more; and a second wiring conductor located in the second trench and including a narrow pattern having a width of 15 μm or less. The first wiring conductor includes: a first base metal layer located on the first upper surface; a first electrolytically plated layer located on the first base metal layer, and the side surface of the first inner surface is a part of the first inner surface; a second base metal layer located on the first inner surface and connected to the side surface of the first electrolytically plated layer; and a second electrolytically plated layer located on the second base metal layer and filled in the first trench. The second wiring conductor includes: a third base metal layer located on the second inner surface; and a third electrolytically plated layer located on the third base metal layer and filled in the second trench.

Regarding the implementation forms of the present disclosure, the implementation forms described in the following (2) to (9) and (11) to (16) are further disclosed.

(2) In the wiring substrate described in (1) above, the side surface of the first electrolytic coating layer has an arithmetic average roughness Ra of not less than 150nm and not more than 300nm.

(3) In the wiring substrate described in (1) or (2) above, at least one of the first inner surface and the second inner surface has an arithmetic mean roughness Ra of 50 nm to 100 nm.

(4) In the wiring substrate described in any one of (1) to (3) above, the depth of the second trench is smaller than the thickness of the second insulating layer.

(5) In the wiring substrate described in any one of (1) to (4) above, at least a portion of the surface of the first electrolytic coating layer is covered by the second insulating layer.

(6) In the wiring substrate described in any one of (1) to (5) above, there is further provided a lower conductor, which is located on the surface of the first insulating layer opposite to the first upper surface. The first wiring conductor located in the first groove is connected to the lower conductor.

(7) In the wiring substrate described in (6) above, there is further provided: a third insulating layer located on the second upper surface and having a third upper surface; a fourth insulating layer located on the third upper surface and having a fourth upper surface; a third trench having a third inner surface recessed from the fourth upper surface toward the third insulating layer side; and a third wiring conductor configured to extend from the third trench to the third upper surface and include a second width pattern having a width of 150 μm or more. The third wiring conductor located in the third trench is connected to the first wiring conductor. In a cross-sectional view in the thickness direction of the wiring substrate, a portion of the second wiring conductor is surrounded by the lower conductor, the first wiring conductor, and the third wiring conductor.

(8) In the wiring substrate described in (7) above, there is further provided a fifth insulating layer having a plurality of electrodes on the first upper surface side. The lower conductor further includes: a first cylindrical through-hole conductor, and a second through-hole conductor, the second through-hole conductor being separated from the first through-hole conductor and located inside the first through-hole conductor when viewed from above. The first through-hole conductor is electrically connected to the first wiring conductor and the third wiring conductor. At least one electrode among the plurality of electrodes is electrically connected to the second through-hole conductor via the second wiring conductor.

(9) In the wiring substrate described in (8) above, at least two electrodes among the plurality of electrodes are electrically connected via the second wiring conductor.

(10) The manufacturing method of the wiring substrate disclosed in the present invention comprises: a step of forming a first insulating layer having a first upper surface; a step of forming a wide pattern having a width of 150 μm or more and including a first base metal layer and a first electrolytically plated layer located on the first base metal layer on the first upper surface; a step of forming a second insulating layer covering the first upper surface and the wide pattern and having a second upper surface; a step of forming a first trench recessed from the second upper surface toward the side of the first insulating layer and having a first inner surface connected to the side surface of the wide pattern and a second trench having a second inner surface separated from the wide pattern; a step of forming a second base metal layer covering the first inner surface, a third base metal layer covering the second inner surface, and a second base metal layer recessed from the second upper surface toward the side surface of the first insulating layer; a fourth base metal layer continuous with the third base metal layer and covering the second upper surface, a second electrolytic coating layer located on the second base metal layer and filling the first trench, a third electrolytic coating layer located on the third base metal layer and filling the second trench, and a fourth base metal layer continuous with the second electrolytic coating layer and the third electrolytic coating layer and located on the fourth base metal layer and removing at least the fourth base metal layer and the fourth electrolytic coating layer located on the second upper surface, thereby forming a first wiring conductor configured to extend from the first trench to the first upper surface and include a wide pattern, and forming a second wiring conductor located in the second trench and including a narrow pattern with a width of less than 15μm.

(11) In the manufacturing method described in (10) above, in the step of forming the first wiring conductor, the side surface of the first electrolytic coating layer is subjected to a roughening treatment so that its roughness becomes an arithmetic average roughness Ra of not less than 150nm and not more than 300nm.

(12) In the manufacturing method described in (10) or (11) above, in the step of forming the first groove and the second groove, a groove forming process is performed so that the first inner surface and the second inner surface, except for the side surface of the wide pattern, have an arithmetic average roughness Ra of 50nm to 100nm.

(13) In the manufacturing method described in (10) to (12) above, in the step of forming the first trench and the second trench, the depth of the second trench is formed to be smaller than the thickness of the second insulating layer.

(14) In the manufacturing method described in (10) to (13) above, in the step of forming the first wiring conductor and the second wiring conductor, at least the fourth base metal layer and the fourth electrolytic coating layer located on the second insulating layer are removed in such a manner that at least a portion of the surface of the first wiring conductor is not exposed.

(15) In the manufacturing method described in (10) to (14) above, the step of forming a lower conductive layer on the surface of the first insulating layer opposite to the first surface is further included. The first trench is formed to a depth reaching the lower conductive layer.

(16) The manufacturing method described in (15) further comprises: forming a third insulating layer having a third upper surface on the second upper surface; forming a second wide pattern having a width of 150 μm or more on the third upper surface; forming a fourth insulating layer having a fourth upper surface covering the third upper surface and the second wide pattern; and forming a second insulating layer having a third upper surface on both sides of the second wiring conductor 24. The step of forming: a third groove G3 that is recessed from the fourth upper surface toward the third insulating layer 21c side, connected to the side of the second wide pattern WP2 and reaches the first wiring conductor 23; and the step of forming: a third wiring conductor that is configured to extend from the third groove to the third upper surface, includes the second wide pattern and is partially connected to the first wiring conductor on both sides of the second wiring conductor 24.

10: Core substrate

11: Core insulation layer

12: Core conductor

12a: Core conductor layer

12b: Through-hole conductor

20: Additional floor

21: Add insulation layer

21a: First insulating layer

21b: Second insulating layer

22: Add conductor layer

22a: First base metal layer

22b: First electrolytic coating

22c: Second base metal layer

22d: Second electrolytic coating

22e: Third base metal layer

22f: The third electrolytic coating

23: First wiring conductor

24: Second wiring conductor

30: Solder resist layer

100:Wiring board

G1: First groove

G2: Second groove

NP: Narrow pattern

WP: Wide Image

Claims (16)

A wiring substrate comprises: a first insulating layer having a first upper surface; a second insulating layer located on the first upper surface and having a second upper surface; a first base metal layer located on the first upper surface; a first electrolytically plated layer located on the first base metal layer; a first trench recessed from the second upper surface along the side surface of the first electrolytically plated layer toward the side surface of the first insulating layer and having a first inner surface, wherein the first inner surface includes the side surface of the first electrolytically plated layer as a part of the inner surface; a second trench having a second inner surface recessed from the second upper surface toward the side surface of the first insulating layer; a first wiring conductor arranged to extend from the first trench to the first insulating layer; The first wiring conductor includes a second base metal layer located on the first inner surface and connected to the side surface of the first electrolytically plated layer; and a second electrolytically plated layer located on the second base metal layer and filled in the first trench; the second wiring conductor includes a third base metal layer located on the second inner surface; and a third electrolytically plated layer located on the third base metal layer and filled in the second trench. The wiring substrate as described in claim 1, wherein the side surface of the first electrolytic coating layer has an arithmetic average roughness Ra of not less than 150nm and not more than 300nm. A wiring substrate as described in claim 1 or 2, wherein at least one of the first inner surface and the second inner surface has an arithmetic average roughness Ra of not less than 50nm and not more than 100nm. A wiring substrate as described in claim 1 or 2, wherein the depth of the second trench is smaller than the thickness of the second insulating layer. A wiring substrate as described in claim 1 or 2, wherein at least a portion of the surface of the first electrolytic coating layer is covered by the second insulating layer. The wiring substrate as described in claim 1 or 2 further comprises a lower conductor, which is located on the surface of the first insulating layer opposite to the first upper surface; the first wiring conductor located in the first trench is connected to the lower conductor. The wiring substrate as described in claim 6 is further provided with: a third insulating layer located on the second upper surface and having a third upper surface; a fourth insulating layer located on the third upper surface and having a fourth upper surface; a third trench having a third inner surface recessed from the fourth upper surface toward the third insulating layer side; and a third wiring conductor configured to extend from the third trench to the third upper surface and include a second width pattern having a width of 150 μm or more; the third wiring conductor located in the third trench is connected to the first wiring conductor; In a cross-sectional view in the thickness direction of the wiring substrate, a portion of the second wiring conductor is surrounded by the lower conductor, the first wiring conductor, and the third wiring conductor. The wiring substrate as described in claim 7 is further provided with a fifth insulating layer, the fifth insulating layer having a plurality of electrodes; the lower conductor further comprises: a first cylindrical through-hole conductor, and a second through-hole conductor, the second through-hole conductor being separated from the first through-hole conductor and located inside the first through-hole conductor when viewed from above; the first through-hole conductor is electrically connected to the first wiring conductor and the third wiring conductor; at least one electrode among the plurality of electrodes is electrically connected to the second through-hole conductor via the second wiring conductor. A wiring substrate as described in claim 8, wherein at least two of the plurality of electrodes are electrically connected via the second wiring conductor. A method for manufacturing a wiring board includes: forming a first insulating layer having a first upper surface; forming a wide pattern having a width of 150 μm or more and including a first base metal layer and a first electrolytically plated layer on the first base metal layer on the first upper surface; forming a second insulating layer covering the first upper surface and the wide pattern and having a second upper surface; forming a second insulating layer from the first upper surface to the second upper surface; The second upper surface is recessed along the side of the first electrolytic coating layer toward the side of the first insulating layer and has a first groove having a first inner surface including the side of the first electrolytic coating layer as a part of the inner surface, and a second groove having a second inner surface separated from the side of the first electrolytic coating layer; forming a second base metal layer covering the first inner surface, a third base metal layer covering the second inner surface, a fourth base metal layer continuous with the second base metal layer and the third base metal layer and covering the second upper surface, a second electrolytic coating layer located on the second base metal layer and filling the thickness of the first trench, a third electrolytic coating layer located on the third base metal layer and filling the thickness of the second trench, and a third electrolytic coating layer continuous with the second electrolytic coating layer and the third electrolytic coating layer and located on the second upper surface; The fourth electrolytic coating layer is formed on the fourth base metal layer; and at least the fourth base metal layer and the fourth electrolytic coating layer located on the second upper surface are removed to form a first wiring conductor extending from the first trench to the first upper surface and including the wide pattern, and a second wiring conductor located in the second trench and including a narrow pattern with a width of less than 15μm is formed. A method for manufacturing a wiring board as described in claim 10, wherein, in the step of forming the first wiring conductor, the side surface of the first electrolytic coating is subjected to a roughening treatment to obtain an arithmetic average roughness Ra of not less than 150nm and not more than 300nm. A method for manufacturing a wiring board as described in claim 10 or 11, wherein in the step of forming the first trench and the second trench, a trench forming process is performed so that the first inner surface and the second inner surface except the side surface of the wide pattern have an arithmetic average roughness Ra of 50 nm or more and 100 nm or less. A method for manufacturing a wiring board as described in claim 10 or 11, wherein, in the step of forming the first trench and the second trench, the depth of the second trench is formed to be smaller than the thickness of the second insulating layer. A method for manufacturing a wiring board as described in claim 10 or 11, wherein, in the step of forming the first wiring conductor and the second wiring conductor, at least the fourth base metal layer and the fourth electrolytic coating layer located on the second insulating layer are removed in such a manner that at least a portion of the surface of the first wiring conductor is not exposed. The manufacturing method of the wiring board as described in claim 10 or 11 further includes the step of forming a lower conductive layer on the surface of the first insulating layer opposite to the first upper surface, and forming the first trench to a depth reaching the lower conductive layer. The method for manufacturing a wiring substrate as described in claim 15 further comprises: forming a third insulating layer having a third upper surface on the second upper surface; forming a second wide pattern having a width of 150 μm or more on the third upper surface; forming a fourth insulating layer having a fourth upper surface and covering the third upper surface and the second wide pattern; forming a second insulating layer on both sides of the second wiring conductor; The step of forming a third trench that is recessed from the fourth upper surface toward the third insulating layer side, is in contact with the side of the second wide pattern and reaches the first wiring conductor; and the step of forming a third wiring conductor that is configured to extend from the third trench to the third upper surface, includes the second wide pattern, and is partially in contact with the first wiring conductor on both sides of the second wiring conductor.

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