TWI888055B - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor structure includes a substrate, a gate structure, a source/drain region, a first oxide dielectric layer, a nitride dielectric layer, a second oxide dielectric layer, and a contact. The gate structure is disposed on the substrate. The source/drain region is disposed in the substrate and adjacent to the gate structure. The first oxide dielectric layer covers the gate structure and the source/drain region. The nitride dielectric layer covers the first oxide dielectric layer. The second oxide dielectric layer covers the nitride dielectric layer. The contact penetrates through the first oxide dielectric layer, the nitride dielectric layer, and the second oxide dielectric layer to electrically connect the source/drain region, in which the nitride dielectric layer includes a nitride spacer interposed between the first oxide dielectric layer and the contact.

Description

Semiconductor structure and method for manufacturing the same

The present disclosure relates to a semiconductor structure and a method for manufacturing the same, and in particular to a semiconductor structure including a self-aligned contact (SAC) and a method for manufacturing the same.

The integrated circuit industry has grown rapidly, developing multiple generations of integrated circuits, each with smaller and more complex circuits than the previous generation. During the development process, the geometric size of integrated circuits has gradually become smaller. As the geometric size of integrated circuits becomes smaller, the spacing between gates also decreases, so the distance between the contact structure above the source/drain and the gate also decreases, thereby increasing the probability of leakage current generation caused by a short circuit between the contact structure and the gate. In view of the above, it is necessary to provide a new semiconductor structure and a manufacturing method thereof to solve the above problems.

The present disclosure provides a semiconductor structure, which includes a substrate, a gate structure, a source/drain region, a first oxide dielectric layer, a nitride dielectric layer, a second oxide dielectric layer and a contact. The gate structure is disposed on the substrate. The source/drain region is disposed in the substrate and adjacent to the gate structure. The first oxide dielectric layer covers the gate structure and the source/drain region. The nitride dielectric layer covers the first oxide dielectric layer. The second oxide dielectric layer covers the nitride dielectric layer. The contact penetrates the first oxide dielectric layer, the nitride dielectric layer and the second oxide dielectric layer to electrically connect the source/drain region, wherein the nitride dielectric layer includes a nitride spacer sandwiched between the first oxide dielectric layer and the contact.

The present disclosure provides a method for manufacturing a semiconductor structure, which includes the following operations. A gate structure is formed on a substrate. A source/drain region is formed in the substrate, wherein the source/drain region is adjacent to the gate structure. A first oxide dielectric layer, a nitride dielectric layer, and a second oxide dielectric layer are sequentially formed to cover the gate structure and the source/drain region. The second oxide dielectric layer is etched to form a first hole, wherein the nitride dielectric layer is exposed from the first hole. The nitride dielectric layer exposed from the first hole is partially etched to form a second hole, wherein a portion of the nitride dielectric layer remains on the first oxide dielectric layer to form a nitride spacer, and the first oxide dielectric layer is exposed from the bottom of the second hole. Etching the first oxide dielectric layer to form a third hole, wherein the source/drain region is exposed from the third hole. Forming a contact in the third hole.

100:Methods

110, 120, 130, 140, 150, 160, 170: Operation

210:Substrate

220: Gate structure

222: Gate insulation layer

224: Gate

226: Silicide layer

230: Source/drain region

310: first oxide dielectric layer

320: Nitride dielectric layer

330: Second oxide dielectric layer

700:Semiconductor structure

710: Contact plug

720: Barrier layer

C: Contacts

h: opening

H1: First hole

H2: Second hole

H3: The third hole

PR: Photoresist layer

S1: Concave

S2: convex surface

S2’: convex surface

S3: Convex surface

SP: Nitride spacer

SW1: First side wall

SW2: Second side wall

By reading the detailed description of the following implementation method and referring to the attached drawings, you can more fully understand the content of this disclosure.

FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure according to various embodiments of the present disclosure.

Figures 2 to 7 are schematic cross-sectional views of intermediate stages of manufacturing semiconductor structures according to various implementations of the present disclosure.

Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numbers are used in the drawings and description to refer to the same or similar parts.

The following multiple implementations are described and disclosed in detail with the attached figures. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details are not intended to limit the content of this disclosure. In other words, in some implementations of the content of this disclosure, these practical details are not necessary. In addition, to simplify the drawings, some known structures and components will be shown in schematic form in the drawings.

Although a series of operations or steps are used below to illustrate the methods disclosed herein, the order in which these operations or steps are shown should not be interpreted as a limitation of the present disclosure. For example, certain operations or steps may be performed in a different order and/or simultaneously with other steps. In addition, not all operations, steps, and/or features shown must be performed to implement the present disclosure. In addition, each operation or step described herein may include a number of sub-steps or actions.

Various integrated circuits are developing in the direction of downsizing. Integrated circuits may include, for example, metal oxide semiconductor field effect transistors (MOSFETs). As the size decreases, the distance between gates in the integrated circuit also decreases, so the distance between the contact above the source/drain and the gate also decreases. Therefore, the overlay budget of the contact and the gate decreases. In detail, when the overlay budget is small, if the position shift occurs during the manufacturing process of the contact, a short circuit is likely to occur between the contact and the gate, resulting in leakage current generation, thereby affecting the performance of the integrated circuit.

To solve the above problems, the present disclosure provides a semiconductor structure and a method for manufacturing the same. In the semiconductor structure of the present disclosure, by setting a nitride spacer between a gate and a contact in a stack of multiple interlayer dielectrics, the size of the contact adjacent to the gate is limited, and a certain distance is provided between the gate and the contact, thereby reducing the probability of a short circuit between the contact and the gate. Therefore, even if the size of the semiconductor structure is reduced and the overlap budget between the contact and the gate is 0 or very small, the semiconductor structure of the present disclosure can be free from the overlap budget and still have good performance. Furthermore, the manufacturing method disclosed herein can form contact openings by etching different interlayer dielectric layers in the stack by dry etching process and/or wet etching process. If the different interlayer dielectric layers in the stack are etched by dry etching process, the above dry etching process can be performed in the same reaction chamber without changing the reaction chamber. Therefore, the manufacturing method disclosed herein has a simple process flow and can reduce manufacturing costs. The semiconductor structure disclosed herein and its manufacturing method can be applied to the technical field of high voltage power MOSFET, for example.

The present disclosure provides a method for manufacturing a semiconductor structure, see FIGS. 1 to 7. FIG. 1 is a flow chart of a method 100 for manufacturing a semiconductor structure according to various embodiments of the present disclosure. The manufacturing method 100 includes operations 110, 120, 130, 140, 150, 160, and 170. FIGS. 2 to 7 are cross-sectional schematic diagrams of intermediate stages of manufacturing a semiconductor structure 700 according to various embodiments of the present disclosure. The above operations 110 to 170 will be described below with reference to FIGS. 2 to 7.

In operation 110, as shown in FIG. 2 , a gate structure 220 is formed on a substrate 210. The gate structure 220 includes a gate insulation layer 222, a gate 224, and a silicide layer 226. The gate insulation layer 222 is disposed on the substrate 210, the gate 224 is disposed on the gate insulation layer 222, and the silicide layer 226 is disposed on the gate 224. In some embodiments, the substrate 210 includes any suitable semiconductor material and/or semiconductor material for forming a semiconductor structure. The semiconductor material includes, for example, one or more materials, such as crystalline silicon, silicon oxide, strained silicon, germanium silicon, doped or undoped polysilicon, doped or undoped silicon wafer, germanium, gallium arsenide, other suitable semiconductor materials or combinations thereof. In some embodiments, the substrate 210 is a silicon substrate. In some embodiments, the material of the gate insulating layer 222 includes silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, zirconium oxide, titanium oxide, tantalum oxide, other suitable high-k dielectric materials or combinations thereof. In some embodiments, the material of the gate 224 includes polysilicon, tungsten nitride, tungsten, copper, aluminum, gold, silver or a combination thereof. In some embodiments, the material of the silicide layer 226 includes tungsten disilicide (WSi ₂ ). In other embodiments, the silicide layer 226 in the gate structure 220 may be omitted.

In operation 120, as shown in FIG. 2, a source/drain region 230 is formed in the substrate 210, wherein the source/drain region 230 is adjacent to the gate structure 220. The source/drain region 230 can be formed by an implantation process or other suitable process. In some embodiments, the source/drain region 230 is a P-type doped region, including impurities such as boron, aluminum, gallium, or indium. In some embodiments, the source/drain region 230 is an N-type doped region, including impurities such as phosphorus, antimony, or arsenic. FIG. 2 shows a plurality of source/drain regions 230. The operations shown in the subsequent FIG. 3 to FIG. 7 can be referred to to form contacts electrically connected to each source/drain region 230. In order to simplify the diagram, FIG. 3 to FIG. 7 only show the formation process of one contact, but the content of the present disclosure is not limited to this.

In operation 130, as shown in FIG. 3, a first oxide dielectric layer 310, a nitride dielectric layer 320, and a second oxide dielectric layer 330 are sequentially formed to cover the gate structure 220 and the source/drain region 230, and a photoresist layer PR having an opening h is formed on the second oxide dielectric layer 330, wherein the first oxide dielectric layer 310, the nitride dielectric layer 320, and the second oxide dielectric layer 330 are all interlayer dielectric layers (ILD layers). In some embodiments, the first oxide dielectric layer 310 conformally covers the gate structure 220 and the source/drain region 230, the nitride dielectric layer 320 conformally covers the first oxide dielectric layer 310, and the second oxide dielectric layer 330 conformally covers the nitride dielectric layer 320. In some embodiments, the material of the first oxide dielectric layer 310 and the second oxide dielectric layer 330 includes silicon oxide, such as silicon dioxide. In some embodiments, the material of the nitride dielectric layer 320 includes silicon nitride. In some embodiments, the first oxide dielectric layer 310 and the second oxide dielectric layer 330 are silicon dioxide layers, and the nitride dielectric layer 320 is a silicon nitride layer. In some embodiments, the first oxide dielectric layer 310, the nitride dielectric layer 320, and the second oxide dielectric layer 330 may be formed by chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or flowable CVD. In some embodiments, the thickness of the nitride dielectric layer 320 is less than the thickness of the first oxide dielectric layer 310. In some embodiments, the thickness of the nitride dielectric layer 320 is less than the thickness of the second oxide dielectric layer 330.

In operation 140, as shown in FIG. 4, the second oxide dielectric layer 330 is etched to form a first hole H1, wherein the nitride dielectric layer 320 is exposed from the first hole H1. In more detail, the photoresist layer PR having an opening h is used as an etching mask for etching the second oxide dielectric layer 330. The second oxide dielectric layer 330 can be etched by a wet etching process or a dry etching process. In some embodiments, etching the second oxide dielectric layer 330 to form the first hole H1 is performed by a wet etching process. As shown in FIG. 4, in the cross-sectional view of the first hole H1 formed by the wet etching process, the hole wall of the first hole H1 is a concave surface S1. Compared to the dry etching process, the wet etching process can form a first hole H1 with a larger aperture (e.g., larger than the minimum aperture of the opening h), which is conducive to accommodating the contact formed subsequently. For example, a hydrofluoric acid (HF) etchant can be used to perform the wet etching process. In other embodiments, etching the second oxide dielectric layer 330 to form the first hole H1 is performed by a dry etching process. In the cross-sectional view of the first hole H1 formed by the dry etching process, the hole wall of the first hole H1 is substantially flat (not shown in FIG. 5). For example, the dry etching process is a plasma etching process, and the plasma of the plasma etching process is generated by fluorocarbon gas, oxygen (O ₂ ) and argon (Ar). The fluorocarbon gas includes, for example, CF ₄ , CHF ₃ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₄ F ₈ , C ₅ F ₈ or a combination thereof. In some embodiments, the fluorocarbon gas includes CF ₄ and CHF ₃ .

In operation 150, as shown in FIG. 5, the nitride dielectric layer 320 exposed from the first hole H1 is partially etched to form a second hole H2, wherein a portion of the nitride dielectric layer 320 remains on the first oxide dielectric layer 310 to form a nitride spacer SP, and the first oxide dielectric layer 310 is exposed from the bottom of the second hole H2. The nitride spacer SP can also be called a self-aligned nitride spacer. In some embodiments, the nitride spacer SP is a silicon nitride spacer. In some embodiments, the partial etching of the nitride dielectric layer 320 exposed from the first hole H1 to form the second hole H2 is performed by a dry etching process, as shown in FIG6 , in the cross-sectional view of the hole of the nitride dielectric layer 320, the hole wall of the hole is substantially planar. For example, the dry etching process is a plasma etching process, and the plasma of the plasma etching process is generated by nitrogen-containing gas, oxygen gas and argon gas. For example, the plasma of the plasma etching process is generated by nitrogen trifluoride (NF ₃ ), nitrogen (N ₂ ), oxygen and argon. When the first oxide dielectric layer 310 is a silicon dioxide layer and the nitride dielectric layer 320 is a silicon nitride layer, the etching selectivity of the silicon nitride layer to the first oxide dielectric layer 310 is about 40.

Please continue to refer to FIG. 5. In some embodiments, in the cross-sectional view of the nitride spacer SP, the nitride spacer SP has a width that increases gradually from top to bottom. The nitride spacer SP has a convex surface S2, and the convex surface S2 faces the second hole H2. As shown in FIG. 5, the first oxide dielectric layer 310 covers the first sidewall SW1 of the gate structure 220, and the nitride spacer SP covers the second sidewall SW2 of the first oxide dielectric layer 310. In FIG. 5, after the nitride dielectric layer 320 exposed from the first hole H1 is partially etched, the top edge of the nitride spacer SP is substantially aligned with the top surface of the first oxide dielectric layer 310. In some embodiments, the top edge of the convex surface S2 of the nitride spacer SP is substantially aligned with the top surface of the first oxide dielectric layer 310. However, in other embodiments, after the nitride dielectric layer 320 exposed from the first hole H1 is partially etched, the nitride spacer SP has a convex surface S2' as shown by the dotted line, so the top edge of the nitride spacer SP is lower than the top surface of the first oxide dielectric layer 310. In some embodiments, the top edge of the convex surface S2' of the nitride spacer SP is lower than the top surface of the first oxide dielectric layer 310. Therefore, a portion of the second sidewall SW2 of the first oxide dielectric layer 310 is not covered by the nitride spacer SP.

In operation 160, as shown in FIG. 6, the first oxide dielectric layer 310 is etched to form a third hole H3, wherein the source/drain region 230 is exposed from the third hole H3. The third hole H3 generally has a hole shape that is wide at the top and narrow at the bottom, so that it is convenient for subsequent contacts to be filled into the third hole H3. During the etching process of the first oxide dielectric layer 310, the etchant etches the first oxide dielectric layer 310 next to the nitride spacer SP along the edge of the nitride spacer SP, thereby limiting the size of the hole formed in the first oxide dielectric layer 310. The nitride spacer SP can serve as a protective layer when etching the first oxide dielectric layer 310. Therefore, the contact to be formed in the third hole H3 will not be short-circuited with the gate 224 due to process deviation, thereby avoiding the performance of the overall structure from being affected. In some embodiments, etching the first oxide dielectric layer 310 to form the third hole H3 is performed by a dry etching process. For example, the dry etching process is a plasma etching process, _and the plasma of _the plasma etching process is generated by fluorocarbon gas, oxygen _and argon. The fluorocarbon gas includes, for example, _CF4 , _CHF3 , _C2F6 , _C3F8 , _C4F6 , _C4F8 , _C5F8 or _a combination thereof. In some embodiments, the fluorocarbon gas includes _CF4 and _{CHF3 .}

In operation 170, as shown in FIG. 7 , a contact C is formed in the third hole H3 to form a semiconductor structure 700, wherein the contact C includes a contact plug 710 and a barrier layer 720. More specifically, the barrier layer 720 is formed to cover the hole wall of the third hole H3, and the contact plug 710 is formed on the barrier layer 720. The barrier layer 720 can conformally cover the hole wall of the third hole H3. As shown in FIG. 7 , the barrier layer 720 is disposed between the second oxide dielectric layer 330, the nitride dielectric layer 320, the first oxide dielectric layer 310, and the source/drain region 230 and the contact plug 710. It is worth noting that the barrier layer 720 is disposed between the nitride spacer SP of the nitride dielectric layer 320 and the contact plug 710. The nitride spacer SP can directly contact the barrier layer 720 of the contact C. In some embodiments, the material of the contact plug 710 includes titanium. In some embodiments, the material of the barrier layer 720 includes titanium nitride.

Please continue to refer to FIG. 7. The semiconductor structure 700 includes a substrate 210, a gate structure 220, a source/drain region 230, a first oxide dielectric layer 310, a nitride dielectric layer 320, a second oxide dielectric layer 330, and a contact C. The gate structure 220 is disposed on the substrate 210. The source/drain region 230 is disposed in the substrate 210 and adjacent to the gate structure 220. The first oxide dielectric layer 310 covers the gate structure 220 and the source/drain region 230. The nitride dielectric layer 320 covers the first oxide dielectric layer 310. The second oxide dielectric layer 330 covers the nitride dielectric layer 320. The contact C penetrates the first oxide dielectric layer 310, the nitride dielectric layer 320 and the second oxide dielectric layer 330 to electrically connect the source/drain region 230, wherein the nitride dielectric layer 320 includes a nitride spacer SP sandwiched between the first oxide dielectric layer 310 and the contact C. The nitride spacer SP can directly contact the contact C and the first oxide dielectric layer 310. The contact C is separated from the gate 224 by the first oxide dielectric layer 310 and the nitride spacer SP. As mentioned above, when etching the first oxide dielectric layer 310, the nitride spacer SP will limit the size of the holes formed in the first oxide dielectric layer 310. It is worth noting that the width of the first oxide dielectric layer 310 located under the nitride spacer SP is determined by the width of the nitride spacer SP, and therefore, the size of the contact C is also determined by the width of the nitride spacer SP. In detail, the nitride spacer SP can make the first oxide dielectric layer 310 located next to the gate structure 220 have a certain width to separate the gate 224 and the contact C, so that the contact C is not easy to short-circuit with the gate 224.

Please continue to refer to FIG. 7 , the nitride spacer SP has a convex surface S2, and the convex surface S2 faces the contact C. The convex surface S2 can directly contact the contact C. In the etching operation of FIG. 5 , if more nitride spacers SP are removed, the nitride spacers SP have a convex surface S2’, and the convex surface S2’ faces the contact C. The convex surface S2’ can directly contact the contact C. In addition, a portion of the contact C on the nitride spacer SP having the convex surface S2’ can directly contact the first oxide dielectric layer 310 (not shown in FIG. 7 ). Please continue to refer to FIG. 7. In the etching operation of FIG. 4, a first hole H1 is formed in the second oxide dielectric layer 330 by a wet etching process. Therefore, the hole wall of the first hole H1 is a concave surface S1. Therefore, as shown in FIG. 7, the contact C has a convex surface S3, and the convex surface S3 faces the second oxide dielectric layer 330. The convex surface S3 can directly contact the second oxide dielectric layer 330.

Please continue to refer to Figure 7. The semiconductor structure 700 can be applied to the technical field of high-voltage power MOSFET, and no spacer is set between the gate structure 220 and the first oxide dielectric layer 310.

In summary, the present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a nitride spacer disposed between a gate and a contact, so that a short circuit is not likely to occur between the gate and the contact. If the distance between a gate and an adjacent gate in the semiconductor structure is small, so that the overlap budget is 0 or very small, the semiconductor structure can still have good performance. In addition, the manufacturing method of the present disclosure has a simple process flow, which can reduce manufacturing costs.

Although the present disclosure has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments included herein.

It is obvious to a person of ordinary skill in the art that various modifications and variations may be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations of the present disclosure that fall within the scope of the attached patent applications.

210:Substrate

220: Gate structure

222: Gate insulation layer

224: Gate

226: Silicide layer

230: Source/drain region

310: first oxide dielectric layer

320: Nitride dielectric layer

330: Second oxide dielectric layer

700:Semiconductor structure

710: Contact plug

720: Barrier layer

C: Contacts

H3: The third hole

S1: Concave

S2: convex surface

S2’: convex surface

S3: Convex surface

SP: Nitride spacer

SW1: First side wall

SW2: Second side wall

Claims (9)

A semiconductor structure includes: a substrate; a gate structure disposed on the substrate; a source/drain region disposed in the substrate and adjacent to the gate structure; a first oxide dielectric layer covering the gate structure and the source/drain region; a nitride dielectric layer covering the first oxide dielectric layer; a second oxide dielectric layer covering the nitride dielectric layer; and A contact penetrates the first oxide dielectric layer, the nitride dielectric layer and the second oxide dielectric layer to electrically connect the source/drain region, wherein the nitride dielectric layer includes a nitride spacer sandwiched between the first oxide dielectric layer and the contact, wherein the first oxide dielectric layer covers a first sidewall of the gate structure, and the nitride spacer covers a second sidewall of the first oxide dielectric layer. A semiconductor structure as described in claim 1, wherein the nitride spacer has a convex surface facing the contact. A semiconductor structure as described in claim 1, wherein a top edge of the nitride spacer is lower than a top surface of the first oxide dielectric layer. A semiconductor structure as described in claim 1, wherein in a cross-sectional view of the nitride spacer, the nitride spacer has a width that gradually increases from top to bottom. A method for manufacturing a semiconductor structure, comprising: forming a gate structure on a substrate; forming a source/drain region in the substrate, wherein the source/drain region is adjacent to the gate structure; sequentially forming a first oxide dielectric layer, a nitride dielectric layer and a second oxide dielectric layer to cover the gate structure and the source/drain region; etching the second oxide dielectric layer to form a first hole, wherein the nitride dielectric layer is exposed from the first hole; Partially etching the nitride dielectric layer exposed from the first hole to form a second hole, wherein a portion of the nitride dielectric layer remains on the first oxide dielectric layer to form a nitride spacer, and the first oxide dielectric layer is exposed from a bottom of the second hole; Etching the first oxide dielectric layer to form a third hole, wherein the source/drain region is exposed from the third hole; and Forming a contact in the third hole. The method of claim 5, wherein partially etching the nitride dielectric layer exposed from the first hole to form the second hole is performed by a dry etching process. The method as described in claim 6, wherein the dry etching process is a plasma etching process, and a plasma of the plasma etching process is generated by nitrogen trifluoride, nitrogen, oxygen and argon. The method of claim 5, wherein etching the second oxide dielectric layer to form the first hole is performed by a wet etching process. The method of claim 5, wherein etching the first oxide dielectric layer to form the third hole is performed by a dry etching process.

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