TWI886986B - Potential conversion circuit, source drive circuit, display and information processing device - Google Patents

Abstract

A potential conversion circuit has: a bit potential conversion module, a pair of low-side inverter circuits and a pair of high-side latched active loads to perform a potential conversion operation on a positive input signal and a negative input signal, a positive output node and a negative output node are provided between the pair of low-side inverter circuits and the pair of high-side latched active loads, and the potential conversion circuit has a characteristic The invention is characterized in that: in the potential conversion operation, a first high-side enabling signal is used to control a pair of first switches to temporarily disconnect the current path between the pair of low-side inverter circuits and the pair of high-side latched active loads, and a second high-side enabling signal is used to control a pair of second switches so that the potentials of the positive output node and the negative output node are precharged to a positive supply voltage; a source A material change detection module is used to perform a comparison operation on the content of a current row period and a previous row period of a display data to generate a comparison result, and generate a first enable output signal and a second enable output signal according to the comparison result, wherein when the comparison result is inconsistent, the first enable output signal and the second enable output signal are both in an active state, and when the comparison result is consistent, the first enable output signal and the second enable output signal are both in an inactive state; and a boost circuit is coupled to the bit potential conversion module and the bit potential conversion module, and is used to correspondingly boost the first enable output signal and the second enable output signal into the first high-side enable signal and the second high-side enable signal.

Description

Potential conversion circuit, source drive circuit, display and information processing device

The present invention relates to a display driver circuit, and in particular to a potential conversion circuit of a source driver.

With the evolution of market demand, the application products of displays have expanded from TVs, laptops, mobile phones, and watches to VR (virtual reality) glasses and AR (augmented reality) glasses. In the high-resolution display applications of VR (virtual reality) glasses and AR (augmented reality) glasses, due to the limited area of the circuit board, the source driver circuit of the display cannot rely on multiple driver chips connected in series, but must provide a large number of output channels in a single driver chip to meet the high-resolution display requirements.

Please refer to FIG1, which is a block diagram of an output channel of a conventional active-source driver chip. As shown in FIG1, the output channel has a shift register 10, a potential conversion circuit 20, a digital-to-analog conversion circuit 30, and a buffer amplifier 40, wherein the shift register 10 is used to store a display data DIN input in a serial manner and output the display data DIN in a parallel format; the potential conversion circuit 20 is used to increase the logic level of the display data DIN to output a corresponding digital signal; the digital-to-analog conversion circuit 30 is used to generate an analog voltage according to the corresponding digital signal; and the buffer amplifier 40 is used to generate an output voltage VOUT according to the analog voltage to drive a display.

Please refer to FIG. 2, which shows a circuit diagram of each bit potential conversion circuit in the potential conversion circuit 20 of FIG. 1. As shown in FIG. 2, the bit potential conversion circuit is coupled between a high-side positive supply voltage AVDD and a reference ground, and has a pair of active loads (composed of a PMOS transistor 21a and a PMOS transistor 21b), a latch circuit (composed of a PMOS transistor 22a and a PMOS transistor 22b), a pair of cascade loads (composed of an NMOS transistor 23a and an NMOS transistor 23b), and a pair of inverters (composed of an NMOS transistor 24a and an NMOS transistor 24b), wherein the PMOS transistors are connected to the PMOS transistors 21a and 21b, respectively. The gate of the transistor 21a and the gate of the PMOS transistor 21b are commonly coupled to a first DC voltage VBP, the gate of the NMOS transistor 23a and the gate of the NMOS transistor 23b are commonly coupled to a second DC voltage VBN, the gate of the NMOS transistor 24a is coupled to a positive input signal VIP, the gate of the NMOS transistor 24b is coupled to a negative input signal VIN, and the source of the NMOS transistor 24a and the source of the NMOS transistor 24b are coupled to a ground node GND, and the ground node GND is then connected to the reference ground via a conductive path. During operation, when the positive input signal VIP is logic 1, the potential of node QB will be pulled down, causing PMOS transistor 22b to turn on and pull the potential of node Q up; when the negative input signal VIN is logic 1, the potential of node Q will be pulled down, causing PMOS transistor 22a to turn on and pull the potential of node QB up.

In order to improve the response speed of the bit potential conversion circuit, the art has added a precharge switch design between the node Q and the positive supply voltage VDD and between the node QB and the positive supply voltage VDD, so as to perform a precharge operation before the positive input signal VIP and the negative input signal VIN arrive to precharge the node Q and the node QB to a high potential.

However, the above pre-charging operation is effective only when the display data DIN of the previous and next rows are different. When the display data DIN of the previous and next rows are the same, the above pre-charging operation is a redundant operation and wastes power.

In order to solve the above problems, this field urgently needs a novel potential conversion circuit.

The main purpose of the present invention is to provide a potential conversion circuit that can determine whether to perform a pre-charge operation based on the comparison results of the pixel display data of the previous and next rows during a potential conversion operation, thereby improving the response speed of the potential conversion circuit and avoiding unnecessary dynamic power consumption.

Another purpose of the present invention is to provide a source drive circuit that can improve the response speed of its output channel and eliminate unnecessary dynamic power consumption through the aforementioned potential conversion circuit.

Another purpose of the present invention is to provide a display device that can improve the display effect of dynamic images and avoid unnecessary dynamic power consumption through the aforementioned source drive circuit.

Another purpose of the present invention is to provide an information processing device that can improve the display effect of dynamic images and avoid unnecessary dynamic power consumption through the aforementioned display.

To achieve the above object, a potential conversion circuit is proposed, which has: a bit potential conversion module, having a pair of low-side inverter circuits and a pair of high-side latched active loads to perform a potential conversion operation on a positive input signal and a negative input signal, a positive output node and a negative output node between the pair of low-side inverter circuits and the pair of high-side latched active loads, and the The potential conversion circuit is characterized in that: in the potential conversion operation, a first high-side enable signal is used to control a pair of first switches to temporarily disconnect the current path between the pair of low-side inverter circuits and the pair of high-side latched active loads, and a second high-side enable signal is used to control a pair of second switches so that the potentials of the positive output node and the negative output node are precharged to a positive supply node. voltage; a data change detection module for performing a comparison operation on the content of a current row period and a previous row period of a display data to generate a comparison result, and generating a first enabling output signal and a second enabling output signal according to the comparison result, wherein, when the comparison result is inconsistent, the first enabling output signal and the second enabling output signal are both effective state, and when the comparison result is consistent, the first enable output signal and the second enable output signal are both in an inactive state; and a boost circuit, coupled to the bit potential conversion module and the bit potential conversion module, for correspondingly boosting the first enable output signal and the second enable output signal into the first high-side enable signal and the second high-side enable signal.

In one embodiment, the display data is provided by a timing control unit.

In one embodiment, the positive input signal and the negative input signal are provided by a shift register, and the shift register generates the positive input signal and the negative input signal according to the display data provided by the timing control unit.

To achieve the above object, the present invention further proposes a source drive circuit having a plurality of output channels, each of which has a potential conversion circuit, and the potential conversion circuit has: a bit potential conversion module having a pair of low-side inverter circuits and a pair of high-side latched active loads to perform a positive input signal and a negative input signal. A potential conversion operation is performed, wherein a positive output node and a negative output node are provided between the pair of low-side inverter circuits and the pair of high-side latched active loads, and the potential conversion circuit is characterized in that: in the potential conversion operation, a first high-side enabling signal is used to control a pair of first switches to temporarily disconnect the pair of low-side inverter circuits and the pair of high-side latched active loads. A current path between a positive output node and a load, and a second high-side enable signal is used to control a pair of second switches so that the potentials of the positive output node and the negative output node are precharged to a positive supply voltage; a data change detection module is used to perform a comparison operation on the content of a current row period and a previous row period of a display data to generate a comparison result, and generate a first enable output signal and a second enable output signal according to the comparison result, wherein, when the comparison result is inconsistent, the first enable output signal and the second enable output signal are both in an active state, and when the comparison result is consistent, the first enable output signal and the second enable output signal are both in an inactive state.

In one embodiment, and the display data are provided by a timing control unit.

In one embodiment, the positive input signal and the negative input signal are provided by a shift register, and the shift register generates the positive input signal and the negative input signal according to the display data provided by the timing control unit.

To achieve the above-mentioned purpose, the present invention further proposes a display device, which includes a display panel and a source driving circuit as described above for driving the display panel.

In a possible embodiment, the display may be a liquid crystal display, a sub-millimeter diode light-emitting display, a micron diode light-emitting display, a quantum dot diode light-emitting display or an organic light-emitting diode display.

To achieve the above-mentioned purpose, the present invention further proposes an information processing device having a central processing unit and a display as described above, wherein the central processing unit is used to communicate with the display.

In a possible embodiment, the information processing device may be a portable computer, a car computer, a smart watch, a smart bracelet, a smart phone, a VR glasses or an AR glasses.

In order to enable the review committee to further understand the structure, features, purpose, and advantages of the present invention, the detailed description of the drawings and preferred specific embodiments is attached as follows.

10: Shift register

20: Potential conversion circuit

21a: PMOS transistor

21b: PMOS transistor

22a: PMOS transistor

22b: PMOS transistor

23a:NMOS transistor

23b:NMOS transistor

24a:NMOS transistor

24b:NMOS transistor

30: Digital to analog conversion circuit

40: Buffer amplifier

100: Potential conversion circuit

101a:PMOS transistor

101b:PMOS transistor

102a: PMOS transistor

102b:PMOS transistor

103a:NMOS transistor

103b:NMOS transistor

104a:NMOS transistor

104b:NMOS transistor

105a:NMOS transistor

105b:NMOS transistor

106a:PMOS transistor

106b:PMOS transistor

107: Data change detection module

107a: First latch

107b: Second latch

107c: Third latch

107d: Mutex or gate

107e: First inverter

107f: Second inverter

107g: First or gate

107h: Second or gate

108:Boost circuit

110: Timing control unit

120: Shift register

200: Display

210: Display panel

220: Source drive circuit

221: Output channel

300: Information processing device

310: Central Processing Unit

320: Display

FIG1 is a block diagram of an output channel of an existing active-electrode driver chip; FIG2 is a circuit diagram of the potential conversion circuit of FIG1; FIG3 is a circuit diagram of an embodiment of the potential conversion circuit of the present invention; FIG4 is a circuit diagram of an embodiment of the data change detection module of the potential conversion circuit of FIG3; FIG5 is a working timing diagram of the data change detection module of FIG4; FIG4 is a circuit diagram of FIG3 FIG. 6 is a timing diagram of the potential conversion operation of the potential conversion circuit of FIG. 3 when the content of the current row period and the previous row period of the display data changes; FIG. 7 is a block diagram of an embodiment of the display of the present invention; and FIG. 8 is a block diagram of an embodiment of the information processing device of the present invention.

Please refer to Figure 3, which shows a circuit diagram of an embodiment of the potential conversion circuit of the present invention.

As shown in FIG. 3 , a potential conversion circuit 100 has a bit potential conversion module, a data change detection module 107 and a boost circuit 108, wherein the bit potential conversion module is coupled between a high-side positive supply voltage AVDD and a reference ground to perform a potential conversion operation on a positive input signal VIP and a negative input signal VIN; the data change detection module 107 is coupled between a low-side positive supply voltage VDD and the reference ground, and the boost circuit 108 is coupled between the high-side positive supply voltage AVDD and a high-side negative supply voltage AVSS; and the positive input signal VIP and the negative input signal VIN are provided by a shift register 120 and are generated according to the binary value of a display data DIN provided by the timing control unit 110. In fact, although only one bit potential conversion module is shown in FIG. 3, since the display data DIN has multiple bits, the potential conversion circuit 100 includes multiple bit potential conversion modules.

In addition, in addition to providing display data DIN, the timing control unit 110 also provides a first enable signal EN1, a second enable signal EN2, N sampling pulse signals SAM[1]~SAM[N], a current row data latch signal LD and a previous row data latch signal LD1, where N is a positive integer greater than 1.

The data change detection module 107 controls the latch display data DIN in the current row and the previous row according to SAM[j], LD, and LD1, where j is an integer between 1 and N, and determines whether to enable a first enable output signal EN1O and a second enable output signal EN2O to correspond to the output of the first enable signal EN1 and the second enable signal EN2 according to the comparison result of the content of the display data DIN in the two periods (the active state is logical 0 in this embodiment). In detail, when the comparison result of the contents of the two periods is inconsistent, the first enable output signal EN1O and the second enable output signal EN2O both present a logical 0 level; when the comparison result of the contents of the two periods is consistent, the first enable output signal EN1O and the second enable output signal EN2O both present a logical 1 level.

Please refer to FIG. 4, which shows a circuit diagram of an embodiment of the data change detection module 107 of the potential conversion circuit 100 of FIG. 3. As shown in FIG. 4, the data change detection module 107 has a first latch 107a, a second latch 107b, a third latch 107c, a mutually exclusive OR gate 107d, a first inverter 107e, a second inverter 107f, a first OR gate 107g and a second OR gate 107h.

The first latch 107a controls the contents of the display data DIN according to the sampling pulse signal SAM[j].

The second latch 107b latches the output content D1 of the first latch 107a according to the control of the current row data latch signal LD to obtain a current data D2 (T).

The third latch 107c latches the output content D1 of the first latch 107a according to the control of the previous row data latch signal LD1 to obtain a previous data D2 (T-1), wherein the previous row data latch signal LD1 lags behind the current row data latch signal LD by a predetermined short time.

The exclusive OR gate 107d is used to perform an exclusive OR operation on the current data D2(T) and the previous data D2(T-1). When the two data are the same, the output of the exclusive OR gate 107d is 0, and when the two data are different, the output of the exclusive OR gate 107d is 1.

The first inverter 107e is used to perform an inversion operation on the output of the exclusive OR gate 107d; the second inverter 107f is used to perform an inversion operation on the output of the exclusive OR gate 107d.

The first OR gate 107g is used to perform an OR operation on the first enable signal EN1 and the output of the first inverter 107e to generate the first enable output signal EN1O; the second OR gate 107h is used to perform an OR operation on the second enable signal EN2 and the output of the second inverter 107f to generate the second enable output signal EN2O.

Please refer to FIG5, which shows a working timing diagram of the data change detection module 107 of FIG4. As shown in FIG5, between every two adjacent pulses of the horizontal scanning signal HSYNC, N sampling pulse signals SAM[1]~SAM[N] appear in sequence, where N is an integer greater than 1; the current row data latch signal LD leads the previous row data latch signal LD1 by a time gap, and in the time gap, EN1 and EN2 are both low. In detail, during this time gap, the second latch 107b has output the current data according to the current row data latch signal LD, and the third latch 107c still outputs the previous data because the previous row data latch signal LD1 has not arrived. Therefore, the result of the exclusive OR operation performed by the exclusive OR gate 107d on the current data D2(T) and the previous data D2(T-1) can be used to mask EN1 and EN2.

Returning to FIG. 3 , the boost circuit 108 is used to increase the logic 1 potential of the low-side first enable output signal EN1O and the second enable output signal EN2O to be close to the high-side positive supply voltage AVDD, and use a first high-side enable signal EN1H and a second high-side enable signal EN2H as the corresponding high-side output signals.

The bit potential conversion module includes a pair of active loads (composed of a PMOS transistor 101a and a PMOS transistor 101b), a latch circuit (composed of a PMOS transistor 102a and a PMOS transistor 102b), a pair of first cascade loads (composed of an NMOS transistor 103a and an NMOS transistor 103b), a pair of second cascade loads (composed of an NMOS transistor 104a and an NMOS transistor 104b), a pair of inverters (composed of an NMOS transistor 105a and an NMOS transistor 105b) and a pair of pull-up switches (composed of a PMOS transistor 106a and a PMOS transistor 106b).

In the pair of active loads, the source of the PMOS transistor 101a and the source of the PMOS transistor 101b are commonly coupled to the high-side positive supply voltage AVDD, the gate of the PMOS transistor 101a and the gate of the PMOS transistor 101b are commonly coupled to a first DC voltage VBP, the drain of the PMOS transistor 101a is coupled to the source of the PMOS transistor 102a, and the drain of the PMOS transistor 101b is coupled to the source of the PMOS transistor 102b.

In the latch circuit, the source of PMOS transistor 102a is coupled to the drain of PMOS transistor 101a, the gate is coupled to the positive output node Q, and the drain is coupled to the negative output node QB; the source of PMOS transistor 102b is coupled to the drain of PMOS transistor 101b, the gate is coupled to the negative output node QB, and the drain is coupled to the positive output node Q.

In the pair of first cascaded loads, the drain of NMOS transistor 103a is coupled to the negative output node QB, the gate is coupled to the first high-side enable signal EN1H, and the source is coupled to the drain of NMOS transistor 104a; The drain of NMOS transistor 103b is coupled to the positive output node Q, the gate is coupled to the first high-side enable signal EN1H, and the source is coupled to the drain of NMOS transistor 104b.

In the pair of second cascade loads, the drain of NMOS transistor 104a is coupled to the source of NMOS transistor 103a, the gate is coupled to a second DC voltage VBN, and the source is coupled to the drain of NMOS transistor 105a; the drain of NMOS transistor 104b is coupled to the source of NMOS transistor 103b, the gate is coupled to the second DC voltage VBN, and the source is coupled to the drain of NMOS transistor 105b.

In the pair of inverters, the drain of NMOS transistor 105a is coupled to the source of NMOS transistor 104a, the gate is coupled to the positive input signal VIP, the source is coupled to a ground node GND, and the ground node GND is further connected to the reference ground via a conductive path; the drain of NMOS transistor 105b is coupled to the source of NMOS transistor 104b, the gate is coupled to the negative input signal VIN, and the source is coupled to the ground node GND.

In the pair of pull-up switches, the source of the PMOS transistor 106a is coupled to the high-side positive supply voltage AVDD, the gate is coupled to the second high-side enable signal EN2H, and the drain is coupled to the negative output node QB; the source of the PMOS transistor 106b is coupled to the high-side positive supply voltage AVDD, the gate is coupled to the second high-side enable signal EN2H, and the drain is coupled to the positive output node Q.

Please refer to Figure 6, which is a timing diagram of the potential conversion operation of the bit potential conversion module when the content of the current row period and the previous row period of the display data DIN changes. As shown in Figure 4, the timing of the potential conversion operation includes 5 time points from t1, t2, t3, t4, and t5.

In the first potential conversion operation:

At time t1: the first high-side enable signal EN1H changes from high to low, causing the NMOS transistor 103a and the NMOS transistor 103b to be disconnected; and the second high-side enable signal EN2H maintains a high level, causing the PMOS transistor 106a and the PMOS transistor 106b to remain disconnected.

At time t2: the first high-side enable signal EN1H maintains a low level, causing the NMOS transistor 103a and the NMOS transistor 103b to remain disconnected; and the second high-side enable signal EN2H changes from a high level to a low level, causing the PMOS transistor 106a and the PMOS transistor 106b to be turned on and the potentials of the nodes Q and QB to be pulled up to VDD.

At time t3: the bit potential conversion module enters a display signal receiving period (in this potential conversion operation, the input signal VIP is high), the first high-side enable signal EN1H maintains a low level, causing the NMOS transistor 103a and the NMOS transistor 103b to remain disconnected; and the second high-side enable signal EN2H maintains a low level, causing the PMOS transistor 106a and the PMOS transistor 106b to remain in the on state and the potential of the node Q and the node QB to remain at VDD.

At time t4: the first high-side enable signal EN1H maintains a low potential, causing the NMOS transistor 103a and the NMOS transistor 103b to remain disconnected; and the second high-side enable signal EN2H changes from a low potential to a high potential, causing the PMOS transistor 106a and the PMOS transistor 106b to be disconnected. At this time, the potentials of the nodes Q and QB remain at VDD.

At time t5: the first high-side enable signal EN1H changes from low to high, causing NMOS transistor 103a and NMOS transistor 103b to be turned on; and the second high-side enable signal EN2H maintains a high level, causing PMOS transistor 106a and PMOS transistor 106b to remain disconnected. At this time, the bit potential conversion module enters a potential conversion period, the potential of node Q remains at VDD, and the potential of node QB is pulled down from VDD to the reference ground.

In the second potential conversion operation:

At time t1: the first high-side enable signal EN1H changes from high to low, causing the NMOS transistor 103a and the NMOS transistor 103b to be disconnected; and the second high-side enable signal EN2H maintains a high level, causing the PMOS transistor 106a and the PMOS transistor 106b to remain disconnected.

At time t2: the first high-side enable signal EN1H maintains a low level, causing the NMOS transistor 103a and the NMOS transistor 103b to remain disconnected; and the second high-side enable signal EN2H changes from a high level to a low level, causing the PMOS transistor 106a and the PMOS transistor 106b to be turned on and the potentials of the nodes Q and QB to be pulled up to VDD.

At time t3: the bit potential conversion module enters a display signal receiving period (in this potential conversion operation, the input signal VIP high potential changes to low potential), the first high-side enable signal EN1H maintains a low potential, causing the NMOS transistor 103a and the NMOS transistor 103b to remain disconnected; and the second high-side enable signal EN2H maintains a low potential, causing the PMOS transistor 106a and the PMOS transistor 106b to remain in the on state and the potential of the node Q and the node QB to remain at VDD.

At time t4: the first high-side enable signal EN1H maintains a low potential, causing the NMOS transistor 103a and the NMOS transistor 103b to remain disconnected; and the second high-side enable signal EN2H changes from a low potential to a high potential, causing the PMOS transistor 106a and the PMOS transistor 106b to be disconnected. At this time, the potentials of the nodes Q and QB remain at VDD.

At time t5: the first high-side enable signal EN1H changes from low to high, causing NMOS transistor 103a and NMOS transistor 103b to be turned on; and the second high-side enable signal EN2H maintains a high level, causing PMOS transistor 106a and PMOS transistor 106b to remain disconnected. At this time, the bit potential conversion module enters a potential conversion period, the potential of node Q is pulled down from VDD to the reference ground, and the potential of node QB is maintained at VDD.

Accordingly, the present invention can make the channel current of NMOS transistor 105a and NMOS transistor 105b zero in each potential conversion operation, so that when multiple output channels are operated simultaneously, the sum of the instantaneous currents of the output channels can be effectively prevented from generating a voltage drop between the ground node GND and the reference ground (i.e., generating a voltage on the path resistance between the ground node GND and the reference ground), causing NMOS transistor 105a and NMOS transistor 105b to fail to operate normally, thereby causing the output of the potential conversion circuit 100 to be abnormal.

As can be seen from the above description, the present invention discloses a bit potential conversion module, which has a pair of low-side inverter circuits and a pair of high-side latched active loads to perform a potential conversion operation on a positive input signal and a negative input signal, and there is a positive output node and a negative output node between the pair of low-side inverter circuits and the pair of high-side latched active loads, and the characteristics of the bit potential conversion module are In the potential conversion operation, a pair of first switches is used to determine whether to temporarily disconnect the current path between the pair of low-side inverter circuits and the pair of high-side latched active loads, and a pair of second switches is used to determine whether to pre-charge the potentials of the positive output node and the negative output node to a positive supply voltage, and the decision is based on the comparison results of the pixel display data of the previous and next rows.

In addition, in the bit potential conversion module of the present invention, the first enable signal and the second enable signal are provided by a timing control unit; the positive input signal and the negative input signal are provided by a shift register, and the shift register generates the positive input signal and the negative input signal according to a display data provided by the timing control unit.

According to the above description, the present invention further proposes a display. Please refer to FIG. 7, which shows a block diagram of an embodiment of the display of the present invention. As shown in FIG. 7, a display 200 includes a display panel 210 and a source drive circuit 220 for driving the display panel 210, wherein the source drive circuit 220 has a plurality of output channels 221, each of which has a potential conversion circuit, and the potential conversion circuit is implemented by the potential conversion circuit 100.

In addition, the display 200 may be a liquid crystal display, a sub-millimeter diode light-emitting display, a micron diode light-emitting display, a quantum dot diode light-emitting display or an organic light-emitting diode display.

In addition, according to the above description, the present invention further proposes an information processing device. Please refer to FIG. 8, which shows a block diagram of an embodiment of the information processing device of the present invention. As shown in FIG. 8, an information processing device 300 has a central processing unit 310 and a display 320, wherein the display 320 is implemented by the display 200 and the central processing unit 310 is used to communicate with the display 320.

In addition, the information processing device 300 may be a portable computer, a car computer, a smart watch, a smart bracelet, a smart phone, a VR glasses, or an AR glasses.

According to the above design, the present invention has the following advantages:

1. The potential conversion circuit of the present invention can determine whether to perform a pre-charge operation according to the comparison results of the pixel display data of the previous and next rows during a potential conversion operation, thereby improving the response speed of the potential conversion circuit and eliminating unnecessary dynamic power consumption;

2. The source drive circuit of the present invention can improve the response speed of its output channel and eliminate unnecessary dynamic power consumption through the aforementioned potential conversion circuit;

3. The display of the present invention can improve the display effect of dynamic images and eliminate unnecessary dynamic power consumption through the aforementioned source drive circuit; and

4. The information processing device of the present invention can improve the display effect of dynamic images and eliminate unnecessary dynamic power consumption through the aforementioned display.

What is disclosed in this case is a better embodiment. Any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by people familiar with the art do not deviate from the scope of the patent rights of this case.

In summary, this case shows that it is very different from the known technology in terms of purpose, means and effect, and it is the first invention that is practical and indeed meets the patent requirements for invention. We sincerely ask the review committee to examine it carefully and grant a patent as soon as possible to benefit the society. This is our utmost prayer.

100: Potential conversion circuit

101a:PMOS transistor

101b:PMOS transistor

102a: PMOS transistor

102b:PMOS transistor

103a:NMOS transistor

103b:NMOS transistor

104a:NMOS transistor

104b:NMOS transistor

105a:NMOS transistor

105b:NMOS transistor

106a:PMOS transistor

106b:PMOS transistor

107: Data change detection module

108:Boost circuit

110: Timing control unit

120: Shift register

Claims (11)

A potential conversion circuit has: A one-bit potential conversion module, having a pair of low-side inverter circuits and a pair of high-side latched active loads to perform a potential conversion operation on a positive input signal and a negative input signal, a positive output node and a negative output node between the pair of low-side inverter circuits and the pair of high-side latched active loads, and the potential conversion circuit is characterized in that: In the potential conversion operation, a first high-side enable signal is used to control a pair of first switches to temporarily disconnect the current path between the pair of low-side inverter circuits and the pair of high-side latched active loads, and a second high-side enable signal is used to control a pair of second switches so that the potentials of the positive output node and the negative output node are precharged to a positive supply voltage; A data change detection module is used to perform a comparison operation on the content of the current row period and the previous row period of a display data to generate a comparison result, and generate a first enable output signal and a second enable output signal according to the comparison result, wherein when the comparison result is inconsistent, the first enable output signal and the second enable output signal are both in an active state, and when the comparison result is consistent, the first enable output signal and the second enable output signal are both in an inactive state; and a boost circuit is coupled to the bit potential conversion module and the bit potential conversion module, and is used to correspondingly boost the first enable output signal and the second enable output signal into the first high-side enable signal and the second high-side enable signal. A potential conversion circuit as described in claim 1, wherein the display data is provided by a timing control unit. A potential conversion circuit as described in claim 2, wherein the positive input signal and the negative input signal are provided by a shift register, and the shift register generates the positive input signal and the negative input signal according to the display data provided by the timing control unit. A source drive circuit has a plurality of output channels, each of which has a potential conversion circuit, and the potential conversion circuit has: A bit potential conversion module, having a pair of low-side inverter circuits and a pair of high-side latched active loads to perform a potential conversion operation on a positive input signal and a negative input signal, and having a positive output node and a negative output node between the pair of low-side inverter circuits and the pair of high-side latched active loads, and the potential conversion circuit is characterized in that: In the potential conversion operation, a first high-side enable signal is used to control a pair of first switches to temporarily disconnect the current path between the pair of low-side inverter circuits and the pair of high-side latched active loads, and a second high-side enable signal is used to control a pair of second switches so that the potentials of the positive output node and the negative output node are precharged to a positive supply voltage; A data change detection module is used to perform a comparison operation on the content of the current row period and the previous row period of a display data to generate a comparison result, and generate a first enable output signal and a second enable output signal according to the comparison result, wherein when the comparison result is inconsistent, the first enable output signal and the second enable output signal are both in an active state, and when the comparison result is consistent, the first enable output signal and the second enable output signal are both in an inactive state; and a boost circuit is coupled to the bit potential conversion module and the bit potential conversion module, and is used to correspondingly boost the first enable output signal and the second enable output signal into the first high-side enable signal and the second high-side enable signal. A source drive circuit as described in claim 4, wherein the display data is provided by a timing control unit. A source drive circuit as described in claim 5, wherein the positive input signal and the negative input signal are provided by a shift register, and the shift register generates the positive input signal and the negative input signal according to the display data provided by the timing control unit. A display comprises a display panel and a source driving circuit as described in any one of claims 4 to 6 for driving the display panel. The display as described in claim 7 is selected from the group consisting of a liquid crystal display, a sub-millimeter diode light-emitting display, a micron diode light-emitting display, a quantum dot diode light-emitting display and an organic light-emitting diode display. An information processing device having a central processing unit and a display as described in claim 7, wherein the central processing unit is used to communicate with the display. An information processing device as described in claim 9, wherein the display is selected from the group consisting of a liquid crystal display, a sub-millimeter diode light-emitting display, a micron diode light-emitting display, a quantum dot diode light-emitting display and an organic light-emitting diode display. The information processing device as described in claim 10 is selected from the group consisting of a portable computer, a car computer, a smart watch, a smart bracelet, a smart phone, VR glasses and AR glasses.

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