TWI892673B - Potential conversion circuit, source drive circuit, display and information processing device - Google Patents

Abstract

A potential conversion circuit, incorporated into a source driver chip, is characterized by providing a rail-to-rail swing to an inverting logic drive signal via a weak pull-high active load. The inverting logic drive signal is then used to drive an output inverter, ensuring that no leakage current is generated in the output inverter when the output inverter outputs a logical 0 potential, thereby optimizing the power consumption specification of the source driver chip.

Description

Potential conversion circuit, source drive circuit, display and information processing device

The present invention relates to a display driver circuit, and more particularly to a source driver potential conversion circuit.

As market demand evolves, display applications have expanded from TVs, laptops, mobile phones, and watches to VR (virtual reality) and AR (augmented reality) glasses. However, due to limited circuit board area, the display's source driver circuit cannot rely on multiple driver chips connected in series. Instead, a single driver chip must provide a large number of output channels to meet high-resolution display requirements.

Please refer to Figure 1, which is a block diagram of an output channel of a conventional active-state driver chip. As shown in Figure 1, the output channel includes a shift register 10, a level conversion circuit 20, a digital-to-analog converter circuit 30, and a buffer amplifier 40. The shift register 10 is used to store display data DIN input in a serial format and output the display data DIN in a parallel format; the level conversion circuit 20 is used to increase the logical level of the display data DIN to output a corresponding digital signal; the digital-to-analog converter circuit 30 is used to generate an analog voltage based on the corresponding digital signal; and the buffer amplifier 40 is used to generate an output voltage VOUT based on the analog voltage to drive a display.

Please refer to FIG2 , which shows a circuit diagram of the potential conversion circuit 20 in FIG1 . As shown in Figure 2, the potential conversion circuit 20 is coupled between a positive supply voltage VDD and a reference ground and includes a pair of active loads (composed of a PMOS transistor 21a and a PMOS transistor 21b), a latch circuit (composed of a PMOS transistor 22a and a PMOS transistor 22b), a pair of first cascade loads (composed of a PMOS transistor 23a and a PMOS transistor 23b), a pair of second cascade loads (composed of an NMOS transistor 24a and an NMOS transistor 24b), a pair of inverters (composed of an NMOS transistor 25a and an NMOS transistor 25b), and an output inverter (composed of a PMOS transistor 26a and an NMOS transistor 26b).

In the pair of active loads, the source of PMOS transistor 21a and the source of PMOS transistor 21b are commonly coupled to the positive supply voltage VDD, the gate of PMOS transistor 21a is coupled to a node A, the gate of PMOS transistor 21b is coupled to a node B, the drain of PMOS transistor 21a is coupled to the source of PMOS transistor 22a, and the drain of PMOS transistor 21b is coupled to the source of PMOS transistor 22b.

In this latching circuit, the source of PMOS transistor 22a is coupled to the drain of PMOS transistor 21a, the gate is coupled to node B, and the drain is coupled to node A. The source of PMOS transistor 22b is coupled to the drain of PMOS transistor 21b, the gate is coupled to node A, and the drain is coupled to node B.

In the first pair of cascaded loads, the source of PMOS transistor 23a is coupled to the drain of PMOS transistor 22a, the gate is coupled to a node C, and the drain is coupled to node C; the source of PMOS transistor 23b is coupled to the drain of PMOS transistor 22b, the gate is coupled to a node D, and the drain is coupled to node D.

In the second pair of cascaded loads, the drain of NMOS transistor 24a is coupled to node C, the gate is coupled to DC voltage VBN, and the source is coupled to the drain of NMOS transistor 25a; the drain of NMOS transistor 24b is coupled to node D, the gate is coupled to DC voltage VBN, and the source is coupled to the drain of NMOS transistor 25b.

In this pair of inverters, NMOS transistor 25a has a drain coupled to the source of NMOS transistor 24a, a gate coupled to a negative input signal INB, and a source coupled to a reference ground GND. NMOS transistor 25b has a drain coupled to the source of NMOS transistor 24b, a gate coupled to a positive input signal IN, and a source coupled to the reference ground GND. The positive input signal IN and the negative input signal INB are provided by shift register 10.

In the output inverter, the source of the PMOS transistor 26a is coupled to the positive supply voltage VDD, the gate is coupled to the node B, and the drain is coupled to an output node E; the drain of the NMOS transistor 26b is coupled to the node E, the gate is coupled to the node D, and the source is coupled to the reference ground GND.

During operation, when the positive input signal IN is logic 1, the potential of node B will be pulled low, causing the PMOS transistor 22a to turn on and the potential of node A to turn off the PMOS transistor 22b, thereby locking the potential of nodes B and D at a low potential to turn on the PMOS transistor 26a and turn off the NMOS transistor 26b. At this time, the potential of the output node E is pulled up to VDD. When the negative input signal INB is at logic 1, the potential of node A is pulled low, turning on PMOS transistor 22b and pulling up the potential of node B to disconnect PMOS transistor 22a. This, in turn, locks the potentials of nodes B and D at high levels, disconnecting PMOS transistor 26a and turning on NMOS transistor 26b. At this time, the potential of output node E is pulled low to the reference ground GND.

However, when the negative input signal INB is at logic 1, the potential at node B has an upper limit due to the source-gate voltage of PMOS transistor 21b. This upper limit is equal to (VDD - VTH), where VTH is the conduction threshold voltage of PMOS transistor 21b. In this case, PMOS transistor 26a is not fully turned off, and leakage current will occur. When the driver chip provides a large number of output channels, this leakage current phenomenon degrades the power consumption specification of the driver chip.

To solve the above problems, a novel potential conversion circuit is urgently needed in this field.

The main purpose of this invention is to provide a potential conversion circuit that can ensure that the PMOS transistor of the output inverter is turned off when the output voltage is low to minimize the leakage current of the output inverter, thereby optimizing the power consumption specification of a source drive circuit.

Another object of the present invention is to provide a source drive circuit that can optimize its power consumption specifications by using the aforementioned potential conversion circuit.

Another object of the present invention is to provide a display device that can optimize its power consumption specifications by using the aforementioned source drive circuit.

To achieve the above object, a potential conversion circuit is proposed, which has: a first PMOS transistor and a second PMOS transistor, wherein the first PMOS transistor has a first source, a first gate and a first drain, the first source is used to couple a positive supply voltage, the first gate is used to couple a first DC voltage; and the second PMOS transistor The transistor has a second source, a second gate, and a second drain, the second source is coupled to the positive supply voltage, and the second gate is coupled to the first DC voltage; a third PMOS transistor and a fourth PMOS transistor, wherein the third PMOS transistor has a third source, a third gate, and a third drain, the third source is coupled to the first drain, and the The third gate is coupled to a positive output node, the third drain is coupled to a negative output node; the fourth PMOS transistor has a fourth source, a fourth gate, and a fourth drain, the fourth source is coupled to the second drain, the fourth gate is coupled to the negative output node, and the fourth drain is coupled to the positive output node; a first NMOS transistor and a second NMOS transistor, The first NMOS transistor has a fifth drain, a fifth gate, and a fifth source, the fifth drain being coupled to the negative output node, and the fifth gate being coupled to a first enable signal; and the second NMOS transistor has a sixth drain, a sixth gate, and a sixth source, the sixth drain being coupled to the positive output node, and the sixth gate being coupled to the first enable signal; three NMOS transistors and a fourth NMOS transistor, wherein the third NMOS transistor has a seventh drain, a seventh gate, and a seventh source, the seventh drain is coupled to the fifth source, and the seventh gate is coupled to a second DC voltage; and the fourth NMOS transistor has an eighth drain, an eighth gate, and an eighth source, the eighth drain is coupled to the sixth source , the eighth gate is coupled to the second DC voltage; a fifth NMOS transistor and a sixth NMOS transistor, wherein the fifth NMOS transistor has a ninth drain, a ninth gate and a ninth source, the ninth drain is coupled to the seventh source, the ninth gate is coupled to a positive input signal, and the ninth source is coupled to a ground node; and the sixth NMOS transistor has a a tenth drain, a tenth gate, and a tenth source, the tenth drain being coupled to the eighth source, the tenth gate being coupled to a negative input signal, and the tenth source being coupled to the ground node; and a fifth PMOS transistor and a sixth PMOS transistor, wherein the fifth PMOS transistor has an eleventh source, an eleventh gate, and an eleventh drain, the eleventh source being coupled to the eighth source, the tenth gate being coupled to a negative input signal, and the tenth source being coupled to the ground node. The eleventh gate is coupled to the positive supply voltage, the eleventh gate is coupled to a second enable signal, and the eleventh drain is coupled to the negative output node; and the sixth PMOS transistor has a twelfth source, a twelfth gate, and a twelfth drain, the twelfth source is coupled to the positive supply voltage, the twelfth gate is coupled to the second enable signal, and the twelfth drain is coupled to the positive output node.

In one embodiment, the first enable signal and the second enable signal are provided by a timing control unit.

In one embodiment, the positive input signal and the negative input signal are provided by a shift register, and the shift register generates the positive input signal and the negative input signal according to a display data provided by the timing control unit.

In one embodiment, the potential conversion circuit performs a potential conversion operation under the control of the first enable signal and the second enable signal. The potential conversion operation is characterized in that the first enable signal disconnects the first NMOS transistor and the second NMOS transistor before the positive input signal and the negative input signal are input, and the second enable signal turns on the fifth PMOS transistor and the sixth PMOS transistor after the first NMOS transistor and the second NMOS transistor are disconnected, thereby pulling the positive output node and the negative output node to the positive supply voltage.

Specifically, the present invention discloses a potential conversion circuit having a pair of low-side inverter circuits and a pair of high-side latched active loads for performing a potential conversion operation on a positive input signal and a negative input signal. A positive output node and a negative output node are located between the pair of low-side inverter circuits and the pair of high-side latched active loads. The potential conversion circuit is characterized in that, during the potential conversion operation, a pair of first switches temporarily disconnects the current path between the pair of low-side inverter circuits and the pair of high-side latched active loads, and a pair of second switches precharges the potentials of the positive output node and the negative output node to a positive supply voltage.

To achieve the above object, the present invention further proposes a source drive circuit having a plurality of output channels, each of which has a potential conversion circuit, and the potential conversion circuit has: a first PMOS transistor and a second PMOS transistor, wherein the first PMOS transistor has a first source, a first gate and a first drain, and the first source is used to couple a positive supply voltage, the first gate is coupled to a first DC voltage; the second PMOS transistor has a second source, a second gate, and a second drain, the second source is coupled to the positive supply voltage, and the second gate is coupled to the first DC voltage; a third PMOS transistor and a fourth PMOS transistor, wherein the third PMOS transistor has a first The third source is coupled to the first drain, the third gate is coupled to a positive output node, and the third drain is coupled to a negative output node; and the fourth PMOS transistor has a fourth source, a fourth gate, and a fourth drain, the fourth source is coupled to the second drain, the fourth gate is coupled to the negative output node, and the fourth drain is coupled to the positive output node. Node; a first NMOS transistor and a second NMOS transistor, wherein the first NMOS transistor has a fifth drain, a fifth gate and a fifth source, the fifth drain is coupled to the negative output node, the fifth gate is coupled to a first enable signal; and the second NMOS transistor has a sixth drain, a sixth gate and a sixth source, the sixth drain is coupled to the positive output node point, the sixth gate coupled to the first enable signal; a third NMOS transistor and a fourth NMOS transistor, wherein the third NMOS transistor has a seventh drain, a seventh gate and a seventh source, the seventh drain coupled to the fifth source, the seventh gate coupled to a second DC voltage; and the fourth NMOS transistor has an eighth drain, an eighth gate and an eighth source The eighth drain is coupled to the sixth source, and the eighth gate is coupled to the second DC voltage; a fifth NMOS transistor and a sixth NMOS transistor, wherein the fifth NMOS transistor has a ninth drain, a ninth gate, and a ninth source, the ninth drain is coupled to the seventh source, the ninth gate is coupled to a positive input signal, and the ninth source is coupled to a ground node; and the sixth NMOS transistor The MOS transistor has a tenth drain, a tenth gate, and a tenth source, the tenth drain being coupled to the eighth source, the tenth gate being coupled to a negative input signal, and the tenth source being coupled to the ground node; and a fifth PMOS transistor and a sixth PMOS transistor, wherein the fifth PMOS transistor has an eleventh source, an eleventh gate, and an eleventh drain, and the sixth PMOS transistor has an eleventh source, an eleventh gate, and an eleventh drain. The eleventh source is coupled to the positive supply voltage, the eleventh gate is coupled to a second enable signal, and the eleventh drain is coupled to the negative output node; and the sixth PMOS transistor has a twelfth source, a twelfth gate, and a twelfth drain, the twelfth source is coupled to the positive supply voltage, the twelfth gate is coupled to the second enable signal, and the twelfth drain is coupled to the positive output node.

In one embodiment, the first enable signal and the second enable signal are provided by a timing control unit.

In one embodiment, the positive input signal and the negative input signal are provided by a shift register, and the shift register generates the positive input signal and the negative input signal according to a display data provided by the timing control unit.

In one embodiment, the potential conversion circuit performs a potential conversion operation under the control of the first enable signal and the second enable signal. The potential conversion operation is characterized in that the first enable signal disconnects the first NMOS transistor and the second NMOS transistor before the positive input signal and the negative input signal are input, and the second enable signal turns on the fifth PMOS transistor and the sixth PMOS transistor after the first NMOS transistor and the second NMOS transistor are disconnected, thereby pulling the positive output node and the negative output node to the positive supply voltage.

To achieve the above-mentioned objectives, the present invention further provides a display comprising a display panel and a source drive circuit as described above for driving the display panel.

In a possible embodiment, the display may be a liquid crystal display, a sub-millimeter diode light-emitting display, a micron diode light-emitting display, a quantum dot diode light-emitting display, or an organic light-emitting diode display.

To achieve the above-mentioned objectives, the present invention further provides an information processing device having a central processing unit and a display as described above, wherein the central processing unit is configured to communicate with the display.

In a possible embodiment, the information processing device may be a portable computer, a car computer, a smart watch, a smart bracelet, a smart phone, VR glasses, or AR glasses.

To help you better understand the structure, features, objectives, and advantages of this invention, we have attached drawings and detailed descriptions of preferred embodiments.

10: Shift register

20: Potential conversion circuit

21a: PMOS transistor

21b: PMOS transistor

22a: PMOS transistor

22b: PMOS transistor

23a: PMOS transistor

23b: PMOS transistor

24a: NMOS transistor

24b: NMOS transistor

25a: NMOS transistor

25b: NMOS transistor

26a: PMOS transistor

26b: NMOS transistor

30: Digital to Analog Converter Circuit

40: Buffer amplifier

100: Potential conversion circuit

101a: PMOS transistor

101b: PMOS transistor

102a: PMOS transistor

102b: PMOS transistor

103a: PMOS transistor

103b: PMOS transistor

104a: NMOS transistor

104b: NMOS transistor

105a: NMOS transistor

105b: NMOS transistor

106a: PMOS transistor

106b: PMOS transistor

107a: PMOS transistor

107b: NMOS transistor

110: Timing control unit

120: Shift register

200: Display

210: Display Panel

220: Source drive circuit

221: Output channel

300: Information processing device

310: Central Processing Unit

320: Display

Figure 1 is a block diagram of an output channel of a conventional active-state driver chip; Figure 2 is a circuit diagram of the potential conversion circuit of Figure 1; Figure 3 is a circuit diagram of an embodiment of the potential conversion circuit of the present invention; Figure 4 is a block diagram of an embodiment of a display of the present invention; and Figure 5 is a block diagram of an embodiment of an information processing device of the present invention.

Please refer to Figure 3, which shows a circuit diagram of an embodiment of the potential conversion circuit of the present invention.

As shown in FIG3 , a potential conversion circuit 100 is coupled between a positive supply voltage VDD and a reference ground GND and includes a pair of active loads (composed of a PMOS transistor 101a and a PMOS transistor 101b), a latch circuit (composed of a PMOS transistor 102a and a PMOS transistor 102b), a pair of first cascade loads (composed of a PMOS transistor 103a and a PMOS transistor 103b), and a first cascade load circuit (composed of a PMOS transistor 103a and a PMOS transistor 103b). ), a pair of second cascaded loads (composed of an NMOS transistor 104a and an NMOS transistor 104b), a pair of inverters (composed of an NMOS transistor 105a and an NMOS transistor 105b), a pair of pull-up loads (composed of a PMOS transistor 106a and a PMOS transistor 106b), and an output inverter (composed of a PMOS transistor 107a and an NMOS transistor 107b). Furthermore, the potential conversion circuit 100 performs a potential conversion operation under the control of a positive input signal IN and a negative input signal INB provided by a shift register 120. The shift register 120 generates a positive input signal VIP and a negative input signal VIN based on a binary value of display data DIN provided by a timing control unit 110.

In the pair of active loads, the source of PMOS transistor 101a and the source of PMOS transistor 101b are commonly coupled to the positive supply voltage VDD, the gate of PMOS transistor 101a is coupled to a node A, the gate of PMOS transistor 101b is coupled to a node B, the drain of PMOS transistor 101a is coupled to the source of PMOS transistor 102a, and the drain of PMOS transistor 101b is coupled to the source of PMOS transistor 102b.

In the latch circuit, the source of PMOS transistor 102a is coupled to the drain of PMOS transistor 101a, the gate is coupled to node B, and the drain is coupled to node A. The source of PMOS transistor 102b is coupled to the drain of PMOS transistor 101b, the gate is coupled to node A, and the drain is coupled to node B.

In the first pair of cascaded loads, the source of PMOS transistor 103a is coupled to the drain of PMOS transistor 102a, the gate is coupled to a node C, and the drain is coupled to node C; the source of PMOS transistor 103b is coupled to the drain of PMOS transistor 102b, the gate is coupled to a node D, and the drain is coupled to node D.

In the second cascaded load pair, the drain of NMOS transistor 104a is coupled to node C, the gate is coupled to a first DC voltage VBN, and the source is coupled to the drain of NMOS transistor 105a. The drain of NMOS transistor 104b is coupled to node D, the gate is coupled to the first DC voltage VBN, and the source is coupled to the drain of NMOS transistor 105b.

In the pair of inverters, the drain of NMOS transistor 105a is coupled to the source of NMOS transistor 104a, the gate is coupled to a negative input signal INB, and the source is coupled to a reference ground GND; the drain of NMOS transistor 105b is coupled to the source of NMOS transistor 104b, the gate is coupled to a positive input signal IN, and the source is coupled to the reference ground GND.

In the pair of pull-up loads, the source of PMOS transistor 106a and the source of PMOS transistor 106b are commonly coupled to the positive supply voltage VDD, the gate of PMOS transistor 106a and the gate of PMOS transistor 106b are commonly coupled to a second DC voltage VBP, the drain of PMOS transistor 106a is coupled to the source of PMOS transistor 102a, and the drain of PMOS transistor 106b is coupled to the source of PMOS transistor 102b.

In the output inverter, the source of the PMOS transistor 107a is coupled to the positive supply voltage VDD, the gate is coupled to the node B, and the drain is coupled to an output node E. The drain of the NMOS transistor 107b is coupled to the node E, the gate is coupled to the node D, and the source is coupled to the reference ground GND.

During operation, when the positive input signal IN is logic 1, the potential of node B will be pulled low, causing the PMOS transistor 102a to turn on and the potential of node A to be pulled high to disconnect the PMOS transistor 102b, thereby locking the potentials of nodes B and D at a low potential to turn on the PMOS transistor 107a and disconnect the NMOS transistor 107b. At this time, the potential of the output node E is pulled up to VDD. When the negative input signal INB is at logic 1, the potential of node A is pulled low, turning on PMOS transistor 102b and pulling up the potential of node B, disconnecting PMOS transistor 102a. This, in turn, locks the potentials of nodes B and D at high levels, disconnecting PMOS transistor 107a and turning on NMOS transistor 107b. At this point, the potential of output node E is pulled low to the reference ground GND.

It's worth noting that when the negative input signal INB is at logic 1 (and the positive input signal IN is at logic 0), NMOS transistor 105b is turned off, and the channel currents of PMOS transistors 102b and 106b are both zero. When both PMOS transistors 102b and 106b are turned on and the channel currents are zero, the source-drain voltage difference between PMOS transistors 102b and 106b is zero, making the potential at node B approximately equal to VDD. In this case, the source-gate voltage difference of PMOS transistor 107a is approximately zero, effectively disconnecting its channel and preventing leakage current. Accordingly, when the driver chip provides a large number of output channels, the present invention can optimize the power consumption specifications of the driver chip.

As can be seen from the above description, the present invention discloses a potential conversion circuit, which has: a first PMOS transistor (101a) and a second PMOS transistor (101b), wherein the first PMOS transistor has a first source, a first gate and a first drain, the first source is used to couple a positive supply voltage (VDD), the first gate is coupled to a first node (A); and the second PMOS transistor has a second source, a second gate and a second drain. , the second source is used to couple the positive supply voltage, the second gate is coupled to a second node (B); a third PMOS transistor (102a) and a fourth PMOS transistor (102b), wherein the third PMOS transistor has a third source, a third gate and a third drain, the third source is coupled to the first drain, the third gate is coupled to the second node, and the third drain is coupled to the first node; and the fourth PMOS transistor has a fourth source, a fourth gate a fourth drain, the fourth source coupled to the second drain, the fourth gate coupled to the first node, and the fourth drain coupled to the second node; a fifth PMOS transistor (103a) and a sixth PMOS transistor (103b), wherein the fifth PMOS transistor has a fifth source, a fifth gate and a fifth drain, the fifth source coupled to the first node, the fifth gate coupled to a third node (C), and the fifth drain coupled to the third node; and the sixth PMOS The S transistor has a sixth source, a sixth gate, and a sixth drain, the sixth source being coupled to the second node, the sixth gate being coupled to a fourth node (D), and the sixth drain being coupled to the fourth node; a first NMOS transistor (104a) and a second NMOS transistor (104b), wherein the first NMOS transistor has a seventh drain, a seventh gate, and a seventh source, the seventh drain being coupled to the third node, and the seventh gate being coupled to a first DC voltage (V BN); the second NMOS transistor has an eighth drain, an eighth gate and an eighth source, the eighth drain is coupled to the fourth node, and the eighth gate is coupled to the first DC voltage; a third NMOS transistor (105a) and a fourth NMOS transistor (105b), wherein the third NMOS transistor has a ninth drain, a ninth gate and a ninth source, the ninth drain is coupled to the seventh source, the ninth gate is coupled to a negative input signal (INB), the The ninth source is coupled to a reference ground (GND); the fourth NMOS transistor has a tenth drain, a tenth gate and a tenth source, the tenth drain is coupled to the eighth source, the tenth gate is coupled to a positive input signal (IN), and the tenth source is coupled to the reference ground; a seventh PMOS transistor (106a) and an eighth PMOS transistor (106b), wherein the seventh PMOS transistor has an eleventh source, an eleventh gate and an eleventh drain, the tenth A source is coupled to the positive supply voltage, the eleventh gate is used to couple a second DC voltage (VBP), and the eleventh drain is coupled to the third source; and the eighth PMOS transistor has a twelfth source, a twelfth gate and a twelfth drain, the twelfth source is coupled to the positive supply voltage, the twelfth gate is coupled to the second DC voltage, and the twelfth drain is coupled to the fourth source; and an output stage PMOS transistor (107a) and an output stage NMOS transistor (10 7b), wherein the output-stage PMOS transistor has a thirteenth source, a thirteenth gate, and a thirteenth drain, the thirteenth source coupled to the positive supply voltage, the thirteenth gate coupled to the second node, and the thirteenth drain coupled to an output node (E); and the output-stage NMOS transistor has a fourteenth drain, a fourteenth gate, and a fourteenth source, the fourteenth drain coupled to the output node, the fourteenth gate coupled to the fourth node, and the fourteenth source coupled to the reference ground.

In addition, the positive input signal and the negative input signal are provided by a shift register (120), and the shift register generates the positive input signal and the negative input signal according to a display data (DIN) provided by a timing control unit (110).

Based on the above description, the present invention further provides a display. Please refer to Figure 4, which shows a block diagram of an embodiment of a display according to the present invention. As shown in Figure 4, a display 200 includes a display panel 210 and a source driver circuit 220 for driving the display panel 210. The source driver circuit 220 has multiple output channels 221, each of which has a potential conversion circuit implemented by the potential conversion circuit 100.

In addition, the display 200 may be a liquid crystal display, a sub-millimeter diode light-emitting display, a micron diode light-emitting display, a quantum dot diode light-emitting display, or an organic light-emitting diode display.

In addition, based on the above description, the present invention further provides an information processing device. Please refer to Figure 5, which shows a block diagram of an embodiment of the information processing device of the present invention. As shown in Figure 5, an information processing device 300 includes a central processing unit 310 and a display 320. The display 320 is implemented by the display 200, and the central processing unit 310 is used to communicate with the display 320.

In addition, the information processing device 300 may be a portable computer, a car computer, a smart watch, a smart bracelet, a smart phone, VR glasses, or AR glasses.

Based on the above design, the present invention has the following advantages: 1. The potential conversion circuit of the present invention ensures that the PMOS transistor of the output inverter is turned off when the output voltage is low, thereby minimizing the leakage current of the output inverter and optimizing the power consumption specification of the source drive circuit; 2. The source drive circuit of the present invention can optimize its power consumption specification by using the above-mentioned potential conversion circuit; and 3. The display of the present invention can optimize its power consumption specification by using the above-mentioned source drive circuit.

The invention disclosed in this case is a preferred embodiment. Any partial changes or modifications that are derived from the technical concept of this case and are easily inferred by those skilled in the art do not deviate from the scope of the patent rights of this case.

In summary, this case demonstrates significant differences from known technologies in terms of purpose, means, and effects. Furthermore, its first invention is practical and truly meets the patent requirements for invention. We sincerely request the Review Commission to carefully examine this matter and grant a patent to this invention as soon as possible to benefit society. This is our utmost prayer.

100: Potential conversion circuit

101a: PMOS transistor

101b: PMOS transistor

102a: PMOS transistor

102b: PMOS transistor

103a: PMOS transistor

103b: PMOS transistor

104a: NMOS transistor

104b: NMOS transistor

105a: NMOS transistor

105b: NMOS transistor

106a: PMOS transistor

106b: PMOS transistor

107a: PMOS transistor

107b: NMOS transistor

110: Timing control unit

120: Shift register

Claims (9)

A potential conversion circuit comprises: a first PMOS transistor and a second PMOS transistor, wherein the first PMOS transistor has a first source, a first gate, and a first drain, the first source being coupled to a positive supply voltage, and the first gate being coupled to a first node; and the second PMOS transistor has a second source, a second gate, and a second drain, the second source being coupled to the positive supply voltage, and the second gate being coupled to a second node. a third PMOS transistor and a fourth PMOS transistor, wherein the third PMOS transistor has a third source, a third gate, and a third drain, the third source being coupled to the first drain, the third gate being coupled to the second node, and the third drain being coupled to the first node; and the fourth PMOS transistor has a fourth source, a fourth gate, and a fourth drain, the fourth source being coupled to the second drain, the fourth gate being coupled to the first node, and the fourth drain being coupled to the second node; a fifth PMOS transistor and a sixth PMOS transistor, wherein the fifth PMOS transistor has a fifth source, a fifth gate, and a fifth drain, the fifth source being coupled to the first node, the fifth gate being coupled to a third node, and the fifth drain being coupled to the third node; and the sixth PMOS transistor has a sixth source, a sixth gate, and a sixth drain, the sixth source being coupled to the second node, the sixth gate being coupled to a fourth node, and the sixth drain being coupled to the fourth node; a first NMOS transistor and a second NMOS transistor, wherein the first NMOS transistor has a seventh drain, a seventh gate, and a seventh source, the seventh drain being coupled to the third node, and the seventh gate being coupled to a first DC voltage; and the second NMOS transistor has an eighth drain, an eighth gate, and an eighth source, the eighth drain being coupled to the fourth node, and the eighth gate being coupled to the first DC voltage; a third NMOS transistor and a fourth NMOS transistor, wherein the third NMOS transistor has a ninth drain, a ninth gate, and a ninth source, the ninth drain being coupled to the seventh source, the ninth gate being coupled to a negative input signal, and the ninth source being coupled to a reference ground; and the fourth NMOS transistor has a tenth drain, a tenth gate, and a tenth source, the tenth drain being coupled to the eighth source, the tenth gate being coupled to a positive input signal, and the tenth source being coupled to the reference ground; a seventh PMOS transistor and an eighth PMOS transistor, wherein the seventh PMOS transistor has an eleventh source, an eleventh gate, and an eleventh drain, the eleventh source being coupled to the positive supply voltage, the eleventh gate being coupled to a second DC voltage, and the eleventh drain being coupled to the third source; and the eighth PMOS transistor having a twelfth source, a twelfth gate, and a twelfth drain, the twelfth source being coupled to the positive supply voltage, the twelfth gate being coupled to the second DC voltage, and the twelfth drain being coupled to the fourth source; and An output-stage PMOS transistor and an output-stage NMOS transistor, wherein the output-stage PMOS transistor has a thirteenth source, a thirteenth gate, and a thirteenth drain, the thirteenth source coupled to the positive supply voltage, the thirteenth gate coupled to the second node, and the thirteenth drain coupled to an output node; and the output-stage NMOS transistor has a fourteenth drain, a fourteenth gate, and a fourteenth source, the fourteenth drain coupled to the output node, the fourteenth gate coupled to the fourth node, and the fourteenth source coupled to the reference ground. The potential conversion circuit as described in claim 1, wherein the positive input signal and the negative input signal are provided by a shift register, and the shift register generates the positive input signal and the negative input signal according to a display data provided by a timing control unit. A source-driven circuit has multiple output channels, each of which has a potential conversion circuit. The potential conversion circuit comprises: a first PMOS transistor and a second PMOS transistor, wherein the first PMOS transistor has a first source, a first gate, and a first drain, the first source being coupled to a positive supply voltage, and the first gate being coupled to a first node; and the second PMOS transistor has a second source, a second gate, and a second drain, the second source being coupled to the positive supply voltage, and the second gate being coupled to a second node. a third PMOS transistor and a fourth PMOS transistor, wherein the third PMOS transistor has a third source, a third gate, and a third drain, the third source being coupled to the first drain, the third gate being coupled to the second node, and the third drain being coupled to the first node; and the fourth PMOS transistor has a fourth source, a fourth gate, and a fourth drain, the fourth source being coupled to the second drain, the fourth gate being coupled to the first node, and the fourth drain being coupled to the second node; a fifth PMOS transistor and a sixth PMOS transistor, wherein the fifth PMOS transistor has a fifth source, a fifth gate, and a fifth drain, the fifth source being coupled to the first node, the fifth gate being coupled to a third node, and the fifth drain being coupled to the third node; and the sixth PMOS transistor has a sixth source, a sixth gate, and a sixth drain, the sixth source being coupled to the second node, the sixth gate being coupled to a fourth node, and the sixth drain being coupled to the fourth node; a first NMOS transistor and a second NMOS transistor, wherein the first NMOS transistor has a seventh drain, a seventh gate, and a seventh source, the seventh drain being coupled to the third node, and the seventh gate being coupled to a first DC voltage; and the second NMOS transistor has an eighth drain, an eighth gate, and an eighth source, the eighth drain being coupled to the fourth node, and the eighth gate being coupled to the first DC voltage; a third NMOS transistor and a fourth NMOS transistor, wherein the third NMOS transistor has a ninth drain, a ninth gate, and a ninth source, the ninth drain being coupled to the seventh source, the ninth gate being coupled to a negative input signal, and the ninth source being coupled to a reference ground; and the fourth NMOS transistor has a tenth drain, a tenth gate, and a tenth source, the tenth drain being coupled to the eighth source, the tenth gate being coupled to a positive input signal, and the tenth source being coupled to the reference ground; a seventh PMOS transistor and an eighth PMOS transistor, wherein the seventh PMOS transistor has an eleventh source, an eleventh gate, and an eleventh drain, the eleventh source being coupled to the positive supply voltage, the eleventh gate being coupled to a second DC voltage, and the eleventh drain being coupled to the third source; and the eighth PMOS transistor having a twelfth source, a twelfth gate, and a twelfth drain, the twelfth source being coupled to the positive supply voltage, the twelfth gate being coupled to the second DC voltage, and the twelfth drain being coupled to the fourth source; and An output-stage PMOS transistor and an output-stage NMOS transistor, wherein the output-stage PMOS transistor has a thirteenth source, a thirteenth gate, and a thirteenth drain, the thirteenth source coupled to the positive supply voltage, the thirteenth gate coupled to the second node, and the thirteenth drain coupled to an output node; and the output-stage NMOS transistor has a fourteenth drain, a fourteenth gate, and a fourteenth source, the fourteenth drain coupled to the output node, the fourteenth gate coupled to the fourth node, and the fourteenth source coupled to the reference ground. The source drive circuit as described in claim 3, wherein the positive input signal and the negative input signal are provided by a shift register, and the shift register generates the positive input signal and the negative input signal according to a display data provided by a timing control unit. A display includes a display panel and a source drive circuit for driving the display panel. The source drive circuit has multiple output channels, each of which has a potential conversion circuit. The potential conversion circuit comprises: a first PMOS transistor and a second PMOS transistor, wherein the first PMOS transistor has a first source, a first gate, and a first drain, the first source being coupled to a positive supply voltage, and the first gate being coupled to a first node; and the second PMOS transistor has a second source, a second gate, and a second drain, the second source being coupled to the positive supply voltage, and the second gate being coupled to a second node. a third PMOS transistor and a fourth PMOS transistor, wherein the third PMOS transistor has a third source, a third gate, and a third drain, the third source being coupled to the first drain, the third gate being coupled to the second node, and the third drain being coupled to the first node; and the fourth PMOS transistor has a fourth source, a fourth gate, and a fourth drain, the fourth source being coupled to the second drain, the fourth gate being coupled to the first node, and the fourth drain being coupled to the second node; a fifth PMOS transistor and a sixth PMOS transistor, wherein the fifth PMOS transistor has a fifth source, a fifth gate, and a fifth drain, the fifth source being coupled to the first node, the fifth gate being coupled to a third node, and the fifth drain being coupled to the third node; and the sixth PMOS transistor has a sixth source, a sixth gate, and a sixth drain, the sixth source being coupled to the second node, the sixth gate being coupled to a fourth node, and the sixth drain being coupled to the fourth node; a first NMOS transistor and a second NMOS transistor, wherein the first NMOS transistor has a seventh drain, a seventh gate, and a seventh source, the seventh drain being coupled to the third node, and the seventh gate being coupled to a first DC voltage; and the second NMOS transistor has an eighth drain, an eighth gate, and an eighth source, the eighth drain being coupled to the fourth node, and the eighth gate being coupled to the first DC voltage; a third NMOS transistor and a fourth NMOS transistor, wherein the third NMOS transistor has a ninth drain, a ninth gate, and a ninth source, the ninth drain being coupled to the seventh source, the ninth gate being coupled to a negative input signal, and the ninth source being coupled to a reference ground; and the fourth NMOS transistor has a tenth drain, a tenth gate, and a tenth source, the tenth drain being coupled to the eighth source, the tenth gate being coupled to a positive input signal, and the tenth source being coupled to the reference ground; a seventh PMOS transistor and an eighth PMOS transistor, wherein the seventh PMOS transistor has an eleventh source, an eleventh gate, and an eleventh drain, the eleventh source being coupled to the positive supply voltage, the eleventh gate being coupled to a second DC voltage, and the eleventh drain being coupled to the third source; and the eighth PMOS transistor having a twelfth source, a twelfth gate, and a twelfth drain, the twelfth source being coupled to the positive supply voltage, the twelfth gate being coupled to the second DC voltage, and the twelfth drain being coupled to the fourth source; and An output-stage PMOS transistor and an output-stage NMOS transistor, wherein the output-stage PMOS transistor has a thirteenth source, a thirteenth gate, and a thirteenth drain, the thirteenth source coupled to the positive supply voltage, the thirteenth gate coupled to the second node, and the thirteenth drain coupled to an output node; and the output-stage NMOS transistor has a fourteenth drain, a fourteenth gate, and a fourteenth source, the fourteenth drain coupled to the output node, the fourteenth gate coupled to the fourth node, and the fourteenth source coupled to the reference ground. The display as described in claim 5, wherein the positive input signal and the negative input signal are provided by a shift register, and the shift register generates the positive input signal and the negative input signal according to display data provided by a timing control unit. The display as described in claim 5 is selected from the group consisting of a liquid crystal display, a sub-millimeter diode light-emitting display, a micron diode light-emitting display, a quantum dot diode light-emitting display and an organic light-emitting diode display. An information processing device having a central processing unit and a display as described in any one of claims 5 to 7, wherein the central processing unit is used to communicate with the display. The information processing device as described in claim 8 is selected from the group consisting of a portable computer, a car computer, a smart watch, a smart bracelet, a smart phone, VR glasses and AR glasses.