TWI885354B - Electronic package and manufacturing method thereof - Google Patents

Abstract

An electronic package is provided, in which electronic components and dummy chips are arranged on a carrier, and the electronic component and the dummy chip are encapsulated with an encapsulation layer, wherein the dummy chips are exposed from side edges of the encapsulation layer. Therefore, by increasing total volume of the dummy chips, the dummy chips can suppress warpage of the encapsulation layer after removal of the carrier.

Description

Electronic packaging and its manufacturing method

The present invention relates to a semiconductor device, in particular an electronic package and a method for manufacturing the same.

With the evolution of technology, the demand for electronic products is moving towards heterogeneous integration. For this reason, multi-chip module (MCM or MCP) is gradually emerging.

The semiconductor package 1 shown in FIG1A is manufactured by bonding a plurality of semiconductor chips 11 to a carrier 8 (as shown in FIG1B ), and then encapsulating the semiconductor chips 11 with a packaging gel 15. Then, the carrier 8 is removed, and a circuit structure 16 is formed on the packaging gel 15, so that the circuit structure 16 is electrically connected to the semiconductor chips 11. Afterwards, the circuit structure 16 is disposed on a packaging substrate 10 through a plurality of conductive elements 17, and the packaging substrate 10 can be connected to a circuit board (not shown) through a plurality of solder balls 19. By packaging multiple semiconductor chips 11 into a single structure, it has more I/Os, can greatly increase the computing power of the processor, and reduce the delay time of signal transmission, so as to be applied to high-end products with high-density lines/high transmission speeds/high stacking numbers/large-size designs.

During the packaging process, the carrier 8 is a wafer form layout. The packaging colloid 15 is prone to warpage due to its large coefficient of thermal expansion (CTE), which causes the carrier 8 to warp and cause the edge of the carrier 8 to break. Therefore, the industry configures a dummy chip 18 on the empty area of the carrier 8 to occupy the surface area of the carrier 8, reduce the amount of the packaging colloid 15, and thereby reduce the degree of warpage.

Furthermore, the packaging glue 15 needs to provide the amount in the packaging area A as shown in FIG. 1B through the molding operation, so the packaging glue 15 will completely cover the side surface 18c of the dummy chip 18, wherein the packaging glue 15 is filled in the space between each semiconductor chip 11 (such as the cutting line L), the space between the semiconductor chip 11 and the dummy chip 18 (such as the cutting line L) and the edge of the packaging area A.

However, after the carrier 8 is removed, the overall structure cannot suppress the warping of the packaging colloid 15 due to thinning, causing the packaging colloid 15 to break at the edge of the packaging area A, and even making it impossible to perform the subsequent process of the circuit structure 16.

Furthermore, since the dummy chip 18 cannot fully fill the edge contour of the carrier 8, the amount of the packaging colloid 15 used in the packaging area A is limited. Therefore, even if the dummy chip 18 is configured, the warping degree of the packaging colloid 15 cannot be suppressed after the carrier 8 is removed.

Therefore, how to overcome the above-mentioned problems of knowledge and technology has become an urgent issue to be solved.

In view of the various deficiencies of the above-mentioned prior art, the present invention provides an electronic package, which includes: a coating layer; an electronic component embedded in the coating layer, wherein the electronic component has an opposite active surface and an inactive surface; and a dummy chip embedded in the coating layer in a manner of spacing the electronic component so that the dummy chip is exposed on the side surface of the coating layer.

The present invention also provides a method for manufacturing an electronic package, which includes: placing an electronic component and a dummy chip on a carrier, wherein the electronic component has an active surface and an inactive surface opposite to each other, so that the electronic component is bonded to the carrier with its inactive surface, and the dummy chip is placed on the edge of the carrier in a manner of spacing the electronic component; forming a coating layer on the carrier, so that the coating layer covers the electronic component and the dummy chip, and the dummy chip is exposed on the side surface of the coating layer; and removing the carrier.

In the aforementioned electronic package and its manufacturing method, the electronic component is provided with a plurality of conductive bodies on its active surface.

In the aforementioned electronic package and its manufacturing method, the electronic package includes a plurality of dummy chips and a plurality of electronic components, and the plurality of dummy chips surround the plurality of electronic components.

The aforementioned electronic package and its manufacturing method further include forming a circuit structure on the coating layer so that the circuit structure is electrically connected to the electronic component. For example, the circuit structure is not electrically connected to the dummy chip.

In the aforementioned electronic package and its manufacturing method, part of the edge profile of the dummy chip is the same as the edge profile of the carrier.

The aforementioned electronic package and its manufacturing method further include providing a plurality of electronic components as a chipset, and then placing the chipset and the dummy chip on the carrier. For example, the chipset further includes a packaging layer that encapsulates the plurality of electronic components.

As can be seen from the above, in the electronic package and its manufacturing method of the present invention, the overall volume of the dummy chip is increased mainly by exposing the side surface of the coating layer of the dummy chip to reduce the amount of the coating layer. Therefore, compared with the prior art, the present invention can effectively prevent the coating layer from warping.

1:Semiconductor packages

10:Packaging substrate

11: Semiconductor chip

15: Packaging colloid

16,26: Line structure

17,27: Conductive components

18,28,38: Virtual chips

18c, 25c, 28c: Side

19,42: Shot

2,2a,2b,3,5,6: Electronic packaging

20,8: Carrier

200: Release layer

201: Dielectric protective layer

21,51: Electronic components

21a: Action surface

21b: Non-active surface

210:Electrode pad

211: Conductor

25: Coating layer

25a: First surface

25b: Second surface

260: Dielectric layer

261: Line layer

262: Electrical contact pad

28a: Surface

30: Wafer structure

40: Electronic devices

5a,6a: Chipset

60: Packaging layer

91: First bonding layer

92: Second bonding layer

A: Packaging area

L: Cutting path

S0,S1: edge contour

h1,h2: height

FIG1A is a schematic cross-sectional view of a conventional semiconductor package.

FIG. 1B is a top view schematic diagram of the process status of a conventional semiconductor package.

Figures 2A to 2D are cross-sectional schematic diagrams of the manufacturing method of the first embodiment of the electronic package of the present invention.

Figures 2A-1 to 2A-2 are top views of the manufacturing process of Figure 2A.

Figure 2B-1 is a schematic diagram of Figure 2B from above.

FIG3 is a cross-sectional schematic diagram of another implementation of FIG2D.

FIG4 is a cross-sectional schematic diagram of the subsequent process of FIG2D.

FIG5 is a cross-sectional schematic diagram of the manufacturing method of the second embodiment of the electronic package of the present invention.

FIG6 is a cross-sectional schematic diagram of another implementation of FIG5.

The following is a specific and concrete example to illustrate the implementation of the present invention. People familiar with this technology can easily understand other advantages and effects of the present invention from the content disclosed in this manual.

It should be noted that the structures, proportions, sizes, etc. depicted in the drawings attached to this specification are only used to match the contents disclosed in the specification for understanding and reading by people familiar with this technology, and are not used to limit the restrictive conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "above", "first", "second" and "one" used in this specification are only used to facilitate the clarity of the description, and are not used to limit the scope of the implementation of the present invention. The changes or adjustments in their relative relationships shall also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

Figures 2A to 2D are cross-sectional schematic diagrams of the manufacturing method of the first embodiment of the electronic package of the present invention.

As shown in FIG2A , a plurality of electronic components 21 are disposed on a carrier 20 via a first bonding layer 91, and at least one dummy die 28 is disposed on the carrier 20 via a second bonding layer 92 (as shown in FIG2A-2 , a plurality of electronic components 21 and a plurality of dummy chips 28 are disposed on the carrier 20), wherein the height h1 of the electronic component 21 relative to the carrier 20 is equal to or less than the height h2 of the dummy chip 28 relative to the carrier 20.

The carrier 20 can be made of a metal plate or a semiconductor plate (such as a wafer or a glass plate). In this embodiment, the edge profile S0 of the carrier 20 is circular, and a release layer 200 and a dielectric protective layer 201 can be sequentially formed on its surface.

The electronic component 21 is an active component, a passive component or a combination of the two, and the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor.

In this embodiment, the electronic component 21 is a single semiconductor chip, and its substrate body has an active surface 21a and an inactive surface 21b opposite to each other. The active surface 21a has a plurality of electrode pads 210, and the electronic component 21 is bonded to the dielectric protection layer 201 of the carrier 20 through the first bonding layer 91 with its inactive surface 21b, and a plurality of bump-shaped conductors 211 are bonded to the plurality of electrode pads 210.

Furthermore, an insulating layer (not shown) covering the plurality of conductors 211 may be formed on the active surface 21a so that the top surface of the insulating layer and the end surface of the conductor 211 are flush with each other, so that the conductor 211 is exposed from the insulating layer. For example, the material forming the insulating layer is polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

The dummy chip 28 is a semiconductor material block without the function of transmitting signals, and part of its edge profile S1 is the same as the edge profile S0 of the carrier 20.

In this embodiment, the substrate body of the electronic component 21 and the dummy chip 28 are made by using a wafer of the same size. For example, the dummy chip 28 is made by cutting a wafer structure 30, as shown in FIG. 2A-1, and removing the dummy chip 38 corresponding to the electronic component 21, so as to select the remaining dummy chip 28 and place it on the carrier 20, so that the partial edge profile S1 of the dummy chip 28 on the carrier 20 corresponds to the edge profile S0 of the carrier 20, so that the overall outer peripheral profile of the dummy chips 28 is like a circle. It should be understood that the substrate body of the electronic component 21 forms the conductors 211 in the subsequent process, and the dummy chip 28 does not need to make the conductors 211.

Therefore, since the wafer structure 30 and the carrier 20 have the same shape and area, when the dummy chips 28 are arranged at the edge of the carrier 20 according to their positions on the wafer structure 30, as shown in FIG. 2A-2, the dummy chips 28 can be arranged corresponding to the edge profile S0 of the carrier 20.

In addition, the first bonding layer 91 and the second bonding layer 92 are both in the form of a die attach film (DAF), but there is no special limitation.

As shown in FIG. 2B , a coating layer 25 is formed on the carrier 20 to cover the electronic component 21 and the dummy chip 28 so as to obtain the electronic package 2, and the dummy chip 28 is exposed on the side surface 25c of the coating layer 25 (as shown in FIG. 2B-1 ).

In this embodiment, the coating layer 25 has a first surface 25a and a second surface 25b opposite to each other, and the coating layer 25 is bonded to the dielectric protection layer 201 of the carrier 20 with its second surface 25b. For example, the coating layer 25 is an insulating material, such as an encapsulation resin of epoxy resin, which can be formed on the carrier 20 by lamination or molding.

Furthermore, by a flattening process, such as grinding, part of the material of the first surface 25a of the cladding layer 25 is removed, so that the first surface 25a of the cladding layer 25 is flush with the end surface of the conductor 211 and the surface 28a of the dummy chip 28, so that the conductor 211 and the dummy chip 28 are exposed on the first surface 25a of the cladding layer 25.

Furthermore, the dummy chips 28 are arranged corresponding to the edge profile S0 of the carrier 20, so that when the encapsulation layer 25 is formed in the packaging area A as shown in FIG. 2A-2, the side surface 28c of the dummy chip 28 is exposed to the side surface 25c of the encapsulation layer 25, wherein the packaging colloid 15 is filled in the space between each of the electronic components 21 (such as the cutting line L shown in FIG. 2A-2), the space between each of the dummy chips 28 (such as the cutting line L shown in FIG. 2A-2), and the space between the electronic component 21 and the dummy chip 28 (such as the cutting line L shown in FIG. 2A-2).

It should be understood that since the dummy chips 28 can be arranged corresponding to the edge profile S0 of the carrier 20, so that the dummy chips 28 are distributed all over the edge of the packaging area A, the area of the empty area on the surface of the carrier 20 can be greatly reduced, so that the coating layer 25 only occupies the cutting lane L and its usage can be greatly reduced.

As shown in FIG. 2C , the carrier 20 and the release layer 200 and dielectric protective layer 201 thereon are removed to form another electronic package 2a.

As shown in FIG. 2D , a circuit structure 26 is formed on the first surface 25a of the coating layer 25, and the circuit structure 26 is electrically connected to the conductor 211 to form another electronic package 2b.

In this embodiment, the circuit structure 26 includes a plurality of dielectric layers 260 and a plurality of circuit layers 261 disposed on the plurality of dielectric layers 260 and electrically connected to the conductors 211, such as a circuit redistribution layer (RDL) specification. For example, the material forming the circuit layer 261 is copper, and the material forming the dielectric layer 260 is polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

Furthermore, a flattening process can be performed as required. As shown in FIG3 , the first bonding layer 91 and the second bonding layer 92 are removed by grinding, so that the inactive surface 21b of the electronic component 21 and the surface of the dummy chip 28 are flush with the second surface 25b of the encapsulation layer 25, so that the inactive surface 21b of the electronic component 21 and the surface of the dummy chip 28 are exposed on the second surface 25b of the encapsulation layer 25, so as to obtain an electronic package 3 with a thinner thickness.

In addition, the circuit structure 26 may have a plurality of electrical contact pads 262 exposed from the dielectric layer 260 on the outermost circuit layer 261 to combine with a conductive element 27 such as a copper column or a solder ball, so as to be subsequently connected with an electronic device 40 such as a package structure, a circuit board or a chip, as shown in FIG4. For example, the package substrate serves as the electronic device 40, and a plurality of solder balls 42 may be arranged on the lower side of the package substrate to combine with the circuit board.

In addition, the circuit structure 26 does not need to be electrically connected to the dummy chip 28 because no signal is transmitted to the dummy chip 28.

Therefore, the manufacturing method of the present invention mainly makes the edge profile S1 of the dummy chip 28 the same as the edge profile S0 of the carrier 20, so that the dummy chip 28 almost covers the edge of the packaging area A, that is, the encapsulation layer 25 only occupies the area of the cutting line L of the packaging area A, so that after the encapsulation layer 25 is formed, the dummy chip 28 exposes the side surface 25c of the encapsulation layer 25. Therefore, compared with the prior art, the present invention reduces the volume proportion of the encapsulation layer 25 in the packaging area A, so as to effectively reduce the degree of warping caused by the CTE mismatch between the encapsulation layer 25 and the electronic component 21.

Furthermore, since the dummy chip 28 is distributed all over the edge of the package area A, the overall volume of the dummy chip 28 is increased, so that after the carrier 20 is removed, the warping of the coating layer 25 caused by the larger coefficient of thermal expansion (CTE) can be effectively suppressed. Therefore, compared with the conventional technology, the internal stress of the coating layer 25 can be greatly dispersed into the dummy chip 28 to prevent the coating layer 25 from warping.

Furthermore, when the size of the carrier 20 is larger, the curvature of the cladding layer 25 will not increase due to the configuration of the plurality of dummy chips 28 corresponding to the edge profile S0 of the carrier 20. Therefore, when manufacturing the circuit structure 26, the electrical connection between the circuit layer 261 and the conductor 211 of the electronic component 21 can be effectively connected, thereby avoiding problems such as low yield and poor product reliability, thereby reducing costs and improving productivity.

In addition, the manufacturing method of the present invention can use existing materials and old processes and machines without adding new processes and materials or purchasing new equipment. Therefore, the manufacturing method of the present invention can effectively control the process cost, making the electronic packaging parts 2, 2a, 2b, 3 of the present invention economically efficient.

FIG5 is a cross-sectional schematic diagram of the manufacturing method of the second embodiment of the electronic package 5 of the present invention. The difference between this embodiment and the first embodiment lies in the size of the electronic components. The other processes are roughly the same, so the similarities will not be described in detail below.

As shown in FIG5, in the process shown in FIG2A, a smaller electronic component 51 is used to arrange a plurality of electronic components 51 in the original layout area of the electronic component 21, as shown in FIG2A-2, to serve as a chip set 5a. Afterwards, a coating layer 25 is formed on the carrier 20 to cover the chip set 5a and the dummy chip 28, so as to obtain the electronic package 5.

In this embodiment, the structure of the electronic component 51 with a smaller width is the same as the structure of the electronic component 21 with a larger width.

Furthermore, in another embodiment, as shown in FIG. 6 , the chip set 6a of the electronic package 6 may also firstly encapsulate the electronic components 51 with the encapsulation layer 60, and then the chip set 6a is bonded to the dielectric protection layer 201 of the carrier 20 through the first bonding layer 91. For example, the encapsulation layer 60 is an insulating material, such as an encapsulation colloid of epoxy resin, which may be the same as or different from the composition of the encapsulation layer 25.

The present invention further provides an electronic package 2, 2a, 2b, 3, 5, 6, comprising: a coating layer 25, at least one electronic component 21, 51, and at least one dummy chip 28.

The electronic components 21, 51 are embedded in the coating layer 25, wherein the electronic components 21, 51 have opposite active surfaces 21a and inactive surfaces 21b.

The dummy chip 28 is embedded in the encapsulation layer 25 in a manner that the electronic components 21, 51 are spaced apart, and the dummy chip 28 is exposed on the side surface 25c of the encapsulation layer 25.

In one embodiment, the electronic element 21, 51 is provided with a plurality of conductive bodies 211 on its active surface 21a.

In one embodiment, the electronic package 2, 2a, 2b, 3, 5, 6 includes a plurality of dummy chips 28 and a plurality of electronic components 21, 51, and the plurality of dummy chips 28 surround the plurality of electronic components 21.

In one embodiment, the electronic package 2b further includes a circuit structure 26 disposed on the encapsulation layer 25 to electrically connect the electronic element 21. For example, the circuit structure 26 is not electrically connected to the dummy chip 28.

In one embodiment, the electronic package 2 further includes a carrier 20 disposed on the coating layer 25, which carries the electronic components 21, 51 and the dummy chip 28, and a portion of the edge profile S1 of the dummy chip 28 is the same as the edge profile S0 of the carrier 20.

In one embodiment, the encapsulation layer 25 embeds a plurality of the electronic components 21 so that the plurality of the electronic components 21 serve as a chipset 5a, 6a. For example, the chipset 6a further includes a packaging layer 60 encapsulating the plurality of electronic components 51.

In summary, the electronic package and its manufacturing method of the present invention increases the overall volume of the dummy chip by exposing the side of the coating layer of the dummy chip, thereby reducing the amount of the coating layer used. Therefore, the present invention can effectively prevent the coating layer from warping.

The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Anyone familiar with this technology can modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application described below.

20: Carrier

21: Electronic components

25: Coating layer

25c,28c: Side

28: Virtual chip

S0,S1: edge contour

Claims (16)

An electronic package includes: Coating layer; An electronic component is embedded in the coating layer, wherein the electronic component has an active surface and an inactive surface opposite to each other; and The dummy chip is embedded in the encapsulation layer in a manner that separates the electronic components, and the dummy chip is exposed on the side surface of the encapsulation layer. An electronic package as described in claim 1, wherein the electronic component is provided with a plurality of conductors on its active surface. The electronic package as described in claim 1, wherein the electronic package comprises a plurality of the dummy chips and a plurality of the electronic components, and the plurality of the dummy chips surround the plurality of the electronic components. The electronic package as described in claim 1 further includes a circuit structure disposed on the coating layer to electrically connect the electronic component. An electronic package as described in claim 4, wherein the circuit structure is not electrically connected to the dummy chip. The electronic package as described in claim 1 further includes a carrier disposed on the coating layer, which carries the electronic component and the dummy chip, and a portion of the edge contour of the dummy chip is the same as the edge contour of the carrier. An electronic package as described in claim 1, wherein a plurality of electronic components are embedded in the encapsulation layer so that the plurality of electronic components serve as a chip set. An electronic package as described in claim 7, wherein the chip assembly includes a packaging layer encapsulating the plurality of electronic components. A method for manufacturing an electronic package includes: The electronic component and the dummy chip are arranged on a carrier, the electronic component has an active surface and an inactive surface opposite to each other, the electronic component is bonded to the carrier with its inactive surface, and the dummy chip is arranged on the edge of the carrier in a manner of spacing the electronic component; Forming a coating layer on the carrier so that the coating layer covers the electronic component and the dummy chip, and the dummy chip is exposed on the side of the coating layer; and Remove the carrier. A method for manufacturing an electronic package as described in claim 9, wherein the electronic component is provided with a plurality of conductors on its active surface. A method for manufacturing an electronic package as described in claim 9, wherein the plurality of dummy chips and the plurality of electronic components are disposed on the carrier, and the plurality of dummy chips surround the plurality of electronic components. The method for manufacturing an electronic package as described in claim 9 further includes forming a circuit structure on the coating layer so that the circuit structure is electrically connected to the electronic component. A method for manufacturing an electronic package as described in claim 12, wherein the circuit structure is not electrically connected to the dummy chip. A method for manufacturing an electronic package as described in claim 9, wherein a portion of the edge profile of the dummy chip is the same as the edge profile of the carrier. The method for manufacturing an electronic package as described in claim 9 further includes providing a plurality of the electronic components as a chipset, and then placing the chipset and the dummy chip on the carrier. A method for manufacturing an electronic package as described in claim 15, wherein the chip assembly includes a packaging layer encapsulating the plurality of electronic components.

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