TWI884561B - Semiconductor substrate and manufacturing method thereof - Google Patents

Abstract

A semiconductor substrate includes a first circuit structure and a second circuit structure. The first circuit structure includes a first wiring layer. The first wiring layer includes a first dielectric layer. The second circuit structure includes a second wiring layer. The second wiring layer includes a second dielectric layer. The second circuit structure is disposed on the first circuit structure and is electrically connected to the first circuit structure to form the semiconductor substrate. A manufacturing method of the semiconductor substrate is also provided.

Description

Semiconductor substrate and method for manufacturing the same

The present invention relates to a semiconductor substrate and a manufacturing method thereof.

Generally speaking, semiconductor substrates often need to use multi-layer circuit structures to meet product requirements. However, when the materials in the multi-layer circuit structure are different, it is easy to cause a mismatch in the coefficient of thermal expansion (CTE), and as the number of layers increases, stress will also accumulate. Therefore, in the process of sequentially forming film layers in the substrate (forming at least four layers in a row), it is easy to cause the semiconductor substrate to warp. The more layers there are, the more obvious the warp problem will be. As a result, it will have an adverse effect on the yield of the semiconductor substrate and the electrical performance in subsequent applications (such as causing the failure of the chip solder joints subsequently bonded thereto).

The present invention provides a semiconductor substrate which can maintain a good yield while having a multi-layer circuit structure and improve the electrical performance in subsequent applications.

A semiconductor substrate of the present invention includes a first circuit structure and a second circuit structure. The first circuit structure includes a first circuit layer. The first circuit layer includes a first dielectric layer. The second circuit structure includes a second circuit layer. The second circuit layer includes a second dielectric layer. The second circuit structure is arranged on the first circuit structure and electrically connected to the first circuit structure to form a semiconductor substrate.

An electronic assembly of the present invention comprises the semiconductor substrate and at least one chip arranged on the semiconductor substrate.

The present invention discloses a method for manufacturing a semiconductor substrate, which comprises at least the following steps: forming a first circuit structure on a first carrier, wherein the first circuit structure comprises a first circuit layer, the first circuit layer comprises a plurality of first conductive patterns and a first dielectric layer; forming a second circuit structure on a second carrier, wherein the second circuit structure comprises a second circuit layer, the second circuit layer comprises a plurality of second conductive patterns and a second dielectric layer, one of the first carrier and the second carrier is a temporary carrier, and the other of the first carrier and the second carrier is a temporary carrier or a permanent carrier; and bonding the first circuit structure and the second circuit structure so that the first circuit structure and the second circuit structure are electrically connected to form a semiconductor substrate.

Based on the above, the present invention first manufactures multiple circuit structures separately and then assembles the aforementioned multiple circuit structures into a semiconductor substrate. In this way, compared with semiconductor substrates manufactured sequentially at one time, the degree of warping can be effectively reduced, so that the semiconductor substrate can maintain a better yield while having a multi-layer circuit structure and improve the electrical performance in subsequent applications.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

The following will refer to the drawings to fully describe the exemplary embodiments of the present invention, but the present invention can also be implemented in many different forms and should not be construed as being limited to the embodiments described herein. In the drawings, for the sake of clarity, the size and thickness of each region, part and layer may not be drawn according to the actual scale. For ease of understanding, the same elements in the following description will be described with the same symbols.

The present invention is more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or size of the layers or regions in the drawings may be exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

Directional terms used herein (eg, up, down, right, left, front, back, top, bottom) are used only with reference to the drawings and are not intended to imply an absolute orientation.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

Unless otherwise specified, the term "between" used in this specification to define a range of numerical values is intended to cover ranges equal to the endpoint values and between the endpoint values. For example, a size range is between a first value and a second value, which means that the size range can cover the first value, the second value, and any value between the first value and the second value.

FIG. 1A is a schematic diagram showing an assembly of a semiconductor substrate according to some embodiments of the present invention. FIG. 1B to FIG. 1E are partially schematic cross-sectional views showing a method for manufacturing a semiconductor substrate according to some embodiments of the present invention. FIG. 1F is a schematic diagram showing a semiconductor substrate according to some embodiments of the present invention when it is joined. FIG. 1G and FIG. 1H are partially schematic cross-sectional views showing an electronic assembly including a semiconductor substrate according to some embodiments of the present invention. FIG. 2 and FIG. 3 are partially schematic cross-sectional views showing alternative embodiments of the structure of FIG. 1D.

1A and 1B , a first circuit structure 110 including a plurality of first circuit layers 111 ( FIG. 1B schematically shows two layers) is formed on a first carrier 10, wherein in this embodiment, the first carrier 10 may be a temporary carrier made of glass, plastic, silicon, metal or other suitable materials, so the first carrier 10 may only have a bearing function without a wiring function and without active components and/or passive components, but the present invention is not limited thereto. Here, the first circuit structure 110 includes a top surface 110t and a bottom surface 110b opposite to each other, and the bottom surface 110b is closer to the first carrier 10 than the top surface 110t.

In the present embodiment, since the first carrier 10 is a temporary carrier, a release layer (such as a light-to-heat conversion film or other suitable release layer) (not shown) may be applied between the first carrier 10 and the first circuit structure 110 to enhance the releasability between the first carrier 10 and the first circuit structure 110 in subsequent processes and to improve the planarity of the first circuit structure 110, thereby enhancing the reliability of subsequent bonding, but the present invention is not limited thereto.

In some embodiments, each first circuit layer 111 may include a first conductive pattern 111a, a first dielectric layer 111b and/or a first conductive via 111c. Here, the first conductive pattern 111a and the first conductive via 111c may be embedded in the first dielectric layer 111b, but the present invention is not limited thereto.

In this embodiment, the first conductive via 111c gradually becomes thicker (such as the width or diameter gradually becomes thicker) in the direction away from the first carrier 10. In other words, the first conductive via 111c gradually becomes thinner (such as the width or diameter gradually becomes thinner) in the direction toward the first carrier 10, but the present invention is not limited thereto.

It should be noted that the first circuit structure 110 shown in FIG. 1B is only exemplary. According to different circuit design requirements, each first circuit layer 111 may have circuits not shown in the figure. For example, the first circuit layer 111 close to the first carrier 10 may be provided with conductive features that can be used to connect with other components. In addition, the first conductive pattern 111a, the first dielectric layer 111b and/or the first conductive via 111c may also be arranged at different positions.

In some embodiments, the first circuit structure 110 is of a back-end-of-line (BEOL) type (which can be used to connect multiple transistors), that is, the first circuit structure 110 is manufactured according to the back-end-of-line design rules, wherein based on the selection of the material of the first dielectric layer 111b (such as silicon nitride (Si ₃ N ₄ ), silicon oxide (SiO ₂ ) or other suitable inorganic materials), the thickness of the first dielectric layer 111b in the first circuit layer 111 is less than 1 micron to reduce the material stress therein and reduce the probability of cracking, but the present invention is not limited thereto.

In some embodiments, the back-end process design rule may be to use chemical and mechanical polishing processes, and the line width and line spacing of the copper wires are from about 0.2 microns to about 1 micron, but the present invention is not limited thereto.

In some embodiments, the first circuit structure 110 is a thin film distribution layers type (which can be used in an interposer), that is, the first circuit structure 110 is manufactured according to thin film distribution layers design rules, wherein based on the selection of the material of the first dielectric layer 111b (such as photo sensitive polyimide (PSPI), benzocyclobutene (BCB) or other suitable organic materials), the thickness of the first dielectric layer 111b in the first circuit layer 111 is between 1 micron and 10 microns to reduce the material stress inside it and reduce the probability of cracking, but the present invention is not limited to this.

In some embodiments, the thin film redistribution design rule may be to fabricate, for example, copper wires (first wiring layer 111) on dielectric materials such as photosensitive polyimide (first dielectric layer 111b), wherein the line width and line spacing of the copper wires range from about 1.5 microns to about 10 microns, but the present invention is not limited thereto.

In some embodiments, the first circuit structure 110 is a build-up substrate type, that is, the first circuit structure 110 is manufactured according to the build-up substrate design rules, wherein based on the selection of the material of the first dielectric layer 111b (such as including ABF material or ABF derivative material), the thickness of the first dielectric layer 111b in the first circuit layer 111 is between 8 microns and 30 microns, but the present invention is not limited to this.

In some embodiments, the build-up substrate design rule may be produced by vacuum pressing of ABF material, wherein the line width and line spacing of the copper conductive layer (first circuit layer 111) on the ABF material (first dielectric layer 111b) ranges from about 5 microns (um) to about 25 microns, but the present invention is not limited thereto.

In some embodiments, the first circuit structure 110 is of a printed circuit board (PCB) type, that is, the first circuit structure 110 is manufactured according to the printed circuit board design rules, wherein based on the selection of the material of the first dielectric layer 111b (such as a semi-cured film (prepreg, PP) or bismaleimide triazine (BT) with glass fiber as a filling material), the thickness of the first dielectric layer 111b in the first circuit layer 111 is between 15 microns and 60 microns to reduce the material stress inside it and reduce the probability of cracking, but the present invention is not limited to this.

In some embodiments, the printed circuit board design rules may be a PCB mass production process known to those skilled in the art, wherein the line width and line spacing of the copper wire (first circuit layer 111) on the dielectric layer (first dielectric layer 111b) thereof range from about 25 microns to 75 microns, but the present invention is not limited thereto.

In some embodiments, the materials of the first conductive patterns 111a and the first conductive vias 111c in the above-mentioned various types may include copper, gold, nickel, aluminum, platinum, tin, graphene, combinations thereof, alloys thereof or other suitable conductive materials, but the present invention is not limited thereto.

In some embodiments, a planarization process (e.g., a grinding process, a chemical mechanical polishing process, or a combination thereof) is performed on the top circuit layer 111 at the top surface 110t so that the top first conductive pattern 111a in the top circuit layer 111 is coplanar with the top surface of the top first dielectric layer 111b, wherein the first conductive pattern 111a exposed on the top surface 110t after the planarization process can be used to electrically connect to other circuit structures (e.g., the second circuit structure 120 in FIG. 1B ).

1A and 1C, a first circuit structure 120 including a plurality of second circuit layers 121 (FIG. 1C schematically shows two layers) is formed on a second carrier 20, wherein in this embodiment, the second carrier 20 may be a temporary carrier made of glass, plastic, silicon, metal or other suitable materials, so the second carrier 20 may only have a bearing function without a wiring function and without active components and/or passive components, but the present invention is not limited thereto. Here, the second circuit structure 120 includes a first surface 120t and a second surface 120b opposite to each other, and the second surface 120b is closer to the second carrier 20 than the first surface 120t.

In the present embodiment, since the second carrier 20 is a temporary carrier, a release layer (such as a light-to-heat conversion film or other suitable release layer) (not shown) may be applied between the second carrier 20 and the second circuit structure 120 to enhance the releasability between the second carrier 20 and the second circuit structure 120 in subsequent processes and to improve the planarity of the second circuit structure 120, thereby enhancing the reliability of subsequent bonding, but the present invention is not limited thereto.

In some embodiments, each second circuit layer 121 may include a second conductive pattern 121a, a second dielectric layer 121b and/or a second conductive via 121c. Here, the second conductive pattern 121a and the second conductive via 121c may be embedded in the second dielectric layer 121b, but the present invention is not limited thereto.

In this embodiment, the second conductive via 121c gradually becomes thicker (such as the width or diameter gradually becomes thicker) in the direction away from the second carrier 20. In other words, the second conductive via 121c gradually becomes thinner (such as the width or diameter gradually becomes thinner) in the direction toward the second carrier 20, but the present invention is not limited thereto.

It should be noted that the second circuit structure 120 shown in FIG. 1C is only exemplary. According to different circuit design requirements, each second circuit layer 121 may have circuits not shown in the figure. For example, the second circuit layer 121 close to the second carrier 20 may be provided with conductive features that can be used to connect with other components. In addition, the second conductive pattern 121a, the second dielectric layer 121b and/or the second conductive via 121c may also be arranged at different positions.

In some embodiments, the second circuit structure 120 is of the back-end process type, that is, the second circuit structure 120 is manufactured according to the back-end process design rules (similar to the above description, which will not be repeated here), wherein based on the selection of the material of the second dielectric layer 121b (such as silicon nitride, silicon oxide or other suitable inorganic materials), the thickness of the second dielectric layer 121b in the second circuit layer 121 is less than 1 micron to reduce the material stress inside it and reduce the probability of cracking, but the present invention is not limited to this.

In some embodiments, the second circuit structure 120 is a thin film redistribution type, that is, the second circuit structure 120 is manufactured according to thin film redistribution design rules (similar to the above description, which will not be repeated here), wherein based on the selection of the material of the second dielectric layer 121b (such as including photosensitive polyimide, benzocyclobutene or other suitable organic materials), the thickness of the second dielectric layer 121b in the second circuit layer 121 is between 1 micron and 10 microns to reduce the material stress inside it and reduce the probability of cracking, but the present invention is not limited to this.

In some embodiments, the second circuit structure 120 is a build-up substrate type, that is, the second circuit structure 120 is manufactured according to the build-up substrate design rules (similar to the above description, which will not be repeated here), wherein based on the selection of the material of the second dielectric layer 121b (such as including ABF material or ABF derivative material), the thickness of the second dielectric layer 121b in the second circuit layer 121 is between 8 microns and 30 microns to reduce the material stress inside it and reduce the probability of cracking, but the present invention is not limited to this.

In some embodiments, the second circuit structure 120 is of a printed circuit board (PCB) type, that is, the second circuit structure 120 is manufactured according to the printed circuit board design rules (similar to the above description, which will not be repeated here), wherein based on the selection of the material of the second dielectric layer 121b (such as a semi-cured film or bismaleimide triazine with glass fiber as a filling material), the thickness of the second dielectric layer 121b in the second circuit layer 121 is between 15 microns and 60 microns to reduce the material stress inside it and reduce the probability of cracking, but the present invention is not limited to this.

In some embodiments, the materials of the second conductive patterns 121a and the second conductive vias 121c in the above-mentioned various types may include copper, gold, nickel, aluminum, platinum, tin, combinations thereof, alloys thereof or other suitable conductive materials, but the present invention is not limited thereto.

It should be noted that the thickness of the dielectric layer described herein is the thickness of a single film layer. In addition, the spacing can be arranged from small to large in the order of back-end process type, thin film redistribution type, build-up substrate type, and printed circuit board type, wherein the spacing can be based on the smallest spacing among various types, but the present invention is not limited thereto.

In some embodiments, the spacing in the circuit layer may be, for example, the distance between the center points of two adjacent circuits or the distance between two adjacent pads. Therefore, the aforementioned spacing may be designed according to actual design requirements and the present invention is not limited thereto.

1A, 1D to 1E, the structure shown in FIG. 1C is flipped upside down, and the first circuit structure 110 and the second circuit structure 120 are joined to electrically connect the first circuit structure 110 and the second circuit structure 120. Then, in this embodiment, since the first carrier 10 and the second carrier 20 are both temporary carriers, the first carrier 10 and the second carrier 20 can be removed by a suitable method (such as applying external energy between the bottom surface of the circuit structure and the temporary carrier to peel off the release layer) to form a semiconductor substrate S1. Accordingly, in this embodiment, a plurality of circuit structures (such as the first circuit structure 110 and the second circuit structure 120) are first manufactured separately, and then the aforementioned plurality of circuit structures are assembled into a semiconductor substrate S1. In this way, compared with semiconductor substrates manufactured sequentially at one time, the degree of warping can be effectively reduced, so that the semiconductor substrate S1 can maintain a better yield while having a multi-layer circuit structure and improve the electrical performance in subsequent applications.

Furthermore, due to process limitations, the difficulty is positively correlated with the number of layers to be manufactured. Therefore, the more layers are to be manufactured, the higher the probability that the entire semiconductor substrate will be damaged during the manufacturing process, and the yield and cost issues cannot be effectively controlled. In this embodiment, the semiconductor substrate S1 is split into multiple groups of circuit structures with fewer layers and each is manufactured separately, thereby avoiding the problem of continuously stacking multiple layers and being unable to effectively control the yield and cost. In addition, due to the difference in the coefficient of thermal expansion (CTE), warping will occur, and the situation will become more serious when more layers are stacked. Therefore, when the semiconductor substrate is continuously manufactured at one time, the amplitude of the warping will accumulate and become larger and larger. In this embodiment, after the semiconductor substrate is disassembled into multiple groups of circuit structures (a first group of circuit structures 110 and a second group of circuit structures 120) are manufactured separately, one of the groups is turned upside down for bonding (the bonding plane can be subsequently made horizontal by applying pressure from top and bottom). In this way, the different warping directions of the upper and lower parts (that is, the warping direction of the first circuit structure 110 is opposite to the warping direction of the second circuit structure 120) can effectively offset the stress and thus alleviate the warping phenomenon, as shown in FIG. 1F.

In some embodiments, the size of the first circuit structure (such as the width from the left edge to the right edge of the figure) is the same as the size of the second circuit structure 120 (such as the width from the left edge to the right edge of the figure), so that the stress can be offset more evenly and the warp can be improved more significantly, but the present invention is not limited to this.

In some embodiments, the first circuit structure 110 and the second circuit structure 120 are of the same type. For example, the first circuit structure 110 and the second circuit structure 120 are both of a back-end process type, a thin film redistribution type, a build-up substrate type, or a printed circuit board type. However, the present invention is not limited thereto. The first circuit structure 110 and the second circuit structure 120 may also be of different types. For example, the first circuit structure 110 is of a back-end process type and the second circuit structure 120 is of a thin film redistribution type, the first circuit structure 110 is of a back-end process type and the second circuit structure 120 is of a build-up substrate type, the first circuit structure 110 is of a back-end process type and the second circuit structure 120 is of a printed circuit board type, and so on.

In some embodiments, when the line pitch/spacing (L/S) (e.g., line width) of the circuit is finer, the process requirements will be more stringent. Therefore, when the first circuit structure 110 and the second circuit structure 120 are of the back-end process type or the thin film redistribution type, the use of a method of joining and assembling multiple sets of circuit structures can have greater advantages in yield and electrical performance than a continuously formed structure, but the present invention is not limited to this.

Here, no matter the first circuit structure 110 and the second circuit structure 120 are of the same type or different types, they can have different thicknesses and circuit spacings according to actual design requirements. For example, as shown in FIG. 1G , the electronic packaging EP may include a semiconductor substrate S1, chips 101 (two are schematically shown, and there may be more than two, such as three or four) respectively arranged on opposite surfaces of the semiconductor substrate S1, and a plurality of external terminals 102, wherein the circuit spacing in the circuit structure close to the chip 101 may be smaller than the circuit spacing in the circuit structure close to the plurality of external terminals 102, that is, the semiconductor substrate S1 may include circuit structures with fine spacing and coarse spacing at the same time, so as to fan out the signal of the chip 101 to the plurality of external terminals 102, but the present invention is not limited thereto. In another embodiment, as shown in FIG. 1H , the electronic packaging EP2 may include a semiconductor substrate S1, an interposer 1, and a chip 101, wherein the interposer 1 is disposed between the semiconductor substrate S1 and the chip 101, and the interposer 1 may be of any suitable type, and the present invention is not limited thereto. Here, the semiconductor substrate S1 may be a combination of a thin film redistribution type and a build-up substrate type, and the semiconductor substrate S1 may also be replaced by a semiconductor substrate in any of the following embodiments, which will not be described in detail in the following.

In some embodiments, the chip 101 can be connected to the surface of the semiconductor substrate S1 by, for example, flip chip bonding. For example, the conductive bump 101a of the chip 101 can directly contact the surface circuit of the semiconductor substrate S1 to form an electrical connection, but the present invention is not limited thereto, and the chip 101 can also be bonded to the surface of the semiconductor substrate S1 by other appropriate methods. Here, the chip 101 can be a plurality of chips 101 that perform the same or different functions.

In some embodiments, the chip 101 is, for example, a logic chip, a memory chip, a three-dimensional integrated circuit (3DIC) chip (such as a high bandwidth memory chip), an XPU, an I/O, a CPO, and/or the like, wherein the 3DIC chip includes a plurality of layers stacked on each other and through silicon vias (TSVs) are formed to provide vertical electrical connections between the layers, but the present invention is not limited thereto. Here, the chip 101 may be in the form of a chiplet.

In some embodiments, an underfill 103 is formed on the surface of the semiconductor substrate S1 to fill a gap between the surface of the semiconductor substrate S1 and the chip 101, thereby enhancing the reliability of flip chip bonding, but the present invention is not limited thereto.

In some embodiments, the external terminal 102 may be a solder ball and may be formed using a ball implantation process to be placed on a surface of the semiconductor substrate S1 away from the chip 101, and a soldering process and a reflow process may be selectively performed to enhance adhesion between the external terminal 102 and the circuit on the surface of the semiconductor substrate S1, but the present invention is not limited thereto.

In some embodiments, no semiconductor element (such as an active element and/or a passive element) is included between the first circuit structure and the second circuit structure 120. In other words, the semiconductor substrate formed by the first circuit structure and the second circuit structure 120 only has a wiring function to reduce the size of the substrate, but the present invention is not limited to this.

It should be noted that the various implementations of the semiconductor substrate described in this article can be applied to this electronic package with similar rules, and will not be elaborated in the subsequent description.

In this embodiment, the first circuit structure 110 and the second circuit structure 120 are electrically connected via a connector 130, wherein the connector 130 may be a solder ball or the like pre-placed on the top second conductive pattern 121a of FIG. 1B, but the present invention is not limited thereto.

In some embodiments, after bonding, the adjacent first dielectric layer 111b and the second dielectric layer 121b are not in direct contact, and the adjacent first circuit layer 111 and the second circuit layer 121 are bonded via a connector 130 (e.g., a solder ball), wherein a bonding region B1 is provided between the second circuit structure 120 and the first circuit structure 110, and the first conductive via 111c in the first circuit layer 111 gradually becomes thicker in a direction toward the bonding region B1, and the second conductive via 121c in the second circuit layer 121 gradually becomes thicker in a direction toward the bonding region B1, but the present invention is not limited thereto.

In some embodiments, the first circuit structure 110 and the second circuit structure 120 have another electrical connection method, as shown in FIG2 , the connector may be a conductive pillar 230, and the conductive pillar 230 may be joined to the first circuit structure 110 via a conductive cover 230a. Here, the conductive pillar 230 may be made of copper, and the conductive cover 230a may be made of solder, but the present invention is not limited thereto, and the conductive pillar 230 and the conductive cover 230a may also be made of other suitable materials, for example, the conductive cover 230a may be Sn/Ag lead-free solder.

In some embodiments, after bonding, the adjacent first dielectric layer 111b and the second dielectric layer 121b are not in direct contact, and the adjacent first circuit layer 111 and the second circuit layer 121 are bonded via the conductive pillar 230, wherein a bonding region B2 is provided between the second circuit structure 120 and the first circuit structure 110, and the first conductive via 111c in the first circuit layer 111 gradually thickens in a direction toward the bonding region B2, and the second conductive via 121c in the second circuit layer 121 gradually thickens in a direction toward the bonding region B2, but the present invention is not limited thereto.

In some embodiments, the first circuit structure 110 and the second circuit structure 120 have another electrical connection method, as shown in FIG. 3 , the connector can be omitted. In other words, the first circuit structure 110 and the second circuit structure 120 can be directly bonded by a Cu to Cu hybrid bonding process or a Cu to Cu direct bonding process, so that the first conductive pattern 111a is in direct contact with the second conductive pattern 121a, and the first dielectric layer 111b is in direct contact with the second dielectric layer 121b, wherein the first conductive pattern 111a is, for example, substantially aligned with the second conductive pattern 121a, but due to the design of process conditions, the first conductive pattern 111a may also be substantially partially staggered with the second conductive pattern 121a. In addition, since no soldering material is used to connect the first circuit structure 110 and the second circuit structure 120, it can be regarded as a solderless connection.

In some embodiments, after bonding, the adjacent first dielectric layer 111b is in direct contact with the second dielectric layer 121b, and the adjacent first conductive pattern 111a is in direct contact with the second conductive pattern 121a, wherein a bonding region B3 is provided between the second circuit structure 120 and the first circuit structure 110, and the first conductive via 111c in the first circuit layer 111 gradually becomes thicker in a direction toward the bonding region B3, and the second conductive via 121c in the second circuit layer 121 gradually becomes thicker in a direction toward the bonding region B3, but the present invention is not limited thereto.

It must be noted here that the following embodiments continue to use the component numbers and part of the contents of the above embodiments, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the above embodiments, and the following embodiments will not be repeated.

4A, 4B, 4C, and 5 are partial schematic cross-sectional views showing semiconductor substrates according to some embodiments of the present invention.

Referring to FIG. 4A , compared to the semiconductor substrate S1 of FIG. 1E , the semiconductor substrate S2 of this embodiment further includes a circuit board 104 disposed on the first circuit structure 110, wherein the circuit board 104 may be a printed circuit board (PCB) or a multi-layer ceramic substrate, but the present invention does not limit the type or form of the circuit board. It should be noted that the circuit board 104 may also be disposed on the second circuit structure 120 (not shown).

For example, the circuit board 104 includes a core dielectric layer 104a, build-up structures 104b disposed on opposite sides of the core dielectric layer 212, and conductive through holes 104c penetrating the core dielectric layer 104a, wherein the conductive through holes 104c provide a vertical conductive path so that the build-up structures 104b disposed on opposite sides of the core dielectric layer 104a can be electrically connected to each other through the conductive through holes 104c.

In this embodiment, the internal circuit of the build-up structure 104b is not shown. The internal circuit design can be determined according to actual design requirements. For example, the internal circuit of the build-up structure 4b may include a dielectric layer and a conductive layer (which may include conductive features such as conductive wires, conductive through holes, and conductive pads) stacked sequentially on the core dielectric layer 104a.

In some embodiments, the material of the core dielectric layer 104a includes a semi-cured film, glass or other suitable dielectric materials, and the conductive features of the conductive through-hole 104c and the build-up structure 104b may include copper or other suitable conductive materials. For example, when the core dielectric layer 104a is glass, the circuit board 104 can be called a glass core substrate, which has the advantage of high flatness, but the present invention is not limited to this.

In FIG. 4A , the first circuit structure 110 is electrically connected to the circuit board 104 via the connector 102a, and the first circuit structure 110 is electrically connected to the second circuit structure 120 via the connector 130. However, the present invention is not limited thereto. In an embodiment not shown, the connector 102a may be omitted between the first circuit structure 110 and the circuit board 104, and the electrical connection may be performed by a suitable direct bonding process. The connector 130 may be omitted between the first circuit structure 110 and the second circuit structure 120, and the electrical connection may be performed by a suitable direct bonding process.

Referring to FIG. 4B , compared to the semiconductor substrate S2 of FIG. 4A , the connector 102a of the semiconductor substrate S3 of this embodiment is in the form of a conductive column, and first semiconductor elements 105 (two are schematically shown in FIG. 4B ) are further included between adjacent connectors 102a to further enhance the application flexibility of the semiconductor substrate S3, but the present invention is not limited thereto. Here, the first semiconductor element 105 includes a die, a capacitor, an inductor, or the like.

Referring to FIG. 4C , compared to the semiconductor substrate S3 of FIG. 4B , the semiconductor substrate S4 of this embodiment further includes a second semiconductor element 106 (two are schematically shown in FIG. 4C ) disposed in a circuit board 104 (such as a glass core substrate) to further enhance the application flexibility of the semiconductor substrate S4, but the present invention is not limited thereto. Here, the second semiconductor element 106 includes a die, a capacitor, an inductor, or the like.

Please refer to Figure 5. Compared with the semiconductor substrate S1 in Figure 1D, the semiconductor substrate S5 of this embodiment further includes a permanent carrier 10a, which is arranged on the first circuit structure 110 or the second circuit structure 120, wherein the permanent carrier 10a can replace the first carrier 10 in Figure 1B or can replace the second carrier 20 in Figure 1B, and will not be removed after the bonding process and will remain on the semiconductor substrate S3.

Here, although FIG. 5 schematically shows direct contact with the first circuit structure 110, the present invention is not limited thereto, and the permanent carrier 10a may also be directly in contact with the second circuit structure 120. In addition, the permanent carrier 10a may be a carrier including circuits, such as the circuit board 104 of FIG. 4 or the like, which will not be described in detail here, but the present invention does not limit the type of the permanent carrier 10a as long as it does not affect subsequent applications.

FIG6A is a partial schematic cross-sectional view showing a semiconductor substrate according to some embodiments of the present invention. FIG6B to FIG6D are partial schematic cross-sectional views showing a method for manufacturing the first circuit structure or the second circuit structure in FIG6A. FIG6E to FIG6G are partial schematic cross-sectional views showing another method for manufacturing the first circuit structure or the second circuit structure in FIG6A.

Please refer to FIG6A. Compared with the semiconductor substrate S1 of FIG1D, the first circuit structure 110 of the semiconductor substrate S6 of this embodiment is composed of a first glass core substrate 112, and a first bonding pad 113 and a first thin film circuit 114 located on opposite sides thereof, and the second circuit structure 120 is composed of a second glass core substrate 122, and a second bonding pad 123 and a second thin film circuit 124 located on opposite sides thereof. Here, the first thin film circuit 114 and the second thin film circuit 124 are optionally formed in this embodiment and subsequent embodiments, that is, the first thin film circuit 114 and the second thin film circuit 124 can be omitted, and will not be described in detail below. In addition, the first thin film circuit 114 and the second thin film circuit 124 may be appropriate redistribution structures (RDL), which are only schematically shown as alternately stacked circuit layers and dielectric layers (not labeled) in the drawings.

In this embodiment, the first circuit structure 110 and the second circuit structure 120 can be bonded by a bonding layer 310, wherein the bonding layer 310 can be a primer or a suitable adhesive material and the bonding method is, for example, hybrid bonding. Further, when the bonding layer 310 is a primer, the bonding layer 310 can be formed after the first bonding pad 113 and the second bonding pad 123 are directly bonded, so that the primer can fill the gap between the first bonding pad 113 and the second bonding pad 123. When the bonding layer 310 is an adhesive material, other manufacturing methods can be used, which will be described in detail below.

In this embodiment, the first glass core substrate 112 and the second glass core substrate 122 each include a plurality of glass through-holes. Since the present invention first manufactures the glass through-holes in the plurality of circuit structures separately and then assembles the plurality of circuit structures into a semiconductor substrate, it is not necessary to form a glass through-hole with a large aspect ratio at one time (only a glass through-hole of half the size needs to be formed at one time), thereby reducing the difficulty of filling metal during the manufacture of the glass through-holes and reducing the probability of crack propagation, thereby effectively improving the reliability of the semiconductor substrate. Here, the aspect ratio is the depth of the glass through-hole/the diameter of the glass through-hole.

Please refer to FIG. 6B to FIG. 6D . In the embodiment of forming the through glass via first (TGV first), a plurality of through holes 12 may be formed in the glass substrate 11 first, as shown in FIG. 6B . Then, a conductive metal material is filled in the plurality of through holes 12 to form the through glass via 13, as shown in FIG. 6C . Then, a thin film circuit 14 may be optionally formed on the aforementioned structure and a corresponding bonding pad 15 may be formed on the through glass via 13, as shown in FIG. 6D . The aforementioned manufacturing process may be applicable to the first circuit structure 110 and the second circuit structure 120 . The glass substrate 11 and the through glass via 13 may correspond to the first glass core substrate 112 / the second glass core substrate 122 . The bonding pad 15 may correspond to the first bonding pad 113 / the second bonding pad 123 . The thin film circuit 14 may correspond to the first thin film circuit 114 / the second thin film circuit 124 .

Please refer to FIG. 6E to FIG. 6G . In the embodiment of forming the through glass via last (TGV last), a thin film circuit 14 may be optionally formed on the glass substrate 11 first, as shown in FIG. 6E , and then a plurality of through holes 12 are formed in the glass substrate 11, as shown in FIG. 6F . Then, a conductive metal material is filled in the plurality of through holes 12 to form the through glass via 13 and then a bonding pad 15 is formed thereon, as shown in FIG. 6G . The above manufacturing process may be applied to the first circuit structure 110 and the second circuit structure 120 and have a similar corresponding relationship, which will not be described in detail here.

It should be noted that, in the following embodiments, for clarity of description, the first glass core substrate 112 and the second glass core substrate 122 are briefly illustrated. The first glass core substrate 112 and the second glass core substrate 122 may be as shown in FIG. 6A , and their manufacturing methods may refer to FIGS. 6B to 6G .

7A to 7B are partially schematic cross-sectional views illustrating a method of manufacturing a semiconductor substrate according to some embodiments of the present invention.

Referring to FIG. 7A , a two-stage curing material layer 311 having an opening O1 (e.g., by a suitable patterning process) is formed on the glass core substrate 112/122, wherein the opening exposes a portion of the bonding pad 113/123. Then, referring to FIG. 7B , a metal adhesive layer 312 (e.g., copper/silver) is formed in the aforementioned opening, so that the glass core substrate is bonded to the two-stage curing material layer 311 by the metal adhesive layer 312. The board 112/122 forms a semiconductor substrate S7, wherein the metal adhesive layer 312 allows the bonding pads 113/123 to bond to each other, and the two-stage curing material layer 311 surrounds the metal adhesive layer 312. Here, the metal adhesive layer 312 and the two-stage curing material layer 311 (adhesive material) constitute a bonding layer 310, and the metal adhesive layer 312 can be called the first part, and the two-stage curing material layer 311 can be called the second part. In addition, the two-stage curing material layer 311 can be in a semi-cured state before the metal adhesive layer 312 is formed, and after the metal adhesive layer 312 is formed, a heating process is performed to make it a cured state.

In the present embodiment, the second portion covers a portion of the top surface of the bonding pad 113/123, but the present invention is not limited thereto.

8A to 8B are partially schematic cross-sectional views illustrating a method of manufacturing a semiconductor substrate according to some embodiments of the present invention.

Referring to FIG. 8A , compared to the glass core substrate 112/122 of FIG. 7A , the glass core substrate 112A/122A of the present embodiment does not have a bonding pad, and a two-stage curing material layer 311A having an opening O2 (e.g., by a suitable patterning process) is formed thereon, wherein the opening exposes the glass through-hole in the glass core substrate 112A/122A. Then, referring to FIG. 8B , a metal adhesive layer 312A is formed in the aforementioned opening to bond the glass core substrate 112A/122A to the metal adhesive layer. 312A and the two-stage curing material layer 311A are bonded to the glass core substrate 112A/122A to form a semiconductor substrate S8, wherein the metal adhesive layer 312A enables the glass perforations in the glass core substrate 112A/122A to be bonded to each other, and the two-stage curing material layer 311A surrounds the metal adhesive layer 312A. Here, the metal adhesive layer 312A and the two-stage curing material layer 311A are similar to the metal adhesive layer 312 and the two-stage curing material layer 311, and will not be repeated here.

In the present embodiment, the second portion (two-stage cured material layer 311A) does not directly contact the glass through-holes in the glass core substrate 112A/122A, but the present invention is not limited thereto.

9A to 9C are partially schematic cross-sectional views illustrating a method of manufacturing a semiconductor substrate according to some embodiments of the present invention.

Referring to FIG. 9A , compared to the second glass core substrate 122A of FIG. 8A , the glass through-hole 13 in the second glass core substrate 122B of the present embodiment is retracted into the glass substrate by, for example, an etching process to form an opening O3. Then, referring to FIG. 9B , a portion of the glass through-hole 13 and a portion of the glass substrate 11 are further optionally removed by, for example, an etching process to expand the opening O3. Then, referring to FIG. 9C , a metal adhesive layer 312B is formed in the aforementioned opening, and the second glass core substrate 122B is then bonded to the first glass core substrate 112B by the metal adhesive layer 312B and heated to form a semiconductor substrate S9. Here, although the opening O3 is formed in the second glass core substrate 122B in the figure, it is also possible to form an opening in the first glass core substrate 112B and then perform bonding by similar steps. In addition, the two-stage curing material layer can be omitted in this embodiment.

Fig. 9D, Fig. 9E, and Fig. 9F are partial schematic cross-sectional views showing an alternative embodiment of Fig. 9C. Fig. 9G is a partial schematic top view showing Fig. 9D and Fig. 9F.

9D , compared to the semiconductor substrate S9 of FIG. 9C , the glass through hole 13 of the first glass core substrate 112C without an opening in the semiconductor substrate S10 of this embodiment extends to the metal adhesive layer 312B (bonding layer) to form a lock and key structure, thereby improving the bonding reliability.

Referring to FIG. 9E , compared to the semiconductor substrate S9 in FIG. 9C , the semiconductor substrate S10 of this embodiment further includes a metal adhesive layer 312C and a two-stage curing material layer 311B to enhance the bonding force, but the present invention is not limited thereto.

Referring to FIG. 9E , compared to the semiconductor substrate of FIG. 9E , the glass through hole 13 of the first glass core substrate 112C of the semiconductor substrate S11 of this embodiment extends to the metal adhesive layer 312C (bonding layer) to form a snap-fit structure, thereby improving the bonding reliability.

Please refer to Figure 9G. In the tenon structure of Figure 9D and Figure 9F, the joint part can have a small-sized joint part 2 and a large-sized joint part 3, and the large-sized joint part 3 can more effectively improve the snap-fitting ability and thus enhance the reliability. However, the present invention is not limited to this. Here, the small-sized joint part 2 can be applied to the above-mentioned various implementation forms according to actual design requirements, and the present invention is not limited thereto.

In the above-mentioned embodiment where the first circuit structure 110 and the second circuit structure 120 include a glass core substrate and a thin film circuit, if the coefficient of thermal expansion (CTE) of the second circuit structure 120 is smaller than the CTE of the first circuit structure 110, the second circuit structure 120 shrinks less after high temperature condensation, and the first circuit structure 110 shrinks more, thereby generating a concave (crying face) warp phenomenon. Since the CTE of the glass core substrate is smaller than the CTE of the dielectric layer in the thin film circuit, when the thin film circuit is formed on the glass core substrate, an upward concave (smiley face) force is generated to achieve the function of balancing and compensating the aforementioned warp phenomenon. Here, the glass core substrates in the first circuit structure 110 and the second circuit structure 120 can have different CTEs through appropriate thickness or composition design.

It should be noted that, although only two circuit structures are connected as shown in this article, the present invention does not limit the number of connected circuit structures, that is, according to the design criteria of the present invention, three or more circuit structures can be connected. For example, a third circuit structure can be included between the first circuit structure and the second circuit structure, and the third circuit structure is electrically connected to the first circuit structure and the second circuit structure at the same time to enhance the flexibility of product use. In addition, the above disclosed implementations are only exemplary descriptions, and the contents combined and reasonably extended according to the actual design requirements without departing from the spirit and scope of the present invention are all within the protection scope of the present invention.

In summary, the present invention first manufactures multiple circuit structures separately and then assembles the aforementioned multiple circuit structures into a semiconductor substrate. In this way, compared with semiconductor substrates manufactured sequentially at one time, the degree of warping can be effectively reduced, so that the semiconductor substrate can maintain a better yield while having a multi-layer circuit structure and improve the electrical performance in subsequent applications.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

1: interposer 2, 3: bonding part 10: first carrier 10a: permanent carrier 11: glass substrate 12: through hole 13: glass perforation 14: thin film circuit 15: bonding pad 20: second carrier 101: chip 101a: bump 102: external terminal 103: bottom glue 104: circuit board 104a: core dielectric layer 104b: build-up structure 104c: conductive through hole 105, 106: semiconductor element 110: first circuit structure 110t, 120t: top surface 110b, 120b: bottom surface 111: first circuit layer 111a: first conductive pattern 111b: first dielectric layer 111c: first conductive via 112, 112A, 112B, 112C: first glass core substrate 113: first bonding pad 114: first thin film circuit 120: second circuit structure 121: second circuit layer 121a: second conductive pattern 121b: second dielectric layer 121c: second conductive via 122, 122A, 122B: second glass core substrate 123: second bonding pad 124: second thin film circuit 130: connector 230: conductive column 230a: conductive cover 310: bonding layer 311, 311A, 311B: two-stage curing material layer 312, 312A, 312B, 312C: metal adhesive layer B1, B2, B3: bonding area EP, EP2: electronic package S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11: semiconductor substrate O1, O2, O3: opening

FIG. 1A is a schematic diagram showing an assembly of a semiconductor substrate according to some embodiments of the present invention. FIG. 1B to FIG. 1E are partially schematic cross-sectional views showing a method for manufacturing a semiconductor substrate according to some embodiments of the present invention. FIG. 1F is a schematic diagram showing a semiconductor substrate according to some embodiments of the present invention when it is bonded. FIG. 1G and FIG. 1H are partially schematic cross-sectional views showing an electronic assembly including a semiconductor substrate according to some embodiments of the present invention. FIG. 2 and FIG. 3 are partially schematic cross-sectional views showing an alternative embodiment of the structure of FIG. 1D. FIG. 4A, FIG. 4B, FIG. 4C, and FIG. 5 are partially schematic cross-sectional views showing a semiconductor substrate according to some embodiments of the present invention. FIG. 6A is a partially schematic cross-sectional view showing a semiconductor substrate according to some embodiments of the present invention. 6B to 6D are partially schematic cross-sectional views showing a method for manufacturing the first circuit structure or the second circuit structure in FIG. 6A. FIGS. 6E to 6G are partially schematic cross-sectional views showing another method for manufacturing the first circuit structure or the second circuit structure in FIG. 6A. FIGS. 7A to 7B are partially schematic cross-sectional views showing a method for manufacturing a semiconductor substrate according to some embodiments of the present invention. FIGS. 8A to 8B are partially schematic cross-sectional views showing a method for manufacturing a semiconductor substrate according to some embodiments of the present invention. FIGS. 9A to 9C are partially schematic cross-sectional views showing a method for manufacturing a semiconductor substrate according to some embodiments of the present invention. FIGS. 9D, 9E, and 9F are partially schematic cross-sectional views showing an alternative embodiment of FIG. 9C. FIG. 9G is a partially schematic top view showing FIG. 9D and FIG. 9F.

10: First carrier

20: Second carrier

110: First circuit structure

110t, 120t: Top surface

110b, 120b: bottom surface

111: First circuit layer

111a: First conductive pattern

111b: first dielectric layer

111c: first conductive via

120: Second circuit structure

121: Second circuit layer

121a: Second conductive pattern

121b: Second dielectric layer

121c: second conductive via

130: Connectors

B1: junction area

Claims (31)

A semiconductor substrate, comprising: a first circuit structure, comprising a first circuit layer, a first glass core substrate, a first bonding pad, and a first thin film circuit located on the first glass core substrate and on the opposite side of the first bonding pad, wherein the first circuit layer comprises a first dielectric layer; and a second circuit structure, comprising a second circuit layer, a second glass core substrate, a second bonding pad, and a second thin film circuit located on the second glass core substrate and on the opposite side of the second bonding pad, wherein the thermal expansion coefficient of the first glass core substrate is different from the thermal expansion coefficient of the second glass core substrate, the second circuit layer comprises a second dielectric layer, the second circuit structure is arranged on the first circuit structure and is electrically connected to the first circuit structure to constitute the semiconductor substrate, wherein The first circuit structure is a back-end process type, a thin film redistribution type, a build-up substrate type, or a printed circuit board type, and the second circuit structure is the back-end process type, the thin film redistribution type, the build-up substrate type, or the printed circuit board type, the thickness of the first dielectric layer in the back-end process type is less than 1 micron, the thickness of the first dielectric layer in the thin film redistribution type is between 1 micron and 10 microns, the thickness of the first dielectric layer in the build-up substrate type is between 8 microns and 30 microns, and the thickness of the first dielectric layer in the printed circuit board type is between 15 microns and 60 microns. A semiconductor substrate as described in claim 1, wherein the first circuit structure and the second circuit structure are of the same type or different types. A semiconductor substrate as described in claim 1, wherein the material of the first dielectric layer in the back-end process type includes silicon nitride or silicon oxide, the material of the first dielectric layer in the thin film redistribution type includes polyimide or benzocyclobutene, the material of the first dielectric layer in the build-up substrate type includes Ajinomoto film material or Ajinomoto film-derived material, and the material of the first dielectric layer in the printed circuit board type includes semi-cured film or bismaleimide triazine. A semiconductor substrate as described in claim 1, wherein the bending direction of the first circuit structure is opposite to the bending direction of the second circuit structure. The semiconductor substrate as described in claim 1 further includes a permanent carrier disposed on the first circuit structure or the second circuit structure. A semiconductor substrate as described in claim 1, wherein there is a bonding area between the second circuit structure and the first circuit structure, the first circuit layer further includes a first conductive through hole that gradually becomes thicker in a direction toward the bonding area, and the second circuit layer further includes a second conductive through hole that gradually becomes thicker in a direction toward the bonding area. A semiconductor substrate as described in claim 1, wherein: the first circuit layer includes a plurality of first conductive patterns; the second circuit layer includes a plurality of second conductive patterns; the adjacent first dielectric layer and the second dielectric layer are not in direct contact, and the adjacent first conductive patterns and the second conductive patterns are bonded by solder balls; the adjacent first dielectric layer and the second dielectric layer are not in direct contact, and the adjacent first conductive patterns and the second conductive patterns are bonded by conductive pillars; or the adjacent first dielectric layer and the second dielectric layer are in direct contact, and the adjacent first conductive patterns and the second conductive patterns are in direct contact. The semiconductor substrate as described in claim 1 further includes a third glass core substrate disposed on the first circuit structure or the second circuit structure. A semiconductor substrate as described in claim 8, wherein the third glass core substrate is electrically connected to the first circuit structure or the second circuit structure via a plurality of connectors. The semiconductor substrate as described in claim 9 further includes a first semiconductor element disposed between two adjacent ones of the plurality of connectors. The semiconductor substrate as described in claim 10 further includes a second semiconductor element disposed in the third glass core substrate. A semiconductor substrate as described in claim 8, wherein no connector is included between the third glass core substrate and the first circuit structure or the second circuit structure. The semiconductor substrate as described in claim 1 further includes a bonding layer disposed between the first circuit structure and the second circuit structure. A semiconductor substrate as described in claim 13, wherein the bonding layer is a primer, and the primer fills the gap between the first bonding pad and the second bonding pad. A semiconductor substrate as described in claim 13, wherein the bonding layer is an adhesive material, and the adhesive material includes a first portion bonding the first bonding pad and the second bonding pad and a second portion surrounding the first portion. A semiconductor substrate as described in claim 15, wherein the first part is a metal adhesion layer and the second part is a two-stage curing material layer. A semiconductor substrate as described in claim 15, wherein the second portion covers a portion of the top surface of the first bonding pad and the second bonding pad. A semiconductor substrate as described in claim 1, wherein the first glass core substrate is bonded to the second glass substrate via a bonding layer. A semiconductor substrate as described in claim 18, wherein the bonding layer is an adhesive material, and the adhesive material includes a first portion that bonds the glass through hole in the first glass core substrate and the glass through hole in the second glass core substrate. A semiconductor substrate as described in claim 19, wherein the adhesive material further includes a second portion surrounding the first portion. A semiconductor substrate as described in claim 20, wherein the first part is a metal adhesion layer and the second part is a two-stage curing material layer. A semiconductor substrate as described in claim 20, wherein the second portion does not directly contact the glass through-hole in the first glass core substrate and the glass through-hole in the second glass core substrate. A semiconductor substrate as described in claim 20, wherein the first portion is embedded in one of the first glass core substrate or the second glass core substrate. A semiconductor substrate as described in claim 20, wherein the glass through hole of the other of the first glass core substrate or the second glass core substrate extends to the bonding layer. An electronic package, comprising: A semiconductor substrate as described in any one of claim 1 to claim 24; and At least one chip disposed on the semiconductor substrate. A method for manufacturing a semiconductor substrate, comprising: forming a first circuit structure on a first carrier, wherein the first circuit structure comprises a first circuit layer, a first glass core substrate, a first bonding pad and a first thin film circuit, and the first circuit layer comprises a first dielectric layer; forming a second circuit structure on a second carrier, wherein the second circuit structure comprises a second circuit layer, a second glass core substrate, a second bonding pad and a second thin film circuit, and the second circuit layer comprises a second dielectric layer, one of the first carrier and the second carrier is a temporary carrier, and the other of the first carrier and the second carrier is a temporary carrier or a permanent carrier; and bonding the first circuit structure and the second circuit structure so that the first circuit structure and the second circuit structure are electrically connected to form the semiconductor substrate. A method for manufacturing a semiconductor substrate as described in claim 26, wherein the glass perforations in the first glass core substrate and the second glass core substrate are formed earlier than the first thin film circuit and the second thin film circuit, respectively. A method for manufacturing a semiconductor substrate as described in claim 26, wherein the glass perforations in the first glass core substrate and the second glass core substrate are formed later than the first thin film circuit and the second thin film circuit, respectively. The method for manufacturing a semiconductor substrate as described in claim 28 further includes a plurality of openings, wherein the plurality of openings expose a portion of the first circuit structure or a portion of the second circuit structure before joining the first circuit structure and the second circuit structure. A method for manufacturing a semiconductor substrate as described in claim 29, wherein the plurality of openings are formed in the first glass core substrate or the second glass core substrate. The method for manufacturing a semiconductor substrate as described in claim 30 further includes further expanding the multiple openings.

Images