TWI884420B - Electronic package and manufacturing method thereof - Google Patents

Abstract

An electronic package is provided, in which a first electronic component and a second electronic component stacked each other and electrically connected each other with a plurality of conductors are embedded in the encapsulation layer, and a wiring structure is arranged on the encapsulation layer, a circuit structure is provided on the wiring structure, and a conductive via penetrates the encapsulation layer, the wiring structure and the circuit structure and electrically connects the wiring structure and the circuit structure. Therefore, by stacking the first and second electronic components in the encapsulation layer, the electronic package meets the requirement of multi-function.

Description

Electronic packaging and its manufacturing method

The present invention relates to a semiconductor packaging technology, in particular to an electronic package with multiple stacked chips and its manufacturing method.

With the booming development of portable electronic products in recent years, various related products are gradually developing towards high density, high performance, light, thin, short and small. Among them, various types of semiconductor packaging structures used in portable electronic products are also being developed in order to meet the requirements of lightness, thinness, shortness and high density.

FIG1 is a cross-sectional schematic diagram of a semiconductor package 1 using wafer-level packaging technology. As shown in FIG1 , the semiconductor package 1 includes: a coating layer 15, a semiconductor chip 11 embedded in the coating layer 15, a plurality of conductive pillars 13 embedded in the coating layer 15, a wiring structure 10 disposed on the coating layer 15, an electronic component 16 disposed on the wiring structure 10, and a packaging layer 18 encapsulating the electronic component 16, and the wiring structure 10 electrically connects the semiconductor chip 11, the conductive pillar 13 and the electronic component 16, and forms a plurality of solder balls 19 on the lower side of the conductive pillar 13 for bonding to a circuit board (not shown).

However, in the conventional semiconductor package 1, only a single semiconductor chip 11 is embedded in the encapsulation layer 15, so that the semiconductor package 1 cannot meet the multi-functional requirements. If the multi-functional requirements are to be met, the surface area of the encapsulation layer 15 needs to be expanded to increase the contacts of the wiring structure 10 and configure multiple electronic components 16, which makes it difficult to miniaturize the semiconductor package 1.

Furthermore, since the packaging layer 18 needs to be additionally formed to match the electronic component 16, it is also difficult to thin the semiconductor package 1.

In addition, the insulation layer of the wiring structure 10 is made of Ajinomoto build-up film (ABF), which makes the strength of the wiring structure 10 insufficient. Therefore, the semiconductor package 1 is prone to warping during the manufacturing process.

In addition, the conductive column 13 needs to penetrate the cladding layer 15, so it is necessary to first form a through hole through the cladding layer 15 by laser, and then electroplate a copper column in the through hole. Therefore, before making the through hole, the surface of the cladding layer needs to be polished and flattened to ensure that the laser drilling can accurately burn the cladding layer 15 and reliably penetrate the cladding layer 15. Therefore, the process is extremely complicated, making it difficult to reduce the manufacturing cost.

Therefore, how to overcome the various shortcomings of knowledge technology is a technical problem that all walks of life are eager to solve.

In view of the above-mentioned deficiencies in the prior art, the present invention provides an electronic package, comprising: a coating layer having a first surface and a second surface opposite to each other; a first electronic element embedded in the coating layer; a second electronic element embedded in the coating layer and stacked on the first electronic element; a plurality of conductors embedded in the coating layer and electrically connected to the first electronic element and the second electronic element, respectively, and the plurality of conductors are aligned with the first surface of the coating layer; a wiring structure is provided on the second surface of the coating layer; On a surface, the wiring structure includes at least one insulating layer formed on the coating layer, and a wiring layer combined with the insulating layer and electrically connected to the conductor, and the insulating layer is a Mikoto build-up film; the wiring structure is arranged on the wiring structure, the wiring structure includes at least one dielectric layer, and a wiring layer combined with the dielectric layer, and the material forming the dielectric layer is different from the material forming the insulating layer; and the conductive through-hole penetrates the coating layer, the insulating layer and the dielectric layer and electrically connects the wiring layer and the wiring layer.

The present invention also provides a method for manufacturing an electronic package, comprising: embedding a first electronic component and a second electronic component in a coating layer, wherein the coating layer has a first surface and a second surface opposite to each other, and the second electronic component is stacked on the first electronic component, and forming a plurality of conductors electrically connected to the first electronic component and the second electronic component on the first electronic component and the second electronic component, respectively, so that the plurality of conductors are aligned with the first surface of the coating layer; forming a wiring structure on the first surface of the coating layer, The wiring structure includes at least one insulating layer formed on the coating layer, and a wiring layer combined with the insulating layer and electrically connected to the conductor, and the insulating layer is a Mikoto build-up film; a wiring structure is formed on the wiring structure, and the wiring structure includes at least one dielectric layer and a wiring layer combined with the dielectric layer, and the material forming the dielectric layer is different from the material forming the insulating layer; and at least one conductive perforation is formed that penetrates the coating layer, the insulating layer and the dielectric layer, and the conductive perforation electrically connects the wiring layer and the wiring layer.

The present invention further provides an electronic package, comprising: a coating layer having a first surface and a second surface opposite to each other; a first electronic element embedded in the coating layer; a second electronic element embedded in the coating layer and stacked on the first electronic element; a plurality of conductors embedded in the coating layer and electrically connected to the first electronic element and the second electronic element, respectively, and the plurality of conductors are aligned with the first surface of the coating layer; a wiring structure is disposed on the first surface of the coating layer, and the wiring structure is arranged on the first surface of the coating layer. The line structure includes at least one insulating layer formed on the coating layer, and a wiring layer combined with the insulating layer and electrically connected to the conductor, and the insulating layer is a Mikoto-added film; the line structure is arranged on the second surface of the coating layer, and the line structure includes at least one dielectric layer and a wiring layer combined with the dielectric layer, and the material forming the dielectric layer is different from the material forming the insulating layer; and the conductive through-hole penetrates the coating layer, the insulating layer and the dielectric layer and electrically connects the wiring layer and the wiring layer.

The present invention further provides a method for manufacturing an electronic package, comprising: embedding a first electronic component and a second electronic component in a coating layer, wherein the coating layer has a first surface and a second surface opposite to each other, and the second electronic component is stacked on the first electronic component, and forming a plurality of conductors electrically connected to the first electronic component and the second electronic component on the first electronic component and the second electronic component, respectively, so that the plurality of conductors are flush with the first surface of the coating layer; forming a wiring structure on the first surface of the coating layer, and the The wiring structure includes at least one insulating layer formed on the coating layer, and a wiring layer combined with the insulating layer and electrically connected to the conductor, and the insulating layer is a Mikoto build-up film; a circuit structure is formed on the second surface of the coating layer, and the circuit structure includes at least one dielectric layer and a circuit layer combined with the dielectric layer, and the material forming the dielectric layer is different from the material forming the insulating layer; and at least one conductive perforation is formed that penetrates the coating layer, the insulating layer and the dielectric layer, and the conductive perforation is electrically connected to the wiring layer and the circuit layer.

In the aforementioned electronic package and its manufacturing method, the conductive body is a conductive wire in the form of a welding wire.

In the aforementioned electronic package and its manufacturing method, the conductive body includes a column disposed on the first electronic component and a conductive blind hole connected to the column.

In the aforementioned electronic package and its manufacturing method, the conductive body is a conductive blind hole provided on the second electronic component.

As can be seen from the above, the electronic package and its manufacturing method of the present invention mainly stack the first and second electronic components in the coating layer, so that the electronic package meets the multi-functional requirements and can reduce the surface area of the coating layer, so as to facilitate the miniaturization of the electronic package.

Furthermore, since both the wiring structure and the circuit structure are in the form of a core-less structure, it is beneficial to thin the electronic package.

In addition, the configuration of the dielectric layer is different from that of ABF to improve the toughness of the circuit structure. Therefore, compared with the conventional technology, the electronic package will not warp during the manufacturing process.

In addition, the design of the first conductor reduces the depth of the second conductor. Therefore, compared with the prior art, before the conductive blind hole is made in the electronic package of the present invention, the first surface of the coating layer does not need to be polished and leveled, thereby simplifying the process and reducing the manufacturing cost.

1:Semiconductor packages

10,25,26,27,35: Wiring structure

11: Semiconductor chip

13:Conductive pillar

15,23: Coating layer

16: Electronic components

18: Packaging layer

19,600: Solder balls

2,3,4,5: Electronic packaging

2a: Electronic module

2b: Packaging module

20: Binding layer

21: First electronic component

21a, 22a: Action surface

21b, 22b: non-active surface

210,220:Electrode pad

22: Second electronic component

23: Coating layer

23a: First surface

23b: Second surface

230: Blind hole

24: Welding wire

24a,24b: Conductor

250,260,270: Insulation layer

251,261,262,271,272,351: wiring layer

28,48: Line structure

280,480: Dielectric layer

281,481: Line layer

29:Conductive perforation

34: First conductor

34a, 34b: Second conductor

47: Insulation protective layer

470: Opening

472: Conductive bumps

60: Circuit board

61,62a,63: Functional elements

610,620,630: Conductive components

62: Functional module

621,631: Conductive silicon vias

8: Support parts

9: Carrier plate

90: Release layer

91,92: Metal layer

S: imaginary plane

Figure 1 is a schematic cross-sectional view of a conventional semiconductor package.

Figures 2A to 2G are cross-sectional schematic diagrams of the manufacturing method of the first embodiment of the electronic package of the present invention.

Figure 2A-1 and Figure 2A-2 are cross-sectional schematic diagrams of the manufacturing process of Figure 2A.

Figure 2F-1 and Figure 2F-2 are cross-sectional schematic diagrams of the manufacturing process of Figure 2F.

FIG2H is a cross-sectional schematic diagram of the subsequent process of FIG2G.

Figures 3A to 3E are cross-sectional schematic diagrams of the manufacturing method of the second embodiment of the electronic package of the present invention.

Figures 4A to 4E are cross-sectional schematic diagrams of the manufacturing method of the third embodiment of the electronic package of the present invention.

FIG4F is a cross-sectional schematic diagram of the subsequent process of FIG4E.

FIG5A is a cross-sectional schematic diagram of the manufacturing method of the fourth embodiment of the electronic package of the present invention.

FIG5B is a cross-sectional schematic diagram of the subsequent process of FIG5A.

The following is a specific and concrete example to illustrate the implementation of the present invention. People familiar with this technology can easily understand other advantages and effects of the present invention from the content disclosed in this manual.

It should be noted that the structures, proportions, sizes, etc. depicted in the drawings attached to this specification are only used to match the contents disclosed in the specification for understanding and reading by people familiar with this technology, and are not used to limit the restrictive conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "above", "first", "second" and "one" used in this specification are only used to facilitate the clarity of the description, and are not used to limit the scope of implementation of the present invention. Changes or adjustments to their relative relationships, without substantially changing the technical content, should also be regarded as the scope of implementation of the present invention.

Figures 2A to 2G are schematic cross-sectional views of the manufacturing method of the first embodiment of the electronic package 2 of the present invention.

As shown in FIG. 2A , a carrier plate 9 is provided, on which a stacking assembly is formed, and the stacking assembly includes at least one first electronic component 21 disposed on the carrier plate 9 and at least one second electronic component 22 disposed on the first electronic component 21. Then, a coating layer 23 is formed on the carrier plate 9 so that the coating layer 23 covers the first electronic component 21 and the second electronic component 22.

The carrier plate 9 is a plate made of semiconductor material (such as silicon or glass) or other materials, on which a release layer 90 and a metal layer 91 are sequentially formed by coating, for example, so that the first electronic element 21 is disposed on the metal layer 91.

The first electronic component 21 is an active component, a passive component or a combination of the two, and the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor.

In this embodiment, the first electronic component 21 is a semiconductor chip having an active surface 21a and an inactive surface 21b opposite to each other. The inactive surface 21b of the first electronic component 21 is bonded to the metal layer 91 via a bonding layer 20 such as a tape, and the active surface 21a has a plurality of electrode pads 210, and a conductor 24a embedded in the encapsulation layer 23 is formed on the electrode pads 210.

The second electronic element 22 is an active element, a passive element or a combination of the two, and the active element is, for example, a semiconductor chip, and the passive element is, for example, a resistor, a capacitor and an inductor. In this embodiment, the second electronic element 22 is a semiconductor chip, which has an active surface 22a and an inactive surface 22b opposite to each other. The second electronic element 22 is bonded to the active surface 21a of the first electronic element 21 by the bonding layer 20 with its inactive surface 22b, and the active surface 22a of the second electronic element 22 also has a plurality of electrode pads 220, and a conductor 24b embedded in the coating layer 23 is formed on the electrode pads 220 of the second electronic element 22.

In this embodiment, the conductors 24a, 24b are wires. For example, before forming the coating layer 23, as shown in FIG. 2A-1, the two opposite ends of the plurality of welding wires 24 are connected to different electrode pads 210, 220 respectively by wire bonding, and then the coating layer 23 is formed, as shown in FIG. 2A-2, so that the coating layer 23 covers the welding wires 24, and then, part of the material of the coating layer 23 and the arc segments of the welding wires 24 are removed, so that the welding wires 24 form straight segments to serve as the conductors 24a, 24b, so that the conductors 24a, 24b are exposed from the coating layer 23.

Furthermore, the layout area of the first electronic component 21 is larger than the layout area of the second electronic component 22. For example, two first electronic components 21 carry one second electronic component 22, so that the two ends of a single welding wire 24 are respectively connected to a single electrode pad 210 of the two first electronic components 21, and the two ends of another welding wire 24 are connected to two electrode pads 220 of a second electronic component 22.

The coating layer 23 has a first surface 23a and a second surface 23b opposite to each other, so that the coating layer 23 is bonded to the metal layer 91 of the carrier plate 9 with its second surface 23b.

In this embodiment, the coating layer 23 is an insulating material, such as polyimide (PI), dry film, epoxy or molding compound. For example, the coating layer 23 can be formed on the metal layer 91 by liquid compound, injection, lamination or compression molding.

Furthermore, by a flattening process, such as grinding, part of the material of the coating layer 23 and the arc segments of the welding wires 24 are removed, so that the first surface 23a of the coating layer 23 is flush with the end surfaces of the conductors 24a, 24b, so that the end surfaces of the conductors 24a, 24b are exposed on the first surface 23a of the coating layer 23.

As shown in FIG. 2B , a wiring structure 25 is formed on the first surface 23a of the cladding layer 23, and the wiring structure 25 is electrically connected to the conductors 24a, 24b. Then, another metal layer 92 is formed on the wiring structure 25.

In this embodiment, the wiring structure 25 includes at least one insulating layer 250 and a wiring layer 251 disposed on the insulating layer 250. For example, the wiring layer 251 is manufactured by electroplating metal (such as copper) or other methods using a build-up process, and includes a plurality of copper pillars electrically connecting the conductors 24a, 24b, and the insulating layer 250 is a dielectric material of Ajinomoto build-up film (ABF).

Furthermore, by configuring the metal layer 92, the surface of the wiring structure 25 is flattened so that the surface of the wiring layer 251 is flush with the surface of the insulating layer 250.

As shown in FIG. 2C , the carrier plate 9 is separated by the release layer 90 so that the metal layer 91 remains on the second surface 23b of the cladding layer 23.

As shown in FIG. 2D to FIG. 2E, another wiring structure 27 is formed on the wiring structure 25, and a wiring structure 26 can also be formed on the second surface 23b of the cladding layer 23 to form an electronic module 2a.

In this embodiment, the wiring structure 27 includes at least one insulating layer 270 and wiring layers 271, 272 disposed on the insulating layer 270. For example, the wiring layers 271, 272 are manufactured by electroplating metal (such as copper) or other methods such as a redistribution layer (RDL), and the insulating layer 270 is ABF. It should be understood that the number of wiring layers 251, 271, 272 on the first surface 23a of the cladding layer 23 can be designed according to demand.

Furthermore, the wiring structure 26 on the second surface 23b of the cladding layer 23 includes at least one insulating layer 260 and wiring layers 261, 262 disposed on the insulating layer 260. For example, the wiring layers 261, 262 are made by electroplating metal (such as copper) or other methods using a build-up method, such as a redistribution layer (RDL), and the insulating layer 260 is ABF. It should be understood that the number of wiring layers 261, 262 on the second surface 23b of the cladding layer 23 can be designed according to demand, so the number of RDLs on the first and second surfaces 23a, 23b of the cladding layer 23 can be the same or different.

Furthermore, when manufacturing the wiring structures 26, 27, the metal layers 91, 92 can be used to first manufacture a single wiring layer 261, 271, as shown in FIG. 2D, to form a packaging module 2b.

As shown in FIG. 2F , a circuit structure 28 is formed on the wiring structures 25, 27 on the first surface 23a of the cladding layer 23.

In this embodiment, the circuit structure 28 includes at least one dielectric layer 280 formed on the insulating layer 270 and the wiring layer 272, and a circuit layer 281 disposed on the dielectric layer 280 and electrically connected to the wiring layer 272. For example, a build-up method is used to perform laser drilling on the dielectric layer 280, and then patterning and electroplating metal (such as copper) or other methods to manufacture the circuit layer 281, and the material forming the dielectric layer 280 is polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

Furthermore, the manufacturing process of the circuit structure 28 adopts a symmetrical method, whereby the wiring structures 26 of the plurality of electronic modules 2a on the second surface 23b of the coating layer 23 are respectively pressed on the opposite sides of a support member 8, as shown in FIG. 2F-1, so that the other wiring structure 27 of the electronic module 2a is exposed; then the circuit structure 28 is formed on the exposed wiring structure 27, as shown in FIG. 2F-2; thereafter, the support member 8 is removed.

Furthermore, if the support member 8 is made of a soft material such as a thermal release film, the wiring layer 262 can be pressed into the support member 8, and it is beneficial to symmetrically form the dielectric layer 280 of the PP material. Therefore, after the production of the circuit structure 28 is completed, the support member 8 can be heated to remove the support member 8. It should be understood that the removal of the thermal release film requires a higher decomposition temperature, about 180~220℃, which is at least higher than the glass transition temperature (symbol Tg) of the dielectric layer 280 (such as PP material).

As shown in FIG. 2G , at least one conductive via 29 is formed to penetrate the wiring structure 25, 26, 27, the cladding layer 23 and the circuit structure 28, so that the conductive via 29 is electrically connected to the wiring layer 261, 262, 271, 272 and the circuit layer 281. It should be understood that if it is mass production, a singulation process is required after forming the conductive via 29.

In this embodiment, the manufacturing process of the conductive via 29 is to first form a via that penetrates the wiring structure 25, 26, 27, the cladding layer 23 and the circuit structure 28, and then form a metal material in the via to serve as the conductive via 29.

Furthermore, the electronic package 2 uses the second surface 23b of the encapsulation layer 23 as the die placement side and the first surface 23a of the encapsulation layer 23 as the mounting side. Therefore, in the subsequent manufacturing process, as shown in FIG. 2H , a plurality of conductive elements 610 such as solder bumps can be formed on the wiring layer 262 at the outermost side of the wiring structure 26 to connect at least one functional element 61 to the conductive elements 610, and a plurality of solder balls 600 can be formed on the circuit layer 281 at the outermost side of the circuit structure 28 to allow the electronic package 2 to be placed on a circuit board 60 through the solder balls 600.

The functional element 61 is an active element, a passive element or a combination of the two, and the active element is, for example, a semiconductor chip, and the passive element is, for example, a resistor, a capacitor and an inductor. In this embodiment, the functional element 61 is a semiconductor chip, which is disposed on the wiring structure 26 in a flip-chip manner through the conductive elements 610, so that the functional element 61 is electrically connected to the wiring layer 262 through the conductive elements 610.

Therefore, in the manufacturing method of the electronic package 2 of the present invention, the welding wire 24 used in the wire bonding process is mainly used as the conductor 24a, 24b and embedded in the coating layer 23 to omit the conventional processes of conducting columns such as laser drilling and electroplating copper columns. Therefore, compared with the conventional technology, the manufacturing method of the present invention can simplify the process to greatly save the manufacturing cost of the electronic package 2.

Furthermore, since the wiring structures 25, 26, 27 and the circuit structure 28 are all coreless, it is beneficial to thin the electronic package 2.

In addition, by using PP material as the dielectric layer 280, the toughness of the circuit structure 28 is improved, so after removing the support member 8, the electronic package 2 will not warp during the manufacturing process.

In addition, by stacking the first and second electronic components 21, 22 in the coating layer 23, the electronic package 2 can meet the multifunctional requirements and reduce the area of the first surface 23a or the second surface 23b of the coating layer 23, so as to facilitate the miniaturization of the electronic package 2.

Figures 3A to 3E are cross-sectional schematic diagrams of the manufacturing method of the second embodiment of the electronic package 3 of the present invention. The difference between this embodiment and the first embodiment lies in the form of the conductor, and the other processes are roughly the same, so the similarities will not be repeated below.

As shown in FIG3A , in the process shown in FIG2A-1 , a plurality of first conductors 34 are formed on a portion of the electrode pad 210 of each first electronic element 21 by electroplating copper pillars.

In this embodiment, the height of the first conductor 34 relative to the first electronic element 21 is equal to the height of the second electronic element 22 relative to the first electronic element 21, that is, the two are coplanar in the height direction (such as the imaginary plane S shown in FIG. 3A ).

As shown in FIG. 3B , the encapsulation layer 23 is formed on the metal layer 91 of the carrier plate 9 so that the encapsulation layer 23 encapsulates the first electronic components 21, the second electronic components 22 and the first conductor 34.

In this embodiment, the first conductor 34 and the second electronic element 22 are not exposed on the first surface 23a of the encapsulation layer 23.

As shown in FIG. 3C , a plurality of blind holes 230 are formed on the first surface 23a of the cladding layer 23 so that the first conductors 34 and the electrode pads 220 of the second electronic element 22 are exposed in the blind holes 230 .

In this embodiment, the blind holes 230 are formed by laser, and since the first conductor 34 and the second electronic element 22 are coplanar in the height direction, the depths of the blind holes 230 are the same.

As shown in FIG. 3D , a wiring layer 351 is formed on the first surface 23a of the cladding layer 23, and conductive blind holes electrically connecting the first conductors 34 and the electrode pads 220 are formed in the blind holes 230 to serve as the second conductors 34a, 34b, so that the wiring layer 351 is electrically connected to the second conductors 34a, 34b.

In this embodiment, the first conductor 34 and the second conductor 34a are formed on the electrode pad 210 of the first electronic element 21, and the second conductor 34b is formed on the electrode pad 220 of the second electronic element 22.

Furthermore, the wiring layer 351 and the second conductors 34a, 34b are made by electroplating copper, so the wiring layer 351 and the second conductors 34a, 34b can be made together, so that the wiring layer 351 and the second conductors 34a, 34b are formed in one piece.

Furthermore, since the first conductor 34 and the second electronic element 22 are not exposed on the first surface 23a of the cladding layer 23, the second conductors 34a and 34b need to be formed. It should be understood that if the first conductor 34 and the second electronic element 22 are flush with the first surface 23a of the cladding layer 23, it is not necessary to form the second conductors 34a and 34b, so that the wiring layer 351 can contact and electrically connect the first conductors 34 and the electrode pads 220.

In addition, in other embodiments, the first conductor 34 may be omitted, but the depth of the conductive blind hole needs to be increased so that part of the second conductor 34a can be connected to the electrode pad 210 of the first electronic element 21.

As shown in FIG. 3E , the wiring layer 251 and the insulating layer 250 are continuously fabricated on the wiring layer 351 and the first surface 23a of the cladding layer 23 to form a wiring structure 35, and then the wiring structure 26, 27, the circuit structure 28 and the conductive via 29 are fabricated, and the conductive via 29 is electrically connected to the wiring layer 261, 262, the wiring layer 351, the wiring layer 271, 272 and the circuit layer 281.

In this embodiment, the wiring structures 26, 27, the circuit structure 28 and the conductive via 29 are manufactured using the process shown in FIG. 2C to FIG. 2G.

Therefore, in the manufacturing method of the electronic package 3 of the present invention, the depth of the second conductor 34a, 34b is reduced mainly by designing the first conductor 34. Therefore, compared with the prior art, before forming the blind hole 230, the first surface 23a of the cladding layer 23 of the electronic package 3 of the present invention does not need to be polished to flatten the process, which can ensure that the laser drilling can accurately burn the cladding layer 23 to expose the first conductor 34 and the electrode pad 220.

Furthermore, by stacking the first and second electronic components 21, 22 in the coating layer 23, the electronic package 3 can meet the multifunctional requirements and reduce the area of the first surface 23a or the second surface 23b of the coating layer 23, so as to facilitate the miniaturization of the electronic package 3.

Furthermore, since the wiring structures 35, 26, 27 and the circuit structure 28 are all coreless, it is beneficial to thin the electronic package 3.

In addition, by using PP material as the dielectric layer 280, the toughness of the circuit structure 28 is improved, so after removing the support member 8, the electronic package 3 will not warp during the manufacturing process.

Figures 4A to 4E are cross-sectional schematic diagrams of the manufacturing method of the third embodiment of the electronic package 4 of the present invention. The difference between this embodiment and the first embodiment is that the manufacturing process of other wiring structures is simplified and the position of the circuit structure 48 is changed. The other manufacturing processes are roughly the same, so the similarities will not be repeated below.

As shown in FIG. 4A , a plurality of packaging modules 2b as shown in FIG. 2D are provided, and then the packaging modules 2b are pressed on opposite sides of the support member 8 .

In this embodiment, the metal layers 91, 92 are made into a single wiring layer 261, 271, that is, the packaging module 2b is combined with the support member 8 by its wiring structure 25.

Furthermore, if the support member 8 is made of a soft material such as a thermal release film, the wiring layer 271 can be pressed into the support member 8, and the wiring layer 261 is exposed.

As shown in FIG. 4B , a circuit structure 48 is formed on the second surface 23b of the encapsulation layer 23 and the wiring layer 261 of each package module 2b.

In this embodiment, the circuit structure 48 includes at least one dielectric layer 480 formed on the cladding layer 23 and the wiring layer 261 and at least one circuit layer 481 disposed on the dielectric layer 480 and electrically connected to the wiring layer 261.

As shown in FIG. 4C , the support member 8 is removed, and at least one conductive via 29 is formed to penetrate the wiring structure 25, the coating layer 23, the wiring layers 261, 271, and the circuit structure 48, so that the conductive via 29 is electrically connected to the wiring layers 261, 271 and the circuit layer 481.

In this embodiment, after the circuit structure 48 is fabricated, the support member 8 may be heated to remove the support member 8.

Furthermore, the manufacturing process of the conductive via 29 is to first form a via that penetrates the wiring structure 25, the cladding layer 23, the wiring layers 261, 271 and the circuit structure 48, and then form a metal material in the via to serve as the conductive via 29.

As shown in FIG. 4D , an insulating protective layer 47 like a solder mask is formed on the wiring structure 25 on the first surface 23a of the cladding layer 23, and the insulating protective layer 47 has a plurality of openings 470 exposing the wiring layer 271.

As shown in FIG. 4E , a plurality of conductive bumps 472 electrically connected to the wiring layer 271 are formed in the openings 470 .

In this embodiment, the number of the wiring layer 271 (or RDL) on the first surface 23a of the cladding layer 23 can be designed according to the requirements and is not limited to one layer.

Furthermore, the electronic package 4 can be applied to chip level of system (CLoS) packaging. For example, the first and second electronic components 21, 22 can be logic chips (Logic Die), micro-electromechanical system (MEMS) components, SOC (system on chip) types or other types.

Furthermore, the electronic package 4 uses the side of the second surface 23b of the encapsulation layer 23 as the mounting side, and uses the side of the first surface 23a of the encapsulation layer 23 as the chip placement side. Therefore, in the subsequent process, as shown in FIG. 4F, a plurality of conductive elements 630 such as solder bumps can be formed on the conductive bumps 472 on the wiring layer 271 on the first surface 23a of the encapsulation layer 23, so as to connect at least one functional element 63 to these conductive elements 630, and a plurality of solder balls 600 can be formed on the circuit layer 481 on the outermost side of the circuit structure 48 on the second surface 23b of the encapsulation layer 23, so that the electronic package 4 is placed on a circuit board 60 through these solder balls 600.

The functional element 63 is an active element, a passive element or a combination of the two, and the active element is, for example, a semiconductor chip, and the passive element is, for example, a resistor, a capacitor and an inductor. In this embodiment, the functional element 63 is a semiconductor chip, which is disposed on the wiring structure 26 in a flip-chip manner through the conductive elements 630, so that the functional element 63 is electrically connected to the wiring layer 271 through the conductive elements 630 and the conductive bumps 472.

In addition, at least one other functional element 62a may be stacked on the functional element 63, such as a plurality of functional elements 62a stacked by conductive elements 620 such as solder bumps to form a functional module 62. For example, the functional element 62a of the functional module 62 may be a semiconductor chip, a dynamic random access memory (DRAM), a graphics processing unit (GPU), a high bandwidth memory (HBM), an application specific integrated circuit (ASIC) or other types of functional chips, and each of the functional elements 62a, 63 has at least one conductive through silicon via (TSV) 621, 631 to electrically connect the conductive elements 620, 630.

Therefore, in the manufacturing method of the electronic package 4 of the present invention, the first and second electronic components 21, 22 are stacked in the coating layer 23, so that the electronic package 4 meets the multi-functional requirements and can reduce the area of the first surface 23a or the second surface 23b of the coating layer 23, so as to facilitate the miniaturization of the electronic package 4.

Furthermore, by using the bonding wire 24 used in the wire bonding process as the conductor 24a, 24b and embedding it in the coating layer 23, the conventional processes of conducting posts such as laser drilling and electroplating copper posts are omitted. Therefore, compared with conventional techniques, the manufacturing method of the present invention can simplify the manufacturing process and greatly save the manufacturing cost of the electronic package 4.

Furthermore, since both the wiring structure 25 and the circuit structure 48 are coreless, it is convenient to thin the electronic package 4.

In addition, by using PP material as the dielectric layer 480, the toughness of the circuit structure 48 is improved, so after removing the support 8, the electronic package 4 will not warp during the manufacturing process.

Figures 5A and 5B are cross-sectional schematic diagrams of the manufacturing method of the fourth embodiment of the electronic package 5 of the present invention. The difference between this embodiment and the third embodiment lies in the form of the conductor, and the other processes are roughly the same, so the similarities will not be repeated below.

As shown in FIG. 5A , the electronic package 5 uses the first conductor 34 and the second conductor 34a, 34b described in the second embodiment to replace the conductors 24a, 24b of the third embodiment.

In this embodiment, an insulating protective layer 47 like a solder mask can be formed on the wiring structure 35 on the first surface 23a of the cladding layer 23, and the insulating protective layer 47 has a plurality of openings 470 exposing the wiring layer 271, so as to form a plurality of conductive bumps 472 electrically connected to the wiring layer 271 in the openings 470. It should be understood that the number of the wiring layers 351, 271 (or RDL) on the first surface 23a of the cladding layer 23 can be designed according to demand and is not limited to one layer.

Furthermore, the electronic package 5 uses the second surface 23b of the encapsulation layer 23 as the mounting side, and the first surface 23a of the encapsulation layer 23 as the die placement side. Therefore, in the subsequent manufacturing process, as shown in FIG. 5B , the functional element 63 and the functional module 62 can be arranged on the die placement side, and the electronic package 5 is disposed on a circuit board 60 with its mounting side through a plurality of solder balls 600.

Therefore, in the manufacturing method of the electronic package 5 of the present invention, the depth of the second conductor 34a, 34b is reduced mainly by designing the first conductor 34. Therefore, compared with the prior art, the first surface 23a of the cladding layer 23 of the electronic package 5 of the present invention does not need to be polished before forming the blind hole 230.

Furthermore, by stacking the first and second electronic components 21, 22 in the coating layer 23, the electronic package 5 can meet the multifunctional requirements and reduce the area of the first surface 23a or the second surface 23b of the coating layer 23, so as to facilitate the miniaturization of the electronic package 5.

Furthermore, since both the wiring structure 35 and the circuit structure 48 are coreless, it is convenient to thin the electronic package 5.

In addition, by using PP material as the dielectric layer 480, the toughness of the circuit structure 48 is improved, so after removing the support 8, the electronic package 5 will not warp during the manufacturing process.

The present invention also provides an electronic package 2, 3, 4, 5, which includes: a coating layer 23, a first electronic component 21, a second electronic component 22, a plurality of conductors 24a, 24b (first and second conductors 34, 34a, 34b), a wiring structure 25, 27, 35, a circuit structure 28, 48 and at least one conductive via 29.

The coating layer 23 has a first surface 23a and a second surface 23b opposite to each other.

The first electronic element 21 is embedded in the encapsulation layer 23.

The second electronic component 22 is embedded in the encapsulation layer 23 and stacked on the first electronic component 21.

The conductors 24a, 24b (first and second conductors 34, 34a, 34b) are embedded in the cladding layer 23 and electrically connected to the first electronic element 21 and the second electronic element 22, respectively, so that the plurality of conductors 24a, 24b (first and second conductors 34, 34a, 34b) are flush with the first surface 23a of the cladding layer 23.

The wiring structures 25, 27, 35 are disposed on the first surface 23a of the cladding layer 23, wherein the wiring structures 25, 27, 35 include at least one insulating layer 250, 270 formed on the cladding layer 23, and wiring layers 251, 271, 351 that are combined with the insulating layers 250, 270 and electrically connected to the conductors 24a, 24b (the first and second conductors 34, 34a, 34b), and the insulating layers 250, 270 are a Mirin layering film.

The circuit structure 28, 48 is disposed on the wiring structure 25, 27, 35 or on the second surface 23b of the cladding layer 23, wherein the circuit structure 28, 48 includes at least one dielectric layer 280, 480 and a circuit layer 281, 481 combined with the dielectric layer 280, 480, and the material forming the dielectric layer 280, 480 is different from the material forming the insulating layer 250, 270.

The conductive vias 29 penetrate the cladding layer 23, the insulating layers 250, 270 and the dielectric layers 280, 480 and electrically connect the wiring layers 271, 351 and the circuit layers 281, 481.

In one embodiment, the conductors 24a, 24b are wires in the form of welding wires.

In one embodiment, the first and second conductors 34, 34a include a column disposed on the first electronic element 21 and a conductive blind hole connected to the column.

In one embodiment, the second conductor 34b is a conductive blind hole provided on the second electronic element 22.

In summary, the electronic package and its manufacturing method of the present invention stack the first and second electronic components in the coating layer, so that the electronic package meets the multi-functional requirements and can reduce the surface area of the coating layer, so as to facilitate the miniaturization of the electronic package.

Furthermore, since both the wiring structure and the circuit structure are in the form of a core-less structure, it is beneficial to thin the electronic package.

In addition, the configuration of the dielectric layer is different from that of ABF to enhance the toughness of the circuit structure, so the electronic package will not warp during the manufacturing process.

In addition, by designing the first conductor, the depth of the second conductor is reduced. Therefore, before forming the blind hole, the first surface of the coating layer of the electronic package of the second and fourth embodiments of the present invention does not need to undergo a polishing process to flatten the process, thereby simplifying the process and reducing the manufacturing cost.

The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Anyone familiar with this technology can modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application described below.

2: Electronic packaging components

20: Binding layer

21: First electronic component

210,220:Electrode pad

22: Second electronic component

23: Coating layer

23a: First surface

23b: Second surface

24a,24b: Conductor

25,26,27: Wiring structure

250,260,270: Insulation layer

251,261,262,271,272: Wiring layer

28:Line structure

280: Dielectric layer

281: Line layer

29:Conductive perforation

Claims (5)

A method for manufacturing an electronic package includes: embedding a first electronic component and a second electronic component in a coating layer, wherein the coating layer has a first surface and a second surface opposite to each other, and the second electronic component is stacked on the first electronic component, and the active surfaces of the first electronic component and the second electronic component correspond to the first surface of the coating layer, and forming a plurality of conductors electrically connected to the first electronic component and the second electronic component on the first electronic component and the second electronic component, respectively, so that the plurality of conductors are flush with the first surface of the coating layer; forming a wiring connection A wiring structure is formed on the first surface of the coating layer, and the wiring structure includes at least one insulating layer formed on the coating layer, and a wiring layer combined with the insulating layer and electrically connected to the conductor, and the insulating layer is a Mikoto build-up film; a wiring structure is formed on the wiring structure, and the wiring structure includes at least one dielectric layer and a wiring layer combined with the dielectric layer, and the material forming the dielectric layer is different from the material forming the insulating layer; and at least one conductive through-hole is formed that penetrates the coating layer, the insulating layer and the dielectric layer, and the conductive through-hole is electrically connected to the wiring layer and the wiring layer. A method for manufacturing an electronic package includes: embedding a first electronic component and a second electronic component in a coating layer, wherein the coating layer has a first surface and a second surface opposite to each other, and the second electronic component is stacked on the first electronic component, and the active surfaces of the first electronic component and the second electronic component correspond to the first surface of the coating layer, and forming a plurality of conductors electrically connected to the first electronic component and the second electronic component on the first electronic component and the second electronic component respectively, so that the plurality of conductors are aligned with the first surface of the coating layer; forming a wiring structure On the first surface of the coating layer, the wiring structure includes at least one insulating layer formed on the coating layer, and a wiring layer combined with the insulating layer and electrically connected to the conductor, and the insulating layer is a Mikoto-added film; a circuit structure is formed on the second surface of the coating layer, the circuit structure includes at least one dielectric layer, and a circuit layer combined with the dielectric layer, and the material forming the dielectric layer is different from the material forming the insulating layer; and at least one conductive perforation is formed that penetrates the coating layer, the insulating layer and the dielectric layer, and the conductive perforation is electrically connected to the wiring layer and the circuit layer. A method for manufacturing an electronic package as described in claim 1 or 2, wherein the conductive body is a conductive wire in the form of a welding wire. A method for manufacturing an electronic package as described in claim 1 or 2, wherein the conductive body comprises a column disposed on the first electronic component and a conductive blind hole connected to the column. A method for manufacturing an electronic package as described in claim 1 or 2, wherein the conductive body is a conductive blind hole provided on the second electronic component.

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