TWI901389B - Double-side packaging chip carrier and double-side packaging structure using the same - Google Patents

Abstract

A double-side packaging chip carrier includes a base layer, a first circuit layer, a plurality of first protective layers and a plurality of second circuit layers, a second protective layer, a third circuit layer, a third protective layer, a fourth circuit layer, The first solder mask layer and the second solder mask layer. The first circuit layer includes first chip contacts. The first protective layers and the second circuit layers are sequentially stacked on the first circuit layer. The third circuit layer includes the second chip contacts. The third protective layer and the base layer have a groove exposing the first chip contacts. The fourth circuit layer is on the third protective layer and has a plurality of soldering contacts. The first solder mask layer is on the fourth circuit layer but exposes the soldering contacts. The second solder mask layer is on the third circuit layer but exposes the second chip contact. The thickness of the double-side packaging chip carrier is greater than 250 μm, and the depth of the groove is greater than 100 μm.

Description

Double-sided package chip carrier and double-sided chip package structure using the same

The present invention relates to the field of chip packaging, and in particular to a double-sided package chip carrier and a double-sided chip packaging structure using the same.

As chip sizes shrink, products become thinner and lighter, while performance improves. Current chip packaging technology typically utilizes double-sided packaging, using a ball grid array (BGA) to arrange signal input/output locations in an array. However, recent chip packaging technologies have resulted in thicker chips, creating a bottleneck for BGAs.

Because ball grid arrays are soldered with solder balls, increasing package height often requires padding at the solder joints. Due to the surface properties of solder, padding the solder balls by pouring solder increases the overall size, increasing the spherical shape of the solder, necessitating a larger pitch between the solder balls. This, in turn, hinders increasing the number of I/Os and overall chip density. While existing methods employ copper pillars, these require the addition of high-resolution, thick photosensitive dry film resists and peeling films, significantly increasing manufacturing costs and labor.

To address the aforementioned problem, a double-sided package chip carrier is provided. The double-sided package chip carrier includes a base layer, a first circuit layer, a plurality of first protection layers, a plurality of second circuit layers, a second protection layer, a third circuit layer, a third protection layer, a fourth circuit layer, a first solder barrier layer, and a second solder barrier layer.

A first circuit layer is located on the first surface of the base layer and includes a plurality of first chip contacts. A plurality of first protective layers and a plurality of second circuit layers are sequentially stacked on the first circuit layer. Each first protective layer has a first connection opening. The first connection openings connect the two second circuit layers, as well as the bottommost second circuit layer and the first circuit layer. A second protective layer is located on the topmost second circuit layer and includes a second connection opening. A third circuit layer is connected to the topmost second circuit layer through the second connection opening, wherein the third circuit layer includes a plurality of second chip contacts.

The third protective layer is located on the second surface of the base layer. The third protective layer and the base layer have a third connecting opening and a groove that are connected. The groove exposes the first chip contact. The fourth circuit layer is located on the third protective layer and is connected to the first circuit layer through the third connecting opening. The fourth circuit layer has a plurality of solder joints. The first solder barrier layer is located on the fourth circuit layer and has a plurality of first solder barrier openings. The first solder barrier openings expose the solder joints. The second solder barrier layer is located on the third circuit layer and has a second solder barrier groove. The second solder barrier groove exposes the second chip contact. The thickness of the double-sided package chip carrier is greater than 250μm, and the depth of the groove is greater than 100μm.

In some embodiments, a first spacing between the first chip contacts is smaller than a second spacing between the solder contacts. More specifically, in some embodiments, the first spacing is 90 to 180 μm. Further, in some embodiments, the first spacing is 100 to 160 μm.

In some embodiments, the total number of the first wiring layer, the second wiring layers, the third wiring layer, and the fourth wiring layer is greater than nine.

In some embodiments, the third circuit layer further includes a plurality of connection contacts, and the second solder-proof layer further includes a third solder-proof slot, wherein the third solder-proof slot exposes a portion of the connection contacts.

A double-sided chip package structure is provided. The double-sided chip package structure includes a double-sided chip carrier, a first chip, and a second chip. The double-sided chip carrier includes a base layer, a first circuit layer, a plurality of first protective layers, a plurality of second circuit layers, a second protective layer, a third circuit layer, a third protective layer, a fourth circuit layer, a first solder barrier layer, and a second solder barrier layer.

A first circuit layer is located on the first surface of the base layer and includes a plurality of first chip contacts. A plurality of first protective layers and a plurality of second circuit layers are sequentially stacked on the first circuit layer. Each first protective layer has a first connection opening. The first connection openings connect the two second circuit layers, as well as the bottommost second circuit layer and the first circuit layer. A second protective layer is located on the topmost second circuit layer and includes a second connection opening. A third circuit layer is connected to the topmost second circuit layer through the second connection opening, wherein the third circuit layer includes a plurality of second chip contacts.

The third protective layer is located on the second surface of the base layer. The third protective layer and the base layer have a third connecting opening and a groove that are connected. The groove exposes the first chip connection. The fourth circuit layer is located on the third protective layer and is connected to the first circuit layer through the third connecting opening. The fourth circuit layer has a plurality of solder joints. The first solder prevention layer is located on the fourth circuit layer and has a plurality of first solder prevention openings. The first solder prevention openings respectively expose the solder joints. The second solder prevention layer is located on the third circuit layer and has a second solder prevention groove. The second solder prevention groove exposes the second chip connection. The thickness of the double-sided package chip carrier is greater than 250μm, and the depth of the groove is greater than 100μm. The first chip is soldered to the first chip connection. The second chip is soldered to the second chip contact.

In some embodiments, a first spacing between the first chip contacts is smaller than a second spacing between the solder contacts. More specifically, in some embodiments, the first spacing is 90 to 180 μm. Further, in some embodiments, the first spacing is 100 to 160 μm.

In some embodiments, the double-sided chip package structure further includes a first packaging layer and a second packaging layer. The first packaging layer covers the first chip, the first chip contact, and the second surface of the base layer. The second packaging layer covers the second chip, the second chip contact, and the second solder barrier layer.

More specifically, in some embodiments, the third circuit layer further includes a plurality of connection contacts, and the second solder-proof layer further includes a third solder-proof slot, wherein the third solder-proof slot exposes a portion of the connection contacts.

Furthermore, in some embodiments, the double-sided chip package structure further includes a passive component connected to the connection pad, and the second packaging layer further covers the passive component.

As shown in the aforementioned embodiments, by disposing the first chip contacts in the first circuit layer and forming a location for accommodating the chip by means of back-grooving, the thickness of the chip carrier and the spacing between the solder contacts can be maintained. At the same time, the number of solder contacts per unit area, i.e., the number of input/output (I/O), can be increased, which can be applied to high-chip density precision packaging.

It should be understood that when an element is referred to as being "disposed on" or "connected to" another element, this may mean that the element is directly located on the other element, or that an intervening element is present, connecting the element to the other element. Conversely, when an element is referred to as being "directly disposed on/connected to" or "directly disposed/connected to" another element, it should be understood that this clearly defines the absence of intervening elements.

In addition, the terms "first," "second," and "third" are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part, and do not necessarily indicate a sequence of precedence or sequence. Furthermore, relative terms such as "lower" and "upper" may be used herein to describe the relationship of one element to another, and it should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if a device in an accompanying figure is turned over, an element described as being on the "lower" side of other elements would be oriented on the "upper" side of the other elements. This only indicates a relative orientation relationship, not an absolute orientation relationship.

Figure 1 is a schematic cross-sectional view of an embodiment of a double-sided package chip carrier. As shown in Figure 1 , the double-sided package chip carrier 1 includes a base layer 11, a first circuit layer 21, a plurality of first protection layers 13, a plurality of second circuit layers 23, a second protection layer 15, a third circuit layer 25, a third protection layer 31, a fourth circuit layer 33, a first solder barrier layer 41, and a second solder barrier layer 43.

The first wiring layer 21 is located on the first surface 11A of the substrate layer 11 and includes a plurality of first chip contacts 211. A plurality of first protection layers 13 and a plurality of second wiring layers 23 are sequentially stacked on the first wiring layer 21. Each first protection layer 13 has a first connection opening 131. The first connection openings 131 connect the two layers of the second wiring layer 23 and the bottommost layer of the second wiring layer 23 to the first wiring layer 21. The second wiring layer 23 can be a redistribution layer (RDL), and each second wiring layer 23 can have a different wiring layout. The second protection layer 15 is located on the topmost second wiring layer 23 and has a second connection opening 151. The third circuit layer 25 is connected to the uppermost second circuit layer 23 through the second connecting opening 151 , wherein the third circuit layer 25 includes a plurality of second chip contacts 251 .

The third protective layer 31 is located on the second surface 11B of the base layer 11. The third protective layer 31 and the base layer 11 are interconnected by a third connecting opening 311 and a groove 313. The groove 313 exposes the first chip contact 211. The fourth circuit layer 33 is located on the third protective layer 31 and is connected to the first circuit layer 21 through the third connecting opening 311. The fourth circuit layer 33 has a plurality of solder contacts 331. Here, the fourth wiring layer 33 can also be multiple layers, and the base layer 11 can also have a single connecting opening. After the fourth wiring layer 33 is formed on the base layer 11, it is connected to the first wiring layer 21 through the opening. Furthermore, after the third protection layer 31 and the fourth wiring layer 33 are provided, the fourth wiring layer 33 is further connected to the underlying fourth wiring layer 33 through the connecting opening. The above is merely an example and is not intended to be limiting. The actual configuration will depend on the specifications and layout.

The first solder barrier layer 41 is located on the fourth circuit layer 33 and has a plurality of first solder barrier openings 411 that expose the soldering contacts 331. The second solder barrier layer 43 is located on the third circuit layer 25 and has second solder barrier grooves 431 that expose the second chip contacts 251.

Here, the thickness of the double-sided package chip carrier 1 is greater than 250μm, and the depth of the groove 313 is greater than 100μm. The deeper groove 313 can accommodate more chips, limiting the impact of the overall thickness and not affecting the layout of the solder contacts 331. This can provide more I/O layouts per unit area, thereby facilitating increased chip density.

In some embodiments, the first spacing P1 between the first chip contacts 211 is smaller than the second spacing P2 between the solder contacts 331. More specifically, in some embodiments, the first spacing P1 is 90 to 180 μm. Furthermore, in some embodiments, the first spacing P1 is 100 to 160 μm.

In some embodiments, the total number of first wiring layer 21, second wiring layers 23, third wiring layer 25, and fourth wiring layer 33 is greater than nine, for example, 11 layers. Considering the chip height, the number of third protection layer 31 and fourth wiring layer 33 can be increased to increase circuit density while minimizing the impact on chip thickness.

In some embodiments, the third circuit layer 25 further includes a plurality of connection contacts 253, and the second solder-proof layer 43 further includes a third solder-proof slot 433. The third solder-proof slot 433 exposes a portion of the connection contacts 253 while providing sufficient width.

Figure 2 is a schematic cross-sectional view of an embodiment of a double-sided chip package structure. As shown in Figure 2 , and with reference to Figure 1 , double-sided chip package structure 100 utilizes the double-sided chip carrier 1 of Figure 1 for packaging. Repeated descriptions are omitted. As shown in Figure 2 , double-sided chip package structure 100 includes double-sided chip carrier 1, a first chip 51, and a second chip 53. The first chip 51 is soldered to the first chip contact 211. The second chip 53 is soldered to the second chip contact 251. Here, by disposing the first chip contacts 211 in the first circuit layer 21 and forming a back-facing groove 313 to accommodate the first chip 51, the thickness of the double-sided package chip carrier 1 and the pitch of the soldering contacts 331 can be maintained. At the same time, the number of soldering contacts 331 per unit area, i.e., the number of input/output (I/O) points, can be increased, which can be applied to high-chip density precision packaging.

Furthermore, in some embodiments, the double-sided chip package structure 100 further includes a first packaging layer 61 and a second packaging layer 63. The first packaging layer 61 covers the first chip 51, the first chip contact 211, the second surface 11B of the base layer 11, and the first solder barrier layer 41. The second packaging layer 63 covers the second chip 53, the second chip contact 251, and the second solder barrier layer 43. After packaging, the first and second packaging layers 61 and 63 prevent exposure of the first and second chips 51 and 53 and the first and second chip contacts 211 and 251, thereby reducing oxidation caused by the external environment and affecting electrical properties. After the first and second packaging layers 61 and 63 are completed, the overall thickness increases by less than 120 μm. In addition, the first packaging layer 61 and the second packaging layer 63 can both be made of anti-soldering materials, that is, they cover the first anti-soldering layer 41 and the second anti-soldering layer 43 without affecting the anti-soldering protection.

More specifically, in some embodiments, in embodiments having connection contacts 253 and third anti-welding slots 433, the double-sided chip package structure 100 further includes a passive component 70, which is connected to the connection contacts 253, for example, by being connected to a portion of the two connection contacts 253 in a bridging manner. Furthermore, the second packaging layer 63 further covers the passive component 70. Furthermore, the connection contacts 253 can be directly soldered using solder balls (not shown), eliminating the need for other methods to achieve a raised surface. Furthermore, solder balls 80 can also be placed in the first anti-welding slots 411 to assist in overall electrical connection.

In summary, by disposing the first chip contacts 211 in the first circuit layer 21 and forming a position for accommodating the first chip 51 by means of a back-grooved pattern, it is possible to maintain the double-sided packaging of the chip carrier 1 and the gap between the connection contacts 253. At the same time, the number of connection contacts 253 per unit area, i.e., the number of input/output (I/O), can be increased. This can be applied to high-chip density precision packaging and saves costs and labor hours.

Although the technical contents of the present invention have been disclosed above with reference to the preferred embodiments, they are not intended to limit the present invention. Any slight changes and modifications made by anyone skilled in the art without departing from the spirit of the present invention should be included within the scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

1: Double-Sided Chip Carrier 11: Base Layer 11A: First Surface 11B: Second Surface 13: First Protective Layer 131: First Connection Opening 15: Second Protective Layer 151: Second Connection Opening 21: First Circuit Layer 211: First Chip Contact 23: Second Circuit Layer 25: Third Circuit Layer 251: Second Chip Contact 253: Connecting Contact 31: Third Protective Layer 311: Third Connection Opening 313: Slot 33: Fourth Circuit Layer 331: Solder Contact 41: First Anti-Welding Layer 411: First Anti-Welding Opening 43: Second Anti-Welding Layer 431: Second soldering groove 433: Third soldering groove 51: First chip 53: Second chip 61: First packaging layer 63: Second packaging layer 70: Passive component 80: Solder ball 100: Double-sided chip package structure P1: First pitch P2: Second pitch

Figure 1 is a schematic cross-sectional view of an embodiment of a double-sided package chip carrier. Figure 2 is a schematic cross-sectional view of an embodiment of a double-sided chip package structure.

1: Double-sided package chip carrier

11: Basal layer

11A: First Surface

11B: Second surface

13: First protective layer

131: First connection opening

15: Second protective layer

151: Second connection opening

21: First Line Layer

211: First chip contact

23: Second circuit layer

25: Third Line Layer

251: Second chip contact

253: Connection point

31: Third protection layer

311: Third connection opening

313: Slotting

33: Fourth circuit layer

331: Soldering contacts

41: First solder barrier layer

411: First solder-proof opening

43: Second solder barrier layer

431: Second anti-weld slot

433: Third anti-weld slot

P1: First Pitch

P2: Second spacing

Claims (12)

A double-sided package chip carrier comprises: a base layer; a first circuit layer, located on a first surface of the base layer, comprising a plurality of first chip contacts; a plurality of first protection layers and a plurality of second circuit layers, stacked sequentially and repeatedly on the first circuit layer, the first protection layers having a first connecting opening, wherein two second circuit layers, as well as the bottommost of the second circuit layers, are connected to each other through the first connecting opening; a second protection layer, located on the topmost second circuit layer, having a second connecting opening; a third circuit layer, connected to the topmost second circuit layer through the second connecting opening, wherein the third circuit layer comprises a plurality of second chip contacts; a third protective layer disposed on a second surface of the base layer, the third protective layer and the base layer having a third connecting opening and a slot communicating with each other, the slot exposing the first chip contacts; a fourth circuit layer disposed on the third protective layer, connected to the first circuit layer through the third connecting opening, the fourth circuit layer having a plurality of soldering contacts, wherein a first spacing between the first chip contacts is less than a second spacing between the soldering contacts; a first solder prevention layer disposed on the fourth circuit layer, having a plurality of first solder prevention openings, the first solder prevention openings respectively exposing the soldering contacts; and A second solder barrier layer is located on the third circuit layer and has a second solder barrier groove, wherein the second solder barrier groove exposes the second chip contacts; wherein the thickness of the double-sided package chip carrier is greater than 250 μm, and the depth of the groove is greater than 100 μm. A double-sided package chip carrier as described in claim 1, wherein the first spacing is 90 to 180 μm. A double-sided package chip carrier as described in claim 2, wherein the first spacing is 100 to 160 μm. The double-sided package chip carrier as described in claim 1, wherein the total number of the first wiring layer, the second wiring layers, the third wiring layer and the fourth wiring layer is greater than nine. The double-sided package chip carrier as described in claim 1, wherein the third circuit layer further includes a plurality of connection contacts, and the second anti-welding layer further includes a third anti-welding groove, and the third anti-welding groove exposes a portion of the connection contacts. A double-sided chip package structure comprises: a double-sided package chip carrier comprising: a base layer; a first circuit layer, located on a first surface of the base layer, comprising a plurality of first chip contacts; a plurality of first protection layers and a plurality of second circuit layers, sequentially and repeatedly stacked on the first circuit layer, the first protection layers having a first connecting opening, the first connecting opening connecting two second circuit layers and the bottommost of the second circuit layers to the first circuit layer; a second protection layer, located on the topmost second circuit layer, having a second connecting opening; a third circuit layer connected to the uppermost second circuit layer through the second connecting opening, wherein the third circuit layer includes a plurality of second chip contacts; a third protective layer located on a second surface of the base layer, the third protective layer and the base layer having a plurality of third connecting openings and a slot that are connected, the slot exposing the first chip contacts; a fourth circuit layer located on the third protective layer, connected to the first circuit layer through the third connecting opening, and having a plurality of soldering contacts; a first solder-proof layer located on the fourth circuit layer, having a plurality of first solder-proof openings, the first solder-proof openings respectively exposing the soldering contacts; and a second solder barrier layer, located on the third circuit layer, having a second solder barrier groove, wherein the second solder barrier groove exposes the second chip contacts, wherein the thickness of the double-sided package chip carrier is greater than 250 μm, and the depth of the groove is greater than 100 μm; a first chip, soldered to the first chip contacts; and a second chip, soldered to the second chip contacts. A double-sided chip package structure as described in claim 6, wherein a first spacing between the first chip contacts is smaller than a second spacing between the solder contacts. The double-sided chip package structure as described in claim 7, wherein the first spacing is 90 to 180 μm. The double-sided chip package structure as described in claim 8, wherein the first spacing is 100 to 160 μm. The double-sided chip package structure as described in claim 6 further includes: a first packaging layer covering the first chip, the first chip contacts and the second surface of the base layer; and a second packaging layer covering the second chip, the second chip contacts and the second anti-welding layer. The double-sided chip package structure as described in claim 10, wherein the third circuit layer further includes a plurality of connection contacts, and the second anti-welding layer further includes a third anti-welding groove, and the third anti-welding groove exposes a portion of the connection contacts. The double-sided chip package structure as described in claim 11 further includes a passive component, which is connected to the connection points, and the second packaging layer further covers the passive component.