TWI884019B - Display device and manufacturing method of active device substrate - Google Patents

Abstract

A display device includes a substrate, a first correction mark, an insulating layer, a semiconductor layer, a gate dielectric layer, a gate electrode, an interlayer dielectric layer, a source electrode and a drain electrode. The substrate has a display area and a peripheral area surrounding the display area. The peripheral area includes an correction mark area, and the display area includes an active device area. The first correction mark is located above the correction mark area. The insulating layer is located above the substrate and extends from the active device area to the correction mark area. The insulating layer has an correction opening that overlaps the first correction mark. The semiconductor layer is located above the active device area. The insulating layer at least partially overlaps the semiconductor layer. The gate dielectric layer is located on the semiconductor layer and the correction opening.

Description

Display device and method for manufacturing active element substrate

The present invention relates to a display device and a manufacturing method of an active element substrate.

In many display devices, thin film transistors are used for signal processing. These thin film transistors may be set in the driving circuit or the pixel structure. Generally speaking, the electrode material layer and the semiconductor material layer are deposited by thin film deposition technology, and these electrode material layers and semiconductor material layers are patterned to obtain the electrode and semiconductor layers in the thin film transistor. Generally speaking, the patterning process is performed using a photoresist pattern as a mask. However, in the process of making the photoresist pattern, the formed photoresist pattern may deviate from the expected position due to alignment problems, thereby affecting the yield of the thin film transistor.

At least one embodiment of the present invention provides a method for manufacturing an active component substrate, comprising the following steps. An alignment mark and a first correction mark are formed on the alignment mark area and the correction mark area of the substrate, respectively. An insulating layer is formed to extend from the active component area of the substrate to the correction mark area. A semiconductor layer is formed on the active component area. A first photoresist pattern is formed on the semiconductor layer and the insulating layer according to the alignment mark. A first ion implantation process is performed on the semiconductor layer using the first photoresist pattern as a mask to form a first doping region in the semiconductor layer. The insulating layer is etched using the first photoresist pattern as a mask to form a correction opening in the insulating layer that overlaps the first correction mark. The first photoresist pattern is removed. A gate dielectric layer is formed on the semiconductor layer and the correction opening. A gate, an interlayer dielectric layer, a source and a drain are formed on the gate dielectric layer.

At least one embodiment of the present invention provides a method for manufacturing an active element substrate, comprising the following steps. An alignment mark and a first correction mark are formed on an alignment mark area and a correction mark area of the substrate, respectively. A buffer layer is formed to extend from the active element area of the substrate to the correction mark area. A semiconductor layer is formed on the buffer layer and on the active element area. An insulating layer is formed on the semiconductor layer and extends from the active element area of the substrate to the correction mark area. A first photoresist pattern is formed on the insulating layer according to the alignment mark. A first ion implantation process is performed on the semiconductor layer using the first photoresist pattern as a mask to form a first doping area in the semiconductor layer. The insulating layer is etched using the first photoresist pattern as a mask to form a correction opening in the insulating layer that overlaps the first correction mark. The first photoresist pattern is removed. A gate dielectric layer is formed on the semiconductor layer, the insulating layer and the correction opening. A gate, an interlayer dielectric layer, a source and a drain are formed on the gate dielectric layer.

At least one embodiment of the present invention provides a display device, which includes a substrate, a first correction mark, an insulating layer, a semiconductor layer, a gate dielectric layer, a gate, an interlayer dielectric layer, a source and a drain. The substrate has a display area and a peripheral area surrounding the display area. The peripheral area includes a correction mark area, and the display area includes an active component area. The first correction mark is located above the correction mark area. The insulating layer is located above the substrate and extends from the active component area to the correction mark area. The insulating layer has a correction opening overlapping the first correction mark. The semiconductor layer is located above the active component area. The insulating layer at least partially overlaps the semiconductor layer. A gate dielectric layer is located on the semiconductor layer and the correction opening. A gate, an interlayer dielectric layer, a source, and a drain are located on the gate dielectric layer.

FIG1 is a top view schematic diagram of a display device according to an embodiment of the present invention. Referring to FIG1 , a substrate 100 of the display device has a display area AA and a peripheral area PA surrounding the display area AA. The shape of the display area AA can be adjusted according to requirements, such as a rectangle, a circle, an ellipse or other suitable shapes.

An array of pixel structures is disposed on the display area AA, each pixel structure including an active element (e.g., a thin film transistor), a passive element (e.g., a capacitor), and other suitable elements. In some embodiments, the pixel structure further includes a display unit, such as a micro light emitting diode, an organic light diode, a liquid crystal medium, an electrophoretic medium, or other suitable elements.

Various circuit structures are arranged on the peripheral area PA, and these circuit structures are used, for example, to provide signals to the pixel structures on the display area AA. In the present embodiment, the peripheral area PA includes a correction mark area MR and an alignment mark area NR. The correction mark area MR is provided with marks used to detect/correct the exposure process in the process of manufacturing the display device. The alignment mark area NR is provided with marks used for alignment in the process of manufacturing the display device. The correction mark area MR and the alignment mark area NR can be located at any position in the peripheral area PA. In the present embodiment, the correction mark area MR is located at the four corners of the peripheral area PA, and the alignment mark area NR is located at the edge of the peripheral area PA, but the present invention is not limited to this. In other embodiments, the correction mark area MR and the alignment mark area NR can also be set at other positions.

FIG2 is a schematic cross-sectional view of a display device 10 (also referred to as an active element substrate) according to an embodiment of the present invention. FIG2 shows a portion of the display area AA and the peripheral area PA of FIG1. Referring to FIG2, the display device 10 includes a substrate 100, a first correction mark 112, an alignment mark 113, a light shielding layer 114, a first capacitor electrode 116, an insulating layer 120A, a semiconductor layer 132, a second capacitor electrode 134, a gate dielectric layer 140, a second correction mark 152, a gate 154, a third capacitor electrode 156, an interlayer dielectric layer 160, a source 172, a drain 174, and a display unit 180.

The substrate 100 has a display area AA and a peripheral area PA surrounding the display area AA (see FIG. 1 ). The peripheral area PA includes an alignment mark area NR and a correction mark area MR, and the display area AA includes an active device area TR and a capacitor area CR. The thin film transistor TFT and the capacitor C are respectively located on the active device area TR and the capacitor area CR. The alignment mark 113 is located on the alignment mark area NR. The first correction mark 112 and the second correction mark 152 are located on the correction mark area MR.

The thin film transistor TFT includes a light shielding layer 114, a semiconductor layer 132, a gate 154, a source 172, and a drain 174. The capacitor C includes a first capacitor electrode 116, a second capacitor electrode 134, and a third capacitor electrode 156.

The light shielding layer 114 and the first capacitor electrode 116 are located on the substrate 100. In this embodiment, the light shielding layer 114 and the first capacitor electrode 116 are separated from each other, but the present invention is not limited thereto. In other embodiments, the light shielding layer 114 and the first capacitor electrode 116 are connected.

The first calibration mark 112 and the alignment mark 113 are located on the substrate 100. In this embodiment, the first calibration mark 112, the alignment mark 113, the light shielding layer 114 and the first capacitor electrode 116 are separated from each other.

The insulating layer 120A is located on the substrate 100 and extends from the active device region TR and the capacitor region CR to the alignment mark region NR and the correction mark region MR. The insulating layer 120A surrounds the light shielding layer 114, the first capacitor electrode 116, the first correction mark 112, and the alignment mark 113. In this embodiment, the insulating layer 120A has a correction opening 122 and an alignment opening 123. The correction opening 122 is located on the correction mark region MR and overlaps the first correction mark 112. The alignment opening 123 is located on the alignment mark region NR and does not overlap the alignment mark 113. In some embodiments, the width of the correction opening 122 is greater than the width of the first correction mark 112, but the present invention is not limited thereto.

In this embodiment, the insulating layer 120A covers the top surface of the first calibration mark 112, the top surface of the alignment mark 113, the top surface of the light shielding layer 114, and the top surface of the first capacitor electrode 116. In other words, the first calibration mark 112, the alignment mark 113, the light shielding layer 114, and the first capacitor electrode 116 are located between the insulating layer 120A and the substrate 100. In other embodiments, the calibration opening 122 extends to the top surface of the first calibration mark 112, so that the insulating layer 120A does not cover the top surface of the first calibration mark 112.

The semiconductor layer 132 and the second capacitor electrode 134 are respectively located on the active device region TR and the capacitor region CR. The insulating layer 120A at least partially overlaps the semiconductor layer 132. In this embodiment, the insulating layer 120A overlaps the semiconductor layer 132 and the second capacitor electrode 134, and the insulating layer 120A is located between the semiconductor layer 132 and the substrate 100 and between the second capacitor electrode 134 and the substrate 100. In some embodiments, the insulating layer 120A has a groove 124 overlapping the sidewall of the semiconductor layer 132. In some embodiments, one sidewall of the semiconductor layer 132 overlaps with the groove 124, while the other sidewall does not overlap with the groove 124. In addition, in some embodiments, the sidewall of the second capacitor electrode 134 also overlaps with the groove 124.

The semiconductor layer 132 includes a first doped region 132a, a second doped region 132b, a lightly doped region 132c, and a channel region 132d. The lightly doped region 132c and the channel region 132d are located between the first doped region 132a and the second doped region 132b. The lightly doped region 132c is located between the channel region 132d and the second doped region 132b, and the channel region 132d is located between the first doped region 132a and the lightly doped region 132c. In the semiconductor layer 132, the channel region 132d has a lower doping concentration (or is not doped) and has the highest resistivity. The first doped region 132a and the second doped region 132b have a higher doping concentration (also referred to as a heavily doped region) and have the lowest resistivity. The doping concentration of the lightly doped region 132c is lower than the doping concentration of the first doped region 132a and the second doped region 132b, and the resistivity of the lightly doped region 132c is higher than the resistivity of the first doped region 132a and the second doped region 132b. In addition, in some embodiments, the doping concentration of the first doped region 132a is equal to or different from the doping concentration of the second doped region 132b.

The second capacitor electrode 134 overlaps the first capacitor electrode 116, and a portion of the insulating layer 120A is located between the second capacitor electrode 134 and the first capacitor electrode 116. The doping concentration of the second capacitor electrode 134 is, for example, substantially the same as the doping concentration of the first doping region 132a, and both have similar resistivity.

The gate dielectric layer 140 is located on the semiconductor layer 132, the second capacitor electrode 134 and the insulating layer 120A. In this embodiment, the gate dielectric layer 140 is located on the correction opening 122, the alignment opening 123 and the groove 124 of the insulating layer 120A and fills the correction opening 122, the alignment opening 123 and the groove 124.

The second alignment mark 152 , the gate 154 , and the third capacitor electrode 156 are located on the gate dielectric layer 140 .

The second alignment mark 152 overlaps the alignment opening 122 and the first alignment mark 112. In some embodiments, a portion of the gate dielectric layer 140 and a portion of the insulating layer 120A are located between the first alignment mark 112 and the second alignment mark 152.

The gate 154 overlaps the channel region 132d and a portion of the first doped region 132a of the semiconductor layer 132. For example, the first doped region 132a has a second portion 132a-2 close to the channel region 132d and a first portion 132a-1 away from the channel region 132d, wherein the gate 154 overlaps the second portion 132a-2 and does not overlap the first portion 132a-1. A portion of the gate dielectric layer 140 is located between the gate 154 and the semiconductor layer 132.

The third capacitor electrode 156 overlaps the second capacitor electrode 134 and the first capacitor electrode 116. A portion of the gate dielectric layer 140 is located between the second capacitor electrode 134 and the third capacitor electrode 156.

The interlayer dielectric layer 160 is located on the gate 154, the third capacitor electrode 156 and the gate dielectric layer 140, and covers the gate 154 and the third capacitor electrode 156. In this embodiment, the interlayer dielectric layer 160 also covers the second correction mark 152, but the present invention is not limited thereto. In other embodiments, the interlayer dielectric layer 160 does not cover the second correction mark 152.

The source 172 and the drain 174 are located on the gate dielectric layer 140. In the present embodiment, the source 172 and the drain 174 are located on the interlayer dielectric layer 160 and are connected to the semiconductor layer 132 through vias in the interlayer dielectric layer 160 and the gate dielectric layer 140. One of the source 172 and the drain 174 is connected to the first doped region 132a, and the other is connected to the second doped region 132b. For example, the drain 174 is connected to the first doped region 132a, and the source 172 is connected to the second doped region 132b. In other embodiments, the source 172 is connected to the first doped region 132a, and the drain 174 is connected to the second doped region 132b.

The display unit 180 is electrically connected or electrically coupled to the active element TFT. For example, the display unit 180 is electrically connected or electrically coupled to one of the source 172 and the drain 174. In some embodiments, the display unit 180 is, for example, a micro light-emitting diode, an organic light-emitting diode, a liquid crystal medium, an electrophoretic display medium, or other suitable elements. In some embodiments, other conductive structures may be included between the display unit 180 and the active element TFT, but the present invention is not limited thereto.

3A to 3O are cross-sectional views of various stages of manufacturing the display device 10 of FIG2. Referring to FIG3A, a first calibration mark 112, an alignment mark 113, a light shielding layer 114 and a first capacitor electrode 116 are formed on the substrate 100.

In some embodiments, the substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, an organic polymer, or an opaque/reflective material (e.g., a conductive material, metal, a wafer, ceramic, or other applicable material) or other applicable materials. However, the present invention is not limited thereto, and in other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane PU, or other suitable materials.

The first calibration mark 112, the alignment mark 113, the light shielding layer 114 and the first capacitor electrode 116 have the same material. In some embodiments, the materials of the first calibration mark 112, the alignment mark 113, the light shielding layer 114 and the first capacitor electrode 116 include metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, the above alloys, the above metal oxides, the above metal nitrides or the above combinations or other conductive materials. In some embodiments, the method of forming the first calibration mark 112, the alignment mark 113, the light shielding layer 114 and the first capacitor electrode 116 includes: first, forming a conductive material layer on the substrate 100. Next, the conductive material layer is patterned to form a first calibration mark 112, an alignment mark 113, a light shielding layer 114, and a first capacitor electrode 116. In some embodiments, the method of forming the conductive material layer includes sputtering, electroplating, chemical plating, physical vapor deposition, chemical vapor deposition or other suitable processes.

In the embodiment of FIG. 3A , the first calibration mark 112, the alignment mark 113, the light shielding layer 114, and the first capacitor electrode 116 directly contact the substrate 100, but the present invention is not limited thereto. In other embodiments, a buffer layer is first formed on the substrate 100, and then the first calibration mark 112, the alignment mark 113, the light shielding layer 114, and the first capacitor electrode 116 are formed on the buffer layer.

3B , an insulating layer 120A is formed on the first calibration mark 112, the alignment mark 113, the light shielding layer 114, and the first capacitor electrode 116. The insulating layer 120A extends from the active device region TR and the capacitor region CR of the substrate 100 to the alignment mark region NR and the calibration mark region MR.

In some embodiments, the material of the insulating layer 120A includes silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, bismuth oxide, aluminum oxide, organic insulating materials, other suitable materials or combinations of the above materials. In some embodiments, the method of forming the insulating layer 120A includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, coating or other suitable processes. In some embodiments, the thickness of the insulating layer 120A is 500 angstroms to 10,000 angstroms.

A semiconductor layer 132 and a second capacitor electrode 134 are formed on the insulating layer 120A. The semiconductor layer 132 and the second capacitor electrode 134 have the same material. In some embodiments, the semiconductor layer 132 and the second capacitor electrode 134 are each a single layer or a multi-layer structure, which includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, oxide semiconductor material (for example: indium zinc oxide, indium gallium zinc oxide or other suitable materials, or a combination of the above materials) or other suitable materials or a combination of the above materials. In some embodiments, the method of forming the semiconductor layer 132 and the second capacitor electrode 134 includes: first, forming a semiconductor material layer on the insulating layer 120A. Next, the semiconductor material layer is patterned to form a semiconductor layer 132 and a second capacitor electrode 134.

Please refer to FIG. 3C , a first photoresist pattern PR1 is formed on the semiconductor layer 132 and the insulating layer 120A according to the alignment mark 113. Specifically, a whole layer of photoresist material layer is first formed on the semiconductor layer 132, the second capacitor electrode 134 and the insulating layer 120A. Then, an exposure process is performed on the photoresist material layer using a mask. In the aforementioned exposure process, the machine and/or mask used in the exposure process are aligned by the alignment mark 113. For example, the alignment mark 113 is irradiated with light, and the position of the alignment mark 113 is confirmed by the penetration and/or reflection of the light, thereby determining the exposure position of the photoresist material layer. After the exposure process, a development process is performed to remove unnecessary portions of the photoresist layer and leave the first photoresist pattern PR1.

In this embodiment, the first photoresist pattern PR1 has an opening H1 and an opening H2, wherein the opening H1 is located on the calibration mark region MR and overlaps the first calibration mark 112. The opening H2 is located on the alignment mark region NR. In addition, the first photoresist pattern PR1 covers a portion of the semiconductor layer 132 and exposes another portion of the semiconductor layer 132 and the second capacitor electrode 134.

In the present embodiment, the positions of the opening H1 of the first photoresist pattern PR1 and the first calibration mark 112 are measured to confirm whether the exposure process is accurately performed. For example, the first photoresist pattern PR1 and the first calibration mark 112 are irradiated with light, and the relative positions of the first photoresist pattern PR1 and the first calibration mark 112 are confirmed by the penetration and/or reflection of the light, thereby obtaining the process offset parameters of the exposure process of the first photoresist pattern PR1. If the exposure process of the first photoresist pattern PR1 produces an excessive offset, the first photoresist pattern PR1 can be removed, and the exposure process can be calibrated using the previously obtained process offset parameters. A photoresist material layer is re-formed on the semiconductor layer 132, the second capacitor electrode 134, and the insulating layer 120A, and the photoresist material layer is exposed using the calibrated exposure process. This method can improve the process yield.

3D , the first ion implantation process IP1 is performed on the semiconductor layer 132 using the first photoresist pattern PR1 as a mask to form a first doped region 132a in the semiconductor layer 132. In this embodiment, the first ion implantation process IP1 also dopes the second capacitor electrode 134.

In some embodiments, the first doped region 132a of the semiconductor layer 132 and the second capacitor electrode 134 include a P-type silicon semiconductor, and the doping selected in the first ion implantation process IP1 is aluminum (Al), boron (B), gallium (Ga) or other suitable materials. In some embodiments, the first doped region 132a of the semiconductor layer 132 and the second capacitor electrode 134 include an N-type silicon semiconductor, and the doping selected in the first ion implantation process IP1 is antimony (Sb), arsenic (As), phosphorus (P) or other suitable materials. In some embodiments, the first ion implantation process IP1 can be called a heavy doping process, and the first doped region 132a can be called a P+ region or an N+ region.

Referring to FIG. 3E , after performing the first ion implantation process IP1, the insulating layer 120A is etched using the first photoresist pattern PR1 as a mask to form an alignment opening 123 and a correction opening 122 in the insulating layer 120A. In some embodiments, the etching also forms a groove 124 in the insulating layer 120A around the semiconductor layer 132 and/or the second capacitor electrode 134. In some embodiments, the etching process includes a wet etching process or other suitable processes. For example, the insulating layer 120A is etched using hydrofluoric acid.

In some embodiments, the sidewalls of the groove 124 may be retracted to the sidewalls of the semiconductor layer 132 and/or the second capacitor electrode 134 due to an undercut problem. Similarly, the sidewalls of the alignment opening 123 and the correction opening 122 may also be retracted to the sidewalls of the first photoresist pattern PR1.

In some embodiments, the depths of the alignment opening 123 , the correction opening 122 , and the recess 124 are in a range of 500 angstroms to 3000 angstroms.

3F , the first photoresist pattern PR1 is removed. For example, the first photoresist pattern PR1 is removed by an ashing process, a stripping process or other suitable processes.

3G, a gate dielectric layer 140 is formed on the insulating layer 120A, the semiconductor layer 132, the second capacitor electrode 134, the alignment opening 123, the correction opening 122, and the groove 124. In some embodiments, the gate dielectric layer 140 has a single-layer or multi-layer structure, and its material includes silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, bismuth oxide, aluminum oxide, organic insulating materials, other suitable materials or combinations of the above materials. In some embodiments, the method of forming the gate dielectric layer 140 includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, coating or other suitable processes. In some embodiments, the gate dielectric layer 140 has a thickness of 500 angstroms to 1500 angstroms.

The gate dielectric layer 140 is filled in the alignment opening 123, the correction opening 122, and the groove 124. In some embodiments, since the sidewalls of the groove 124 are indented to the sidewalls of the semiconductor layer 132 and the second capacitor electrode 134, a portion of the gate dielectric layer 140 may be located between the semiconductor layer 132 and the insulating layer 120A and between the second capacitor electrode 134 and the insulating layer 120A in the normal direction of the top surface of the substrate 100. In this embodiment, a portion of the insulating layer 120A covers the first correction mark 112 and the alignment mark 113, and separates the first correction mark 112 and the alignment mark 113 from the gate dielectric layer 140, but the present invention is not limited thereto. In other embodiments, the correction opening 122 exposes the top surface of the first correction mark 112, and the gate dielectric layer 140 fills the correction opening 122 and contacts the top surface of the first correction mark 112. In this case, the gate dielectric layer 140 contacts the first correction mark 112 but is separated from the alignment mark 113.

3H, a conductive material layer 150 is formed on the gate dielectric layer 140. In some embodiments, the conductive material layer 150 has a single layer or a multi-layer structure, and its material includes metals such as chromium, gold, silver, copper, tin, lead, cobalt, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, the above alloys, the above metal oxides, the above metal nitrides, or the above combinations or other conductive materials. In some embodiments, the method of forming the conductive material layer 150 includes sputtering, electroplating, chemical plating, physical vapor deposition, chemical vapor deposition or other suitable processes.

Please refer to Figure 3I, a second photoresist pattern PR2A~PR2C is formed on the conductive material layer 150 according to the alignment opening 123. Specifically, a whole layer of photoresist material layer is first formed on the conductive material layer 150. Then, an exposure process is performed on the photoresist material layer using a mask. In the aforementioned exposure process, the machine and/or mask used in the exposure process are aligned through the alignment opening 123. For example, the alignment opening 123 is irradiated with light, and the position of the alignment opening 123 is confirmed by the penetration and/or reflection of the light, thereby determining the exposure position of the photoresist material layer. After the exposure process, a development process is performed to remove unnecessary portions of the photoresist material layer, leaving the second photoresist pattern PR2A~PR2C.

In the present embodiment, the second photoresist pattern PR2A overlaps the calibration opening 122, and the positions of the second photoresist pattern PR2A and the calibration opening 122 are measured to confirm whether the exposure process is accurately executed. For example, the second photoresist pattern PR2A and the calibration opening 122 are illuminated with light, and the relative positions of the second photoresist pattern PR2A and the calibration opening 122 are confirmed by the penetration and/or reflection of the light, thereby obtaining the process offset parameters of the exposure process of the second photoresist patterns PR2A~PR2C. If the exposure process of the second photoresist patterns PR2A~PR2C produces an excessively large offset, the second photoresist patterns PR2A~PR2C can be removed, and the exposure process can be calibrated using the previously obtained process offset parameters. A photoresist material layer is re-formed on the conductive material layer 150, and the photoresist material layer is exposed using the calibrated exposure process. This method can improve the process yield.

Referring to FIG. 3J , the conductive material layer 150 is etched with the second photoresist patterns PR2A-PR2C as masks to form a second correction mark 152, a gate 154, and a third capacitor electrode 156. The second correction mark 152 overlaps the first correction mark 112 and the correction opening 122. The gate 154 overlaps the semiconductor layer 132, wherein the gate 154 partially overlaps the first doped region 132a. The third capacitor electrode 156 overlaps the first capacitor electrode 116 and the second capacitor electrode 134.

The lithography process of the second photoresist patterns PR2A-PR2C of this embodiment can be calibrated according to the calibration opening 122 without using the first calibration mark 112 for calibration, thereby avoiding the problem of misalignment caused by the superposition of process variations of the two lithography processes. For example, the position of the first photoresist pattern PR1 (see FIG. 3E ) can be corrected according to the first correction mark 112, and the process variation of the first photoresist pattern PR1 is 0 μm to 0.25 μm, and the process variation is the square of half of the maximum offset of the critical dimension (Critical dimension) of the lithography process plus the square of the maximum offset of the geometric center of the opening H1 (see FIG. 3C ) of the first photoresist pattern PR1 and the geometric center of the first correction mark 112, wherein the maximum offset of the critical dimension is -0.6 μm to 0.6 μm, and the maximum offset of the geometric center is -0.4 μm to 0.4 μm. If the second photoresist patterns PR2A-PR2C are also calibrated according to the first calibration mark 112, the process variation of forming the second photoresist patterns PR2A-PR2C will be accumulated with the process variation of forming the first photoresist pattern PR1, causing the relative position between the gate 154 and the first doped region 132a to be more easily offset.

In this embodiment, the position of the second photoresist patterns PR2A-PR2C can be corrected according to the correction opening 122, and the process variation of the second photoresist patterns PR2A-PR2C is 0 micrometers to 0.25 micrometers, and the process variation is the square of half of the maximum offset of the critical dimension plus the square of the maximum offset of the geometric center of the second photoresist pattern PR2A and the geometric center of the correction opening 122, wherein the maximum offset of the critical dimension is -0.6 micrometers to 0.6 micrometers, and the maximum offset is -0.4 micrometers to 0.4 micrometers. Therefore, the relative position between the gate 154 and the first doped region 132a is only affected by the process variation when forming the second photoresist patterns PR2A-PR2C, and is not affected by the process variation when forming the first photoresist pattern PR1.

3K , a second ion implantation process IP2 is performed on the semiconductor layer 132 using the gate 154 as a mask to form a second doped region 132b in the semiconductor layer 132. The first doped region 132a is separated from the second doped region 132b.

In some embodiments, the second doped region 132b of the semiconductor layer 132 includes a P-type silicon semiconductor, and the dopant selected by the second ion implantation process IP2 is aluminum (Al), boron (B), gallium (Ga) or other suitable materials. In some embodiments, the second doped region 132b of the semiconductor layer 132 includes an N-type silicon semiconductor, and the dopant selected by the first ion implantation process IP1 is antimony (Sb), arsenic (As), phosphorus (P) or other suitable materials. In some embodiments, the second ion implantation process IP2 can be called a heavy doping process, and the second doped region 132b can be called a P+ region or an N+ region. The first doped region 132a and the second doped region 132b include the same dopant.

In some embodiments, since part of the first doped region 132a will also be doped by the second ion implantation process IP2, the first doped region 132a may include a first portion 132a-1 that has been subjected to the first ion implantation process IP1 (see FIG. 3D ) plus the second ion implantation process IP2 and a second portion 132a-2 that has only been subjected to the first ion implantation process IP1. In some embodiments, the doping concentration of the first portion 132a-1 is greater than or equal to the doping concentration of the second portion 132a-2.

3L , an etch-back process is performed on the second correction mark 152, the gate 154, and the third capacitor electrode 156 to reduce the width of the second correction mark 152, the gate 154, and the third capacitor electrode 156. After the etch-back process, a portion of the semiconductor layer 132 between the first doped region 132a and the second doped region 132b that is not doped will not overlap the gate 154 after the width is reduced.

In some embodiments, the width and thickness of the second photoresist patterns PR2A-PR2C are also reduced during the etching process.

3M, the semiconductor layer 132 is subjected to a third ion implantation process IP3 with the gate 154 as a mask to form a lightly doped region 132c in the semiconductor layer 132. The lightly doped region 132c is located between the second doped region 132b and the channel region 132d of the semiconductor layer 132. In some embodiments, the first portion 132a-1, a portion of the second portion 132a-2, and the second doped region 132b are also subjected to the third ion implantation process IP3, while the channel region 132d overlapping the gate 154 and another portion of the second portion 132a-2 are not subjected to the third ion implantation process IP3.

In some embodiments, the third ion implantation process IP3 is performed after the second photoresist patterns PR2A-PR2C are removed, but the present invention is not limited thereto. In other embodiments, the second photoresist patterns PR2A-PR2C are removed after the third ion implantation process IP3 is performed. In some embodiments, the second photoresist patterns PR2A-PR2C are removed by an ashing process, a stripping process or other suitable processes.

3N , an interlayer dielectric layer 160 is formed on the gate 154 and the third capacitor electrode 156. In this embodiment, the interlayer dielectric layer 160 also covers the second correction mark 152, but the present invention is not limited thereto. In other embodiments, the second correction mark 152 is not covered by the interlayer dielectric layer 160.

In some embodiments, the material of the interlayer dielectric layer 160 includes silicon oxide, silicon nitride, silicon oxynitride, organic insulating materials, other suitable materials or combinations of the above materials. In some embodiments, the method of forming the interlayer dielectric layer 160 includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, coating or other suitable processes. In some embodiments, a plurality of through holes passing through the interlayer dielectric layer 160 and the gate dielectric layer 140 are formed by an etching process. These through holes expose the first doped region 132a and the second doped region 132b of the semiconductor layer 132.

3O, a source electrode 172 and a drain electrode 174 are formed on the interlayer dielectric layer 160. One of the source electrode 172 and the drain electrode 174 is connected to the first doped region 132a, and the other is connected to the second doped region 132b.

Finally, please return to FIG. 2 , where the display unit 180 is formed on the active device TFT and is electrically connected or electrically coupled to the active device TFT.

FIG4 is a cross-sectional schematic diagram of a display device 20 according to an embodiment of the present invention. It should be noted that the embodiment of FIG4 uses the component numbers and partial contents of the embodiments of FIG2 to FIG30, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

The display device 20 of FIG4 is different from the display device 10 of FIG2 in that: in the display device 20, the gate dielectric layer 140 contacts the top surface of the first correction mark 112 through the correction opening 122. The insulating layer 120A surrounds the first correction mark 112 and does not cover the top surface of the first correction mark 112.

FIG5 is a cross-sectional schematic diagram of a display device 30 according to an embodiment of the present invention. It should be noted that the embodiment of FIG5 uses the component numbers and some contents of the embodiment of FIG4, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

The display device 30 of FIG. 5 is different from the display device 20 of FIG. 4 in that: in the display device 30, the insulating layer 120A includes a multi-layer structure. For example, the insulating layer 120A includes a first layer 120A-1 and a second layer 120A-2, wherein the first layer 120A-1 is located between the second layer 120A-2 and the substrate 100. In some embodiments, the correction opening 122 and the alignment opening 123 pass through the entire second layer 120A-2 and extend into the first layer 120A-1, but the present invention is not limited thereto. In other embodiments, the correction opening 122 and the alignment opening 123 do not extend into the first layer 120A-1.

The first layer 120A-1 and the second layer 120A-2 include different materials. In some embodiments, the materials of the first layer 120A-1 and the second layer 120A-2 include silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, vanadium oxide, aluminum oxide, organic insulating materials, other suitable materials or combinations thereof.

FIG6 is a cross-sectional schematic diagram of a display device 40 according to an embodiment of the present invention. It should be noted that the embodiment of FIG6 uses the component numbers and partial contents of the embodiments of FIG2 to FIG30, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the aforementioned embodiments, and will not be repeated here.

The display device 40 of FIG. 6 is different from the display device 10 of FIG. 2 in that: in the display device 40, the insulating layer 120B including the correction opening 122 and the alignment opening 123 is disposed above the semiconductor layer 132, and the semiconductor layer 132 further includes a buffer layer BL below. The insulating layer 120B is located between the semiconductor layer 132 and the gate dielectric layer 140.

In some embodiments, the correction opening 122 and the alignment opening 123 do not extend into the buffer layer BL, but the present invention is not limited thereto. In other embodiments, the correction opening 122 and the alignment opening 123 extend into the buffer layer BL.

7A to 7P are cross-sectional views of various stages of manufacturing the display device 40 of FIG6. Referring to FIG7A, a first calibration mark 112, an alignment mark 113, a light shielding layer 114 and a first capacitor electrode 116 are formed on the substrate 100.

In the embodiment of FIG. 7A , the first calibration mark 112, the alignment mark 113, the light shielding layer 114, and the first capacitor electrode 116 directly contact the substrate 100, but the present invention is not limited thereto. In other embodiments, other buffer layers are first formed on the substrate 100, and then the first calibration mark 112, the alignment mark 113, the light shielding layer 114, and the first capacitor electrode 116 are formed on the other buffer layers.

7B, a buffer layer BL is formed on the first calibration mark 112, the alignment mark 113, the light shielding layer 114 and the first capacitor electrode 116. The buffer layer BL extends from the active device region TR and the capacitor region CR of the substrate 100 to the alignment mark region NR and the calibration mark region MR.

In some embodiments, the material of the buffer layer BL includes silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, bismuth oxide, aluminum oxide, organic insulating materials, other suitable materials or a combination of the above materials. In some embodiments, the method of forming the buffer layer BL includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, coating or other suitable processes.

A semiconductor layer 132 and a second capacitor electrode 134 are formed on the buffer layer BL.

7C , an insulating layer 120B is formed on the semiconductor layer 132 and the second capacitor electrode 134. The insulating layer 120B extends from the active device region TR and the capacitor region CR of the substrate 100 to the alignment mark region NR and the calibration mark region MR.

In some embodiments, the material of the insulating layer 120B includes silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, bismuth oxide, aluminum oxide, organic insulating materials, other suitable materials or combinations of the above materials. In some embodiments, the method of forming the insulating layer 120B includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, coating or other suitable processes. In some embodiments, the thickness of the insulating layer 120B is 400 angstroms to 1500 angstroms.

Referring to FIG. 7D , a first photoresist pattern PR1 is formed on the insulating layer 120B according to the alignment mark 113. Specifically, a whole layer of photoresist material layer is first formed on the insulating layer 120B. Then, the photoresist material layer is exposed using a photomask. In the aforementioned exposure process, the machine and/or the photomask used in the exposure process are aligned using the alignment mark 113.

In this embodiment, the first photoresist pattern PR1 has an opening H1 overlapping the first alignment mark 112. In addition, the first photoresist pattern PR1 overlaps a portion of the semiconductor layer 132, but does not overlap another portion of the semiconductor layer 132 and the second capacitor electrode 134.

In the present embodiment, the positions of the opening H1 of the first photoresist pattern PR1 and the first correction mark 112 are measured to confirm whether the exposure process is accurately performed. For example, the first photoresist pattern PR1 and the first correction mark 112 are irradiated with light, and the relative positions of the first photoresist pattern PR1 and the first correction mark 112 are confirmed by the penetration and/or reflection of the light, thereby obtaining the process offset parameters of the exposure process of the first photoresist pattern PR1. If the exposure process of the first photoresist pattern PR1 produces an excessively large offset, the first photoresist pattern PR1 can be removed, and the exposure process can be calibrated using the previously obtained process offset parameters. A photoresist material layer is re-formed on the insulating layer 120B, and the photoresist material layer is exposed using the calibrated exposure process. In this way, the process yield can be improved.

7E , the first ion implantation process IP1 is performed on the semiconductor layer 132 using the first photoresist pattern PR1 as a mask to form a first doped region 132a in the semiconductor layer 132. In this embodiment, the first ion implantation process IP1 also dopes the second capacitor electrode 134.

Referring to FIG. 7F , after performing the first ion implantation process IP1, the insulating layer 120B is etched using the first photoresist pattern PR1 as a mask to form an alignment opening 123 and a correction opening 122 in the insulating layer 120B, and to expose the first doped region 132a and the first capacitor electrode 134. In some embodiments, the etching process includes a dry etching process, a wet etching process or other suitable processes. For example, the insulating layer 120B is etched using hydrofluoric acid or fluoroform (CHF ₃ ).

In this embodiment, since the insulating layer 120B covers the semiconductor layer 132 and the second capacitor electrode 134 before the etching process, the damage to the semiconductor layer 132 and the second capacitor electrode 134 caused by the etching process can be reduced.

In addition, in this embodiment, the alignment opening 123 and the correction opening 122 do not extend into the buffer layer BL, but the present invention is not limited thereto. In some embodiments, the etching process allows the alignment opening 123 and the correction opening 122 to extend into the buffer layer BL, and forms a groove extending into the buffer layer BL around the semiconductor layer 132 and the second capacitor electrode 134.

7G , the first photoresist pattern PR1 is removed. For example, the first photoresist pattern PR1 is removed by an ashing process, a stripping process or other suitable processes.

7H, a gate dielectric layer 140 is formed on the insulating layer 120B, the semiconductor layer 132, the second capacitor electrode 134, the alignment opening 123, and the correction opening 122. In some embodiments, the gate dielectric layer 140 has a single-layer or multi-layer structure, and its material includes silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, bismuth oxide, aluminum oxide, organic insulating materials, other suitable materials, or a combination of the above materials. In some embodiments, the method of forming the gate dielectric layer 140 includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, coating, or other suitable processes. In some embodiments, the gate dielectric layer 140 has a thickness of 200 angstroms to 1500 angstroms. For example, the gate dielectric layer 140 includes 0 angstroms to 1500 angstroms of silicon oxide and 0 angstroms to 1500 angstroms of silicon nitride.

The gate dielectric layer 140 fills the alignment opening 123 and the correction opening 122 and contacts the buffer layer BL.

Referring to FIG. 7I , a conductive material layer 150 is formed on the gate dielectric layer 140. In some embodiments, the conductive material layer 150 has a single layer or a multi-layer structure, and its material includes metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, the above alloys, the above metal oxides, the above metal nitrides, or the above combinations or other conductive materials. In some embodiments, the method of forming the conductive material layer 150 includes sputtering, electroplating, chemical plating, physical vapor deposition, chemical vapor deposition or other suitable processes.

Referring to FIG. 7J , the second photoresist patterns PR2A-PR2C are formed on the conductive material layer 150 according to the alignment opening 123. Specifically, a whole layer of photoresist material layer is first formed on the conductive material layer 150. Then, the photoresist material layer is exposed using a mask. In the aforementioned exposure process, the machine and/or mask used in the exposure process are aligned through the alignment opening 123.

In the present embodiment, the second photoresist pattern PR2A overlaps the calibration opening 122, and the positions of the second photoresist pattern PR2A and the calibration opening 122 are measured to confirm whether the exposure process is accurately executed. For example, the second photoresist pattern PR2A and the calibration opening 122 are illuminated with light, and the relative positions of the second photoresist pattern PR2A and the calibration opening 122 are confirmed by the penetration and/or reflection of the light, thereby obtaining the process offset parameters of the exposure process of the second photoresist patterns PR2A~PR2C. If the exposure process of the second photoresist patterns PR2A~PR2C produces an excessively large offset, the second photoresist patterns PR2A~PR2C can be removed, and the exposure process can be calibrated using the previously obtained process offset parameters. A photoresist material layer is re-formed on the conductive material layer 150, and the photoresist material layer is exposed using the calibrated exposure process. This method can improve the process yield.

Referring to FIG. 7K , the conductive material layer 150 is etched with the second photoresist patterns PR2A-PR2C as masks to form a second correction mark 152, a gate 154, and a third capacitor electrode 156. The second correction mark 152 overlaps the first correction mark 112 and the correction opening 122. The gate 154 overlaps the semiconductor layer 132, wherein the gate 154 partially overlaps the first doped region 132a. The third capacitor electrode 156 overlaps the first capacitor electrode 116 and the second capacitor electrode 134.

The positions of the second photoresist patterns PR2A-PR2C of this embodiment can be calibrated according to the calibration opening 122 instead of the first calibration mark 112, thereby avoiding the problem of excessive process variation caused by the superposition of errors of two lithography processes.

7L , a second ion implantation process IP2 is performed on the semiconductor layer 132 using the gate 154 as a mask to form a second doped region 132b in the semiconductor layer 132. The first doped region 132a is separated from the second doped region 132b.

In some embodiments, since part of the first doped region 132a will also be doped by the second ion implantation process IP2, the first doped region 132a may include a first portion 132a-1 that has undergone the first ion implantation process IP1 (see FIG. 7E ) plus the second ion implantation process IP2 and a second portion 132a-2 that has only undergone the first ion implantation process IP1.

7M , an etch-back process is performed on the second correction mark 152, the gate 154, and the third capacitor electrode 156 to reduce the width of the second correction mark 152, the gate 154, and the third capacitor electrode 156. After the etch-back process, a portion of the semiconductor layer 132 between the first doped region 132a and the second doped region 132b that is not doped will not overlap the gate 154 after the width is reduced.

In some embodiments, the width and thickness of the second photoresist patterns PR2A-PR2C are also reduced during the etching process.

7N , the semiconductor layer 132 is subjected to a third ion implantation process IP3 with the gate 154 as a mask to form a lightly doped region 132c in the semiconductor layer 132. The lightly doped region 132c is located between the second doped region 132b and the channel region 132d of the semiconductor layer 132. In some embodiments, the first portion 132a-1, a portion of the second portion 132a-2, and the second doped region 132b are also subjected to the third ion implantation process IP3, while the channel region 132d overlapping the gate 154 and another portion of the second portion 132a-2 are not subjected to the third ion implantation process IP3.

In this embodiment, the gate dielectric layer 140 contacts the top surface of the first doped region 132a, and the insulating layer 120B contacts the top surface of the second doped region 132b, the top surface of the lightly doped region 132c, and the top surface of the channel region 132d.

In some embodiments, the third ion implantation process IP3 is performed after the second photoresist patterns PR2A-PR2C are removed, but the present invention is not limited thereto. In other embodiments, the second photoresist patterns PR2A-PR2C are removed after the third ion implantation process IP3 is performed. In some embodiments, the second photoresist patterns PR2A-PR2C are removed by an ashing process, a stripping process or other suitable processes.

7O , an interlayer dielectric layer 160 is formed on the gate 154 and the third capacitor electrode 156. In this embodiment, the interlayer dielectric layer 160 also covers the second calibration mark 152, but the present invention is not limited thereto. In other embodiments, the second calibration mark 152 is not covered by the interlayer dielectric layer 160.

7P , a source electrode 172 and a drain electrode 174 are formed on the interlayer dielectric layer 160. One of the source electrode 172 and the drain electrode 174 is connected to the first doped region 132a, and the other is connected to the second doped region 132b. One of the source electrode 172 and the drain electrode 174 contacts the insulating layer 120B, and the other is separated from the insulating layer 120B.

Finally, please return to FIG. 6 , where the display unit 180 is formed on the active device TFT and is electrically connected or electrically coupled to the active device TFT.

In summary, the present invention can avoid the problem of the gate 154 and the first doped region 132a being offset due to excessive process variation by setting the correction opening 122.

10, 20, 30, 40: display device 100: substrate 112: first calibration mark 113: alignment mark 114: light shielding layer 116: first capacitor electrode 120A, 120B: insulating layer 120A-1: first layer 120A-2: second layer 122: calibration opening 123: alignment opening 124: groove 132: semiconductor layer 132a: first doped region 132a-1: first part 132a-2: second part 132b: second doped region 132c: lightly doped region 132d: channel region 134: second capacitor electrode 140: gate dielectric layer 150: conductive material layer 152: second correction mark 154: gate 156: third capacitor electrode 160: interlayer dielectric layer 172: source 174: drain 180: display unit AA: display area BL: buffer layer C: capacitor CR: capacitor area H1, H2: opening IP1: first ion implantation process IP2: second ion implantation process IP3: third ion implantation process MR: correction mark area NR: alignment mark area PA: peripheral area PR1: first photoresist pattern PR2A~PR2C: Second photoresist pattern TFT: Thin film transistor TR: Active device area

FIG. 1 is a schematic top view of a display device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a display device according to an embodiment of the present invention. FIG. 3A to FIG. 3O are schematic cross-sectional views of various stages of manufacturing the display device of FIG. 2. FIG. 4 is a schematic cross-sectional view of a display device according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a display device according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a display device according to an embodiment of the present invention. FIG. 7A to FIG. 7P are schematic cross-sectional views of various stages of manufacturing the display device of FIG. 6.

10: Display device

100:Substrate

112: First calibration mark

113: Alignment mark

114: Shading layer

116: first capacitor electrode

120A: Insulation layer

122:Correction opening

123: Alignment opening

124: Groove

132: Semiconductor layer

132a: First mixed area

132a-1: Part I

132a-2: Part 2

132b: Second mixed area

132c: Lightly mixed area

132d: Channel area

134: Second capacitor electrode

140: Gate dielectric layer

152: Second calibration mark

154: Gate

156: The third capacitor electrode

160: Interlayer dielectric layer

172:Source

174:Jiji

180: Display unit

AA: Display area

C: Capacitor

CR: Capacitance region

MR: Correction Marking Area

NR: Registration mark area

PA: Peripheral Area

TFT: Thin Film Transistor

TR: Active component area

Claims (12)

A method for manufacturing an active element substrate, comprising: Forming an alignment mark and a first correction mark on an alignment mark area and a correction mark area of a substrate respectively; Forming an insulating layer extending from an active element area of the substrate to the correction mark area; Forming a semiconductor layer on the active element area; Forming a first photoresist pattern on the semiconductor layer and the insulating layer according to the alignment mark; Performing a first ion implantation process on the semiconductor layer using the first photoresist pattern as a mask to form a first doping area in the semiconductor layer; Etching the insulating layer using the first photoresist pattern as a mask to form a correction opening in the insulating layer that overlaps the first correction mark; Removing the first photoresist pattern; Forming a gate dielectric layer on the semiconductor layer and the correction opening; and Forming a gate, an inter-layer dielectric layer, a source and a drain on the gate dielectric layer. The manufacturing method as described in claim 1, wherein the method for forming the gate, the interlayer dielectric layer, the source and the drain on the gate dielectric layer comprises: Forming a conductive material layer on the gate dielectric layer; Etching the insulating layer using the first photoresist pattern as a mask to form an alignment opening in the insulating layer; Forming a second photoresist pattern on the conductive material layer according to the alignment opening; Etching the conductive material layer using the second photoresist pattern as a mask to form the gate, wherein the gate overlaps the semiconductor layer; Performing a second ion implantation process on the semiconductor layer with the gate as a mask to form a second doped region in the semiconductor layer, wherein the first doped region is separated from the second doped region; Performing an etch-back process on the gate to reduce the width of the gate; After the etch-back process, performing a third ion implantation process on the semiconductor layer with the gate as a mask to form a lightly doped region in the semiconductor layer, wherein the lightly doped region is located between the second doped region and a channel region of the semiconductor layer; Forming the interlayer dielectric layer on the gate; and The source and the drain are formed on the interlayer dielectric layer, wherein one of the source and the drain is connected to the first doped region, and the other of the source and the drain is connected to the second doped region. The manufacturing method as described in claim 2 further includes: irradiating the first photoresist pattern and the first calibration mark with light to confirm the positions of the first photoresist pattern and the first calibration mark; and irradiating the second photoresist pattern and the calibration opening with light to confirm the positions of the second photoresist pattern and the calibration opening. A method for manufacturing an active element substrate, comprising: Forming an alignment mark and a first correction mark on an alignment mark area and a correction mark area of a substrate respectively; Forming a buffer layer extending from an active element area of the substrate to the correction mark area; Forming a semiconductor layer on the buffer layer and on the active element area; Forming an insulating layer on the semiconductor layer and extending from the active element area of the substrate to the correction mark area; Forming a first photoresist pattern on the insulating layer according to the alignment mark; Performing a first ion implantation process on the semiconductor layer using the first photoresist pattern as a mask to form a first doping area in the semiconductor layer; The insulating layer is etched using the first photoresist pattern as a mask to form a correction opening in the insulating layer that overlaps the first correction mark; The first photoresist pattern is removed; A gate dielectric layer is formed on the semiconductor layer, the insulating layer and the correction opening; and A gate, an inter-layer dielectric layer, a source and a drain are formed on the gate dielectric layer. The manufacturing method as described in claim 4, wherein the insulating layer is etched using the first photoresist pattern as a mask to expose the first doped region, and the gate dielectric layer contacts the first doped region, wherein the method for forming the gate, the interlayer dielectric layer, the source and the drain on the gate dielectric layer includes: Forming a conductive material layer on the gate dielectric layer; Etching the insulating layer using the first photoresist pattern as a mask to form an alignment opening in the insulating layer; Forming a second photoresist pattern on the conductive material layer according to the alignment opening; Using the second photoresist pattern as a mask, the conductive material layer is etched to form the gate, wherein the gate partially overlaps the semiconductor layer; Using the gate as a mask, a second ion implantation process is performed on the semiconductor layer to form a second doped region in the semiconductor layer, wherein the first doped region is separated from the second doped region; Performing an etch-back process on the gate to reduce the width of the gate; After the etching back process, a third ion implantation process is performed on the semiconductor layer using the gate as a mask to form a lightly doped region in the semiconductor layer, wherein the lightly doped region is located between the second doped region and a channel region of the semiconductor layer; the interlayer dielectric layer is formed on the gate; and the source and the drain are formed on the interlayer dielectric layer, wherein one of the source and the drain is connected to the first doped region, and the other of the source and the drain is connected to the second doped region. The manufacturing method as described in claim 5 further includes: irradiating the first photoresist pattern and the first calibration mark with light to confirm the positions of the first photoresist pattern and the first calibration mark; and irradiating the second photoresist pattern and the calibration opening with light to confirm the positions of the second photoresist pattern and the calibration opening. A display device comprises: A substrate having a display area and a peripheral area surrounding the display area, wherein the peripheral area includes a correction mark area, and the display area includes an active component area; A first correction mark, located on the correction mark area; An insulating layer is located on the substrate and extends from the active component area to the correction mark area, wherein the insulating layer has a correction opening overlapping the first correction mark; A semiconductor layer, located on the active component area, and the insulating layer at least partially overlaps the semiconductor layer; A gate dielectric layer, located on the semiconductor layer and the correction opening; A gate, an inter-dielectric layer, a source and a drain are located on the gate dielectric layer. A display device as described in claim 7, wherein the insulating layer surrounds the first correction mark, and the gate dielectric layer contacts the top surface of the first correction mark through the correction opening. A display device as described in claim 7, wherein the insulating layer is located between the semiconductor layer and the substrate, and the insulating layer has a groove overlapping the side wall of the semiconductor layer. The display device as claimed in claim 7, wherein the insulating layer is located between the semiconductor layer and the gate dielectric layer, wherein the semiconductor layer includes a first doped region, a second doped region, a lightly doped region and a channel region, wherein the lightly doped region is located between the channel region and the second doped region, and the channel region is located between the first doped region and the lightly doped region, wherein the resistivity of the lightly doped region is higher than the resistivity of the first doped region and the second doped region, and wherein the gate dielectric layer contacts a top surface of the first doped region, and the insulating layer contacts a top surface of the second doped region, a top surface of the lightly doped region, and a top surface of the channel region. A display device as described in claim 7, wherein the insulating layer is located between the semiconductor layer and the gate dielectric layer, wherein one of the source and the drain contacts the insulating layer, and the other of the source and the drain is separated from the insulating layer. The display device as described in claim 7 further includes: a first capacitor electrode located on the substrate and comprising the same material as the first calibration mark; a second capacitor electrode overlapping the first capacitor electrode and comprising the same material as the semiconductor layer; and a third capacitor electrode overlapping the second capacitor electrode, with a portion of the gate dielectric layer located between the second capacitor electrode and the third capacitor electrode.

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