TWI883605B - Duty cycle correction device - Google Patents

Abstract

A duty cycle correction device includes a first duty cycle corrector, an integrator, a phase detection module, a digital-to-analog converter and a first switch. The integrator generates a pair of feedback clock signals for the first duty cycle corrector to adjust a pair of first internal clock signals generated by the first duty cycle corrector. The phase detection module compares the phase of a second internal clock signal generated by the phase detection module with one of the pair of first internal clock signals when the duty cycle of the pair of first internal clock signals is adjusted to a predetermined duty cycle, to produce a phase detection result. The digital-to-analog converter generates a pair of analog signals corresponding to a digital code based on the phase detection result for adjusting the duty cycle of the second internal clock signal to the predetermined duty cycle and store the digital code. The first switch is turned on when the digital code is stored, and transmits the pair of analog signals to the first duty cycle corrector.

Description

Duty cycle calibration device

The present invention relates to a calibration device, in particular to a duty cycle calibration device.

The duty cycle correction device is used to correct the duty cycle of the internal clock signal of the electronic device so that the duty cycle of the internal clock signal will not be greater than or less than the required duty cycle (i.e., the predetermined duty cycle), thereby avoiding interference from external noise. Existing duty cycle correction devices can use analog signals and digital signals to adjust the duty cycle of the internal clock signal of the electronic device.

Referring to FIG. 1 , the existing duty cycle correction device includes a duty cycle corrector 11, a pump circuit 12, capacitors C1 and C2, a comparator 13, a switch SW1, and a digital-to-analog converter 14. The pump circuit 12 is coupled between the duty cycle corrector 11 and the comparator 13. The two ends of the capacitor C1 are coupled to the pump circuit 12 and the ground end respectively, and the two ends of the capacitor C2 are coupled to the pump circuit 12 and the ground end respectively. The pump circuit 12 and the capacitors C1 and C2 are combined into an integrator. The comparator 13 is coupled to the digital-to-analog converter 14 through the switch SW1, and the digital-to-analog converter 14 is coupled to the duty cycle corrector 11.

During operation, the duty cycle corrector 11 is used to receive a pair of complementary external clock signals XCLK and XCLKn, and generate a pair of complementary internal clock signals CLK and CLKn according to the external clock signals XCLK and XCLKn. Then, the pump circuit 12 receives the internal clock signals CLK and CLKn, and generates a pair of complementary feedback clock signals FCK and FCKb according to the internal clock signals CLK and CLKn. Since the two output terminals of the pump circuit 12 are coupled to the ground terminal through capacitors C1 and C2, the feedback clock signals FCK and FCKb are two analog signals that integrate the time according to the internal clock signals CLK and CLKn. The feedback clock signals FCK and FCKb are fed back to the duty cycle corrector 11, so that the duty cycle corrector 11 quickly adjusts the duty cycle of the internal clock signals CLK and CLKn according to the feedback clock signals FCK and FCKb and outputs the adjusted internal clock signals CLK and CLKn (fast adjustment speed). However, it should be noted that when the duty cycle corrector 11 enters the power saving mode, the feedback clock signals FCK and FCKb are discharged through the capacitors C1 and C2 respectively, causing the feedback clock signals FCK and FCKb to disappear. As a result, the method of using analog signals (i.e., feedback clock signals FCK and FCKb) to adjust the duty cycle of the internal clock signals CLK and CLKn will not be applicable in the power saving mode.

Therefore, after the feedback clock signals FCK and FCKb are used to quickly adjust the internal clock signals CLK and CLKn, the switch SW1 is switched from non-conducting to conducting. At this time, the comparator 13 compares the feedback clock signals FCK and FCKb to generate a comparison result (which is a digital signal) and transmits it to the digital-to-analog converter 14. The digital-to-analog converter 14 generates a pair of complementary analog signals CREG and CREGb corresponding to a digital code according to the comparison result, and feeds the analog signals CREG and CREGb back to the duty cycle corrector 11, so that the duty cycle corrector 11 can adjust the internal clock signals CLK and CLKn accordingly. It should be noted that the digital-to-analog converter 14 receives multiple comparison results in sequence, and generates multiple pairs of analog signals CREG and CREGb in sequence to adjust the internal clock signals CLK and CLKn to the predetermined working cycle. When the internal clock signals CLK and CLKn are adjusted to the predetermined working cycle, the digital-to-analog converter 14 stores the digital code corresponding to the corresponding analog signals CREG and CREGb, so that when the working cycle corrector 11 needs to adjust the working cycle of the internal clock signals CLK and CLKn next time, the digital-to-analog converter 14 can generate the corresponding analog signals CREG and CREGb according to the corresponding digital code for use by the working cycle corrector 11. Thus, when the duty cycle corrector 11 enters the power saving mode, since the corresponding digital code has been stored by the digital-to-analog converter 14 for use in the next adjustment, the method of using the digital signal (i.e., the comparison result) to generate the analog signals CREG and CREGb corresponding to the digital code to adjust the duty cycle of the internal clock signals CLK and CLKn can be applied to the power saving mode (because the digital code is recorded). However, each time the comparator 13 performs a comparison, it needs to wait until the feedback clock signals FCK and FCKb differ by a specific strength value before the comparator 13 can generate a comparison result, resulting in a slower duty cycle adjustment speed and a longer time required to obtain the required digital code.

For example, further refer to FIG. 2. FIG. 2 is a schematic diagram of the time required for the existing duty cycle correction device to complete the duty cycle adjustment operation (including adjusting the internal clock signal to the predetermined duty cycle and obtaining the corresponding digital code). First, before time T1, the duty cycle corrector 11 uses the feedback clock signals FCK and FCKb to quickly adjust the duty cycle of the internal clock signals CLK and CLKn (the required time is 32 system clock cycles tck). Then, the switch SW1 is turned on, and the comparator 13 generates a comparison result based on the feedback clock signals FCK and FCKb, so that the digital-to-analog converter 14 can generate analog signals CREG and CREGb corresponding to a preset digital code of 32. After time T1, the comparator 13 generates a plurality of comparison results in sequence, and the digital-to-analog converter 14 generates a plurality of pairs of analog signals CREG and CREGb (corresponding to digital codes 33, 34, ..., 61, 62, respectively) in sequence according to the plurality of comparison results. The duty cycle corrector 11 sequentially uses the feedback analog signals CREG and CREGb to replace the feedback clock signals FCK and FCKb to adjust the internal clock signals CLK and CLKn to the predetermined duty cycle. As shown in FIG. 2 , the duty cycle corrector 11 first uses the analog signals CREG and CREGb corresponding to the digital code 33 to adjust the duty cycle of the internal clock signals CLK and CLKn. Next, the duty cycle corrector 11 uses the analog signals CREG and CREGb corresponding to the digital code 34 to adjust the duty cycles of the internal clock signals CLK and CLKn. The same operation is repeated until the analog signals CREG and CREGb corresponding to the digital code 62 are used to adjust the duty cycles of the internal clock signals CLK and CLKn. Only then do the duty cycles of the internal clock signals CLK and CLKn meet the required predetermined duty cycles. In this case, since the comparator 13 needs to wait until the feedback clock signals FCK and FCKb differ by a specific strength value each time it performs comparison, the comparator 13 will perform comparison to generate each comparison result, and the waiting time each time is approximately 32 system clock cycles tck, resulting in the digital-to-analog converter 14 generating each pair of analog signals CREG and CREGb according to the comparison result each time. The time required is approximately 32 system clock cycles tck. As a result, in the case of Figure 2, the existing duty cycle correction device needs to spend a total of {1+(62-33+1)}*32=992 system clock cycles tck operation time to obtain the analog signals CREG, CREGb and their corresponding digital codes (62) that can adjust the internal clock signals CLK, CLKn to the predetermined duty cycle, resulting in a longer time required for the existing duty cycle correction device to obtain the corresponding digital code, resulting in a slower speed in completing the duty cycle adjustment operation using this method.

Therefore, the purpose of the present invention is to provide a working cycle correction device that can complete the working cycle adjustment operation faster, so as to solve the problem that the existing working cycle correction device completes the working cycle adjustment operation slowly.

Therefore, the duty cycle correction device of the present invention includes a first duty cycle corrector, an integrator, a phase detection module, a digital-to-analog converter, and a first switch.

The first duty cycle corrector is used to receive a pair of external clock signals and generate a pair of first internal clock signals according to the pair of external clock signals.

The integrator is coupled to the first duty cycle corrector to receive the pair of first internal clock signals, and generates a pair of feedback clock signals according to the pair of first internal clock signals, and transmits the pair of feedback clock signals to the first duty cycle corrector, so that the first duty cycle corrector also adjusts the respective duty cycles of the pair of first internal clock signals according to the pair of feedback clock signals.

The phase detection module is used to receive the pair of external clock signals and generate a pair of second internal clock signals according to the pair of external clock signals, and is coupled to the first duty cycle corrector to receive one of the pair of first internal clock signals, and when the duty cycles of the pair of first internal clock signals are adjusted to a predetermined duty cycle, the phase of the pair of first internal clock signals is compared with one of the pair of second internal clock signals to generate a phase detection result.

The digital-to-analog converter is coupled to the phase detection module to receive the phase detection result, and generates a pair of analog signals corresponding to a digital code according to the phase detection result, and transmits the pair of analog signals to the phase detection module, so that the phase detection module also adjusts the respective duty cycles of the pair of second internal clock signals according to the pair of analog signals. When the pair of analog signals adjusts the respective duty cycles of the pair of second internal clock signals to the predetermined duty cycle, the digital-to-analog converter stores the digital code corresponding to the pair of analog signals.

The first switch is coupled between the first duty cycle corrector and the digital-to-analog converter. When the digital-to-analog converter stores the digital code corresponding to the pair of analog signals, the first switch is controlled by a first switching signal to switch from non-conducting to conducting, and receives the pair of analog signals from the digital-to-analog converter and transmits them to the first duty cycle corrector.

The effect of the present invention is to use the phase detection module to quickly generate the phase detection result for the digital-to-analog converter to generate the pair of analog signals corresponding to the digital code, so that the duty cycle of the pair of second internal clock signals is quickly adjusted to the predetermined duty cycle, and the corresponding digital code is obtained and stored at the same time. In this way, the duty cycle correction device can quickly complete the duty cycle adjustment operation.

2: Duty cycle correction device

3: First working cycle corrector

4: Integrator

5: Phase detection module

6: Digital to Analog Converter

7: First switch

8: Comparator

9: The third switch

11: Duty cycle corrector

12: Pump circuit

13: Comparator

14: Digital to Analog Converter

31: Bias circuit

32: Input and output pairs

33: First input pair

34: Second input pair

41: Pump circuit

42: First capacitor

43: Second capacitor

51: Second working cycle corrector

52: Phase detector

53: Second switch

61: Control circuit

62~64: Bias circuit

65~67: Current mirror circuit

81: Comparison circuit

82:Logic circuit

311~315: NMOS transistor

316, 317: Voltage source

321: First transistor

322: Second transistor

331: The third transistor

332: The fourth transistor

341: The fifth transistor

342: Sixth transistor

411~414: switch

415~418: Current source

810~815: MOS transistor

816~819: PMOS transistor

821~824: Anti-lock

825, 826: Anti-gate

clk1, clkn1: first internal clock signal

clk2, clkn2: second internal clock signal

creg, cregb: analog signal

creg’, cregb’: analog signal output

creg[0], cregb[0]: control signal

creg[1], cregb[1]: control signal

creg[2], cregb[2]: control signals

C1, C2: capacitors

Cr: Comparison results

CLK, CLKn: internal clock signal

CREG, CREGb: analog signal

DK: control signal

En1, En2: Enable signal

fck, fckb: feedback clock signal

fckr, fckbr: feedback clock signal

FCK, FCKb: feedback clock signal

N1: First transistor

N2: Second transistor

N3: The third transistor

N4: The fourth transistor

Pr: Phase detection result

SW1: switch

tck: system clock cycle

T1~T3: time

Vb: Bias voltage

Vcc: power supply voltage

VS: voltage source

xclk, xclkn: external clock signal

XCLK, XCLKn: external clock signal

Other features and effects of the present invention will be clearly presented in the implementation method with reference to the drawings, wherein: FIG. 1 is a circuit block diagram illustrating an existing duty cycle correction device; FIG. 2 is a schematic diagram illustrating the time required for the existing duty cycle correction device to complete the duty cycle adjustment operation; FIG. 3 is a circuit block diagram illustrating an implementation of the duty cycle correction device of the present invention; FIG. 4 is a circuit diagram illustrating the first duty cycle corrector of the implementation; FIG. 5 is a circuit diagram illustrating the integrator of the implementation; FIG. 6 is a circuit diagram illustrating the comparator of the implementation; FIG. 7 is a circuit diagram illustrating the digital-to-analog converter of the implementation; and FIG. 8 is a schematic diagram illustrating the time required for the implementation to complete the duty cycle adjustment operation.

The present invention will be described in detail through the following embodiments and the attached drawings to help those with ordinary knowledge in the technical field of the present invention understand the purpose, features and efficacy of the present invention. It should be noted that in the following description and the scope of the patent application, the terms "including" and "comprising" are used in an open manner and should not be interpreted as closed terms such as "consisting of..." In addition, the term "coupled" is intended to indicate indirect or direct coupling. Therefore, if one device is coupled to another device, the connection can be through direct coupling or through indirect coupling via other devices and connections. In addition, in the content described in the present invention, terms such as "first", "second" and "third" are used to distinguish between elements, rather than to limit the elements themselves or to indicate a specific order of elements.

Referring to FIG. 3 , an embodiment of a duty cycle correction device 2 of the present invention is described. The duty cycle correction device 2 comprises a first duty cycle corrector 3, an integrator 4, a phase detection module 5, a digital to analog converter (DAC) 6, a first switch 7, a comparator 8 and a third switch 9.

The first duty cycle corrector 3 is used to receive a pair of external clock signals xclk, xclkn, and generate a pair of first internal clock signals clk1, clkn1 according to the pair of external clock signals xclk, xclkn. In this embodiment, the pair of external clock signals xclk, xclkn are complementary signals, and the pair of first internal clock signals clk1, clkn1 are complementary signals.

The integrator 4 is coupled to the first duty cycle corrector 3 to receive the pair of first internal clock signals clk1, clkn1, and generates a pair of feedback clock signals fck, fckb (which are analog signals) according to the pair of first internal clock signals clk1, clkn1, and transmits the pair of feedback clock signals fck, fckb to the first duty cycle corrector 3, so that the first duty cycle corrector 3 continuously adjusts the respective duty cycles of the pair of first internal clock signals clk1, clkn1 to a predetermined duty cycle according to the pair of feedback clock signals fck, fckb. In this embodiment, the pair of feedback clock signals fck, fckb are complementary signals, and the predetermined duty cycle is 50%. It should be noted that, since data transmission is most reliable when the duty cycle is equal to 50%, in order to ensure that the duty cycle has sufficient design limits, a duty cycle correction device 2 is required to correct the duty cycle of the internal clock signal to 50%.

The phase detection module 5 is used to receive the pair of external clock signals xclk, xclkn, and generate a pair of second internal clock signals clk2, clkn2 according to the pair of external clock signals xclk, xclkn, and is coupled to the first duty cycle corrector 3 to receive one of the pair of first internal clock signals clk1, clkn1. When the duty cycles of the pair of first internal clock signals clk1, clkn1 are adjusted to the predetermined duty cycle, the phase detection module 5 compares the phase of the pair of first internal clock signals clk1, clkn1 with the phase of the pair of second internal clock signals clk2, clkn2 to generate a phase detection result Pr. In the present embodiment, the pair of second internal clock signals clk2 and clkn2 are complementary signals. It should be noted that in the present embodiment, the pair of first internal clock signals clk1 and clkn1 is explained by taking the first internal clock signal clk1 as an example, and the first internal clock signal clk1 is used as a reference clock signal for the phase detection module 5 to use as a benchmark for phase comparison, and the pair of second internal clock signals clk2 and clkn2 is explained by taking the second internal clock signal clk2 as an example, but is not limited thereto. In other embodiments, the one of the pair of first internal clock signals clk1 and clkn1 can be the first internal clock signal clkn1, and the one of the pair of second internal clock signals clk2 and clkn2 can be the second internal clock signal clkn2. Therefore, for the sake of simplicity, the one of the pair of first internal clock signals clk1 and clkn1 is referred to as the first internal clock signal clk1, and the one of the pair of second internal clock signals clk2 and clkn2 is referred to as the second internal clock signal clk2.

In this embodiment, the phase detection module 5 includes a second duty cycle corrector 51, a phase detector 52 and a second switch 53.

The second duty cycle corrector 51 is used to receive the pair of external clock signals xclk, xclkn, and generate the pair of second internal clock signals clk2, clkn2 according to the pair of external clock signals xclk, xclkn. The phase detector 52 is coupled to the first duty cycle corrector 3 to receive the first internal clock signal clk1, and is coupled to the second duty cycle corrector 51 to receive the second internal clock signal clk2, and compares the phases of the first internal clock signal clk1 and the second internal clock signal clk2 to generate the phase detection result Pr. In this embodiment, the phase detector 52 compares the phases of the first internal clock signal clk1 and the second internal clock signal clk2, that is, compares the rising edge position of the first internal clock signal clk1 and the second internal clock signal clk2 in a single cycle. The second switch 53 is coupled between the phase detector 52 and the digital-to-analog converter 6, and is controlled by a second switching signal to be turned on or off. When the respective duty cycles of the pair of first internal clock signals clk1 and clkn1 are adjusted to the predetermined duty cycle, the second switch 53 is controlled by the second switching signal to switch from being turned off to being turned on, and receives the phase detection result Pr from the phase detector 52 and transmits it to the digital-to-analog converter 6. The phase detector 52 can be implemented by, for example, a phase difference determiner, a timer, and a logic circuit.

It should be noted that the mechanism of the first duty cycle corrector 3 and the second duty cycle corrector 51 in adjusting the duty cycles of the pair of first internal clock signals clk1, clkn1 and the pair of second internal clock signals clk2, clkn2 is to pull up or down the waveform of the internally generated signal to determine the duty cycle, so that the duty cycle will be related to the rising edge position (the position of the voltage rise) of the first internal clock signal and the second internal clock signal in a single cycle. Therefore, by using the phase detector 52 to compare the rising edge position of the first internal clock signal clk1 and the second internal clock signal clk2 in each single cycle, it can be quickly determined how to adjust the duty cycle of the second internal clock signal clk2. For example, the duty cycle of the first internal clock signal clk1 is 50%, and the duty cycle of the second internal clock signal clk2 is 40%. When the rising edge position of the second internal clock signal clk2 lags behind the rising edge position of the first internal clock signal clk1, the waveform of the signal generated inside the second duty cycle corrector 51 needs to be pulled up, so that after the second internal clock signal clk2 is adjusted, its adjusted rising edge position will lead its rising edge position before adjustment (that is, the duty cycle of the second internal clock signal clk2 increases). On the contrary, if the duty cycle of the second internal clock signal clk2 is 60%, when the rising edge position of the second internal clock signal clk2 leads the rising edge position of the first internal clock signal clk1, the waveform of the signal generated inside the second duty cycle corrector 51 needs to be pulled down, so that after the second internal clock signal clk2 is adjusted, its adjusted rising edge position will lag behind its rising edge position before adjustment (that is, the duty cycle of the second internal clock signal clk2 is reduced).

The digital-to-analog converter 6 is coupled to the phase detection module 5 to receive the phase detection result Pr, and generates a pair of analog signals creg, cregb corresponding to a digital code according to the phase detection result Pr, and transmits the pair of analog signals creg, cregb to the phase detection module 5, so that the phase detection module 5 adjusts the respective working cycles of the pair of second internal clock signals clk2, clkn2 according to the pair of analog signals creg, cregb. It should be noted that the digital-to-analog converter 6 sequentially receives a plurality of phase detection results Pr and sequentially generates a plurality of pairs of analog signals creg, cregb accordingly, so that the phase detection module 5 can adjust the respective duty cycles of the pair of second internal clock signals clk2, clkn2 until the respective duty cycles of the pair of second internal clock signals clk2, clkn2 are adjusted to the predetermined duty cycles. When the duty cycle of the pair of second internal clock signals clk2 and clkn2 is adjusted to the predetermined duty cycle, the digital-to-analog converter 6 stores the digital code corresponding to the pair of analog signals creg and cregb in a memory (not shown) inside the digital-to-analog converter 6, and when the digital-to-analog converter 6 stores the digital code, the second switch 53 is controlled by the second switching signal to switch from conducting to non-conducting, so that the phase detection module 5 stops operating. In this embodiment, the pair of analog signals are complementary signals. The digital-to-analog converter 6 can know whether the duty cycle of the pair of second internal clock signals clk2 and clkn2 is adjusted to the predetermined duty cycle according to the phase detection result Pr. For example, when the phase detection result Pr indicates that the rising edge positions of the first internal clock signal clk1 and the second internal clock signal clk2 in a single cycle are the same, that is, the respective duty cycles of the pair of second internal clock signals clk2 and clkn2 are adjusted to the predetermined duty cycle, the digital-to-analog converter 6 stores the digital code corresponding to the corresponding pair of analog signals creg and cregb in the register.

The first switch 7 is coupled between the first duty cycle corrector 3 and the digital-to-analog converter 6. When the duty cycles of the pair of second internal clock signals clk2 and clkn2 are adjusted to the predetermined duty cycle, and the digital-to-analog converter 6 stores the digital code corresponding to the corresponding pair of analog signals creg and cregb, the first switch 7 is controlled by a first switching signal to switch from non-conduction to conduction, and receives the pair of analog signals creg and cregb from the digital-to-analog converter 6 and transmits them to the first duty cycle corrector 3.

The comparator 8 is coupled to the integrator 4 to receive the pair of feedback clock signals fck, fckb, and generates a comparison result Cr according to the pair of feedback clock signals fck, fckb.

The third switch 9 is coupled between the comparator 8 and the digital-to-analog converter 6 and is controlled by a third switching signal to be turned on or off. When the duty cycles of the pair of second internal clock signals clk2 and clkn2 are adjusted to the predetermined duty cycle, and the digital-to-analog converter 6 stores the digital code corresponding to the pair of analog signals creg and cregb, the third switch 9 is controlled by the third switching signal to switch from non-conduction to conduction, and receives the comparison result Cr from the comparator 8 and transmits it to the digital-to-analog converter 6, so that the digital-to-analog converter 6 changes from originally generating the pair of analog signals creg and cregb according to the phase detection result Pr to generating a pair of analog signal outputs creg' and cregb' according to the comparison result Cr.

It should be noted that the duty cycle correction device 2 of the present embodiment further includes a controller (not shown) for providing the first switching signal, the second switching signal and the third switching signal to respectively control the first switch 7, the second switch 53 and the third switch 9 to determine when to conduct or not conduct. The controller can generate the first switching to the third switching signal according to the phase detection result Pr or the comparison result Cr. The controller can also generate the first switching to the third switching signal by counting a counter. The configuration and operation of the controller are well known to those skilled in the art, and for the sake of brevity, they are not described here.

Further referring to FIG. 4 , an embodiment of the first duty cycle corrector 3 is described. The first duty cycle corrector 3 includes a bias circuit 31, an input-output pair 32, a first input pair 33 and a second input pair 34.

The bias circuit 31 includes five NMOS transistors 311, 312, 313, 314, 315 and two voltage sources 316, 317, which are used to receive a bias voltage Vb and an enable signal En1. The input-output pair 32 includes a first transistor 321 and a second transistor 322. The first transistor 321 and the second transistor 322 each have a first end, a second end coupled to the bias circuit 31, and a control end. The first ends of the first transistor 321 and the second transistor 322 cooperate to output the pair of first internal clock signals clk1, clkn1. The control ends of the first transistor 321 and the second transistor 322 cooperate to receive the pair of external clock signals xclk, xclkn. The first input pair 33 includes a third transistor 331 and a fourth transistor 332. The third transistor 331 and the fourth transistor 332 each have a first end, a second end coupled to the bias circuit 31, and a control end. The control ends of the third transistor 331 and the fourth transistor 332 cooperate to receive the pair of feedback clock signals fck, fckb. The first end of the third transistor 331 is coupled to the first end of the first transistor 321. The first end of the fourth transistor 332 is coupled to the first end of the second transistor 322. The second input pair 34 includes a fifth transistor 341 and a sixth transistor 342, and the fifth transistor 341 and the sixth transistor 342 each have a first end for receiving a supply voltage Vcc, a second end, and a control end. The control terminals of the fifth transistor 341 and the sixth transistor 342 cooperate to receive the pair of analog signals creg and cregb. The second terminal of the fifth transistor 341 is coupled to the first terminal of the first transistor 321. The second terminal of the sixth transistor 342 is coupled to the first terminal of the second transistor 322. The first transistor 321, the second transistor 322, the third transistor 331 and the fourth transistor 332 are each NMOS transistors. The fifth transistor 341 and the sixth transistor 342 are each PMOS transistors. In this embodiment, the configuration of the second duty cycle corrector 51 is similar to that of the first duty cycle corrector 3, which is well known to those skilled in the art, and will not be described in detail for the sake of brevity.

Further referring to FIG. 5 , an embodiment of the integrator 4 is described. The integrator 4 includes a pump circuit 41, a first capacitor 42 and a second capacitor 43.

The pump circuit 41 is coupled to the first duty cycle corrector 3 to receive the pair of first internal clock signals clk1, clkn1, and generates the pair of feedback clock signals fck, fckb according to the pair of first internal clock signals clk1, clkn1. The pump circuit 41 includes four switches 411, 412, 413, 414, and four current sources 415, 416, 417, 418. The switches 411, 414 are controlled by the first internal clock signal clk1 to be turned on or off. The switches 412, 413 are controlled by the first internal clock signal clkn1 to be turned on or off. A common connection point of the switches 411, 412 provides the feedback clock signal fck. A common connection point of the switches 413 and 414 provides the feedback clock signal fckb. The first capacitor 42 is coupled between the common connection point of the switches 411 and 412 of the pump circuit 41 and a ground terminal. The second capacitor 43 is coupled between the common connection point of the switches 413 and 414 of the pump circuit 41 and the ground terminal.

Further referring to FIG. 6 , an embodiment of the comparator 8 is described. The comparator 8 includes a comparison circuit 81 and a logic circuit 82.

The comparison circuit 81 is coupled to the integrator 4 to receive the pair of feedback clock signals fck, fckb and a control signal DK. The comparison circuit 81 includes six NMOS transistors 810, 811, 812, 813, 814, 815 and four PMOS transistors 816, 817, 818, 819. The comparison circuit 81 determines whether to compare the potentials of the pair of feedback clock signals fck, fckb according to the control signal DK to generate a comparison signal. The logic circuit 82 is coupled to the comparison circuit 81 to receive the comparison signal and generates the comparison result Cr according to the comparison signal. The logic circuit 82 includes four anti-gates 821, 822, 823, 824 and two anti-AND gates 825, 826. In this embodiment, when the control signal DK has a high logic level, the comparison circuit 81 performs comparison; when the control signal DK has a low logic level, the comparison circuit 81 stops comparing.

Further referring to FIG. 7, an embodiment of the digital-to-analog converter 6 is described. FIG. 7 takes the digital-to-analog converter 6 generating the pair of analog signal outputs creg' and cregb' according to the comparison result Cr as an example. The digital-to-analog converter 6 includes a control circuit 61, a plurality of bias circuits 62, 63, 64, and a plurality of current mirror circuits 65, 66, 67. In this embodiment, the number of bias circuits is three, and the number of current mirror circuits is three, but it is not limited thereto. In other embodiments, the number of bias circuits is the same as the number of current mirror circuits, and the number may be two or more than three.

The control circuit 61 is coupled to the third switch 9 to receive the comparison result Cr from the comparator 8, and generates a plurality of pairs of control signals creg[0], cregb[0], creg[1], cregb[1], creg[2], cregb[2] according to the comparison result Cr. Each of the bias circuits 62, 63, 64 includes a first transistor N1, a second transistor N2, and a voltage source VS connected in series in sequence. The first transistor N1 and the second transistor N2 each have a first terminal, a second terminal, and a control terminal. The control terminal of the first transistor N1 is used to receive an enable signal En2. The first end and the second end of the second transistor N2 are coupled to the second end of the first transistor N1 and the voltage source VS, respectively, and the control end of the second transistor N2 is used to receive the bias voltage Vb. Each of the current mirror circuits 65, 66, and 67 includes a third transistor N3 and a fourth transistor N4. The third transistor N3 and the fourth transistor N4 each have a first end, a second end coupled to the first end of the first transistor N1, and a control end. The first ends of the third transistor N3 and the fourth transistor N4 are used to cooperate to output the pair of analog signal outputs creg’ and cregb’. The control terminals of the third transistor N3 and the fourth transistor N4 are coupled to the control circuit 61 and cooperate to receive a pair of control signals among the plurality of pairs of control signals creg[0], cregb[0], creg[1], cregb[1], creg[2], cregb[2], and are controlled by the corresponding pair of control signals to be turned on or off.

Referring to FIG. 3 and FIG. 8, FIG. 8 is a schematic diagram showing the time required for the duty cycle correction device 2 to adjust the pair of first internal clock signals clk1, clkn1 and the pair of second internal clock signals clk2, clkn2 to the predetermined duty cycle and obtain the corresponding digital code (i.e., complete the duty cycle adjustment operation). Symbol fckr is a feedback clock signal corresponding to the first internal clock signal clk1 (whose duty cycle has been adjusted to the reference clock signal of the predetermined duty cycle). Symbol fckbr is a feedback clock signal corresponding to the second internal clock signal clk2.

First, before time T2, the first switch 7, the second switch 53 and the third switch 9 are not conducting. The first duty cycle corrector 3 quickly adjusts the duty cycles of the pair of first internal clock signals clk1, clkn1 to the predetermined duty cycle (the required time is 32 system clock cycles tck) according to the pair of feedback clock signals fck, fckb. The digital-to-analog converter 6 generates a pair of analog signals creg, cregb corresponding to the preset digital code 32 according to the preset input signal. Then, from time T2 to time T3, the first switch 7 and the third switch 9 are continuously not conducting, and the second switch 53 is switched from not conducting to conducting. The phase detector 52 generates a plurality of phase detection results Pr in sequence, and the digital-to-analog converter 6 generates a plurality of pairs of analog signals creg, cregb corresponding to a plurality of digital codes (48, 56, 60, 62 respectively) in sequence according to the plurality of phase detection results Pr, so that the second duty cycle corrector 51 can adjust the duty cycle of the pair of second internal clock signals clk2, clkn2 in sequence accordingly. As can be seen from FIG8 , until the pair of analog signals creg, cregb with the corresponding digital code 62 is used to adjust the duty cycle of the pair of second internal clock signals clk2, clkn2, the feedback clock signals fckr, fckbr gradually become the same, that is, the duty cycle of the second internal clock signal clk2 is the same as the first internal clock signal clk1, and the duty cycle of the second internal clock signal clk2 is adjusted to meet the required predetermined duty cycle. At this time, the digital-to-analog converter 6 stores the digital code (i.e., 62) corresponding to the pair of analog signals creg, cregb, and the duty cycle correction device 2 completes the duty cycle adjustment operation. In this case, since the phase detector 52 directly compares the rising edge position of the first internal clock signal clk1 and the second internal clock signal clk2 in a single cycle (there is no need to wait until the strength difference of a pair of feedback clock signals reaches a specific strength value as in the existing duty cycle correction device before the comparator can generate a comparison result signal to the digital-to-analog converter), the time required to generate each phase detection result Pr is only about 2 system clock cycles tck. Therefore, the time required for the digital-to-analog converter 6 to generate each pair of analog signals creg and cregb according to each phase detection result Pr is about 2 system clock cycles tck. Thus, in the case of FIG. 8 , the duty cycle correction device 2 needs to spend a total of 32+4*2=40 system clock cycles tck operating time to adjust the pair of first internal clock signals clk1, clkn1 and the pair of second internal clock signals clk2, clkn2 to the predetermined duty cycle, and obtain the digital code corresponding to the analog signal creg, cregb that can adjust the second internal clock signal clk2 to the predetermined duty cycle (i.e., complete the duty cycle adjustment operation). Compared with the existing duty cycle correction device that needs 992 system clock cycles tck operating time to complete the duty cycle adjustment operation, the duty cycle correction device 2 of the present invention can quickly complete the duty cycle adjustment operation.

It should be noted that the digital-to-analog converter 6 uses each phase detection result Pr and executes a binary search algorithm to determine the corresponding bit of a digital code in each conversion cycle, thereby obtaining digital codes 48, 56, 60, and 62. This can reduce the number of times the phase detector 52 is used to compare the phases of the first internal clock signal clk1 and the second internal clock signal clk2 (because each digital code is related to a phase detection result generated by the phase detector 52). After time T3, the first switch 7 and the third switch 9 are switched from non-conductive to conductive, and the second switch 53 is switched from conductive to non-conductive (the phase detection module 5 stops operating). The first duty cycle corrector 3 uses the pair of feedback clock signals fck and fckb to adjust the duty cycle of the pair of first internal clock signals clk1 and clkn1 at any time.

In summary, since the duty cycle correction device 2 of the present invention uses the phase detection module 5 to quickly generate the phase detection result Pr for the digital-to-analog converter 6 to generate the pair of analog signals creg and cregb corresponding to the digital code, the duty cycle of the second internal clock signal clk2 is quickly adjusted to the predetermined duty cycle, and the corresponding digital code is quickly obtained and stored. In this way, the duty cycle correction device 2 of the present invention can complete the duty cycle adjustment operation faster.

However, the above is only an example of the implementation of the present invention, and it cannot be used to limit the scope of the implementation of the present invention. All simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still within the scope of the patent of the present invention.

2: duty cycle correction device 3: first duty cycle corrector 4: integrator 5: phase detection module 6: digital-to-analog converter 7: first switch 8: comparator 9: third switch 41: pump circuit 42: first capacitor 43: second capacitor 51: second duty cycle corrector 52: phase detector 53: second switch clk1, clkn1: first internal clock signal clk2, clkn2: second internal clock signal creg, cregb: analog signal creg’, cregb’: analog signal output Cr: comparison result fck, fckb: feedback clock signal Pr: phase detection result xclk, xclkn: external clock signal

Claims (8)

A duty cycle correction device comprises: A first duty cycle corrector for receiving a pair of external clock signals and generating a pair of first internal clock signals according to the pair of external clock signals; An integrator coupled to the first duty cycle corrector to receive the pair of first internal clock signals and generate a pair of feedback clock signals according to the pair of first internal clock signals, and transmit the pair of feedback clock signals to the first duty cycle corrector, so that the first duty cycle corrector also adjusts the duty cycles of the pair of first internal clock signals according to the pair of feedback clock signals; A phase detection module, for receiving the pair of external clock signals, and generating a pair of second internal clock signals according to the pair of external clock signals, and coupled to the first duty cycle corrector to receive one of the pair of first internal clock signals, and when the duty cycles of the pair of first internal clock signals are adjusted to a predetermined duty cycle, the phase of the one of the pair of first internal clock signals is compared with one of the pair of second internal clock signals to generate a phase detection result; A digital-to-analog converter is coupled to the phase detection module to receive the phase detection result, and generates a pair of analog signals corresponding to a digital code according to the phase detection result, and transmits the pair of analog signals to the phase detection module, so that the phase detection module also adjusts the respective duty cycles of the pair of second internal clock signals according to the pair of analog signals. When the pair of analog signals adjusts the respective duty cycles of the pair of second internal clock signals to the predetermined duty cycle, the digital-to-analog converter stores the digital code corresponding to the pair of analog signals; A first switch coupled between the first duty cycle corrector and the digital-to-analog converter. When the digital-to-analog converter stores the digital code corresponding to the pair of analog signals, the first switch is controlled by a first switching signal to switch from non-conduction to conduction, and receives the pair of analog signals from the digital-to-analog converter and transmits them to the first duty cycle corrector; A comparator coupled to the integrator to receive the pair of feedback clock signals and generate a comparison result according to the pair of feedback clock signals; and A third switch is coupled between the comparator and the digital-to-analog converter and is controlled by a third switching signal to be turned on or off. When the digital-to-analog converter stores the digital code corresponding to the pair of analog signals, the third switch is controlled by the third switching signal to switch from off to on, and receives the comparison result from the comparator and transmits it to the digital-to-analog converter, so that the digital-to-analog converter also generates a pair of analog signal outputs according to the comparison result. Wherein, the comparator includes: A comparison circuit is coupled to the integrator to receive the pair of feedback clock signals, and compares the potentials of the pair of feedback clock signals to generate a comparison signal; and A logic circuit is coupled to the comparison circuit to receive the comparison signal and generate the comparison result according to the comparison signal. The duty cycle correction device as described in claim 1, wherein the phase detection module includes: a second duty cycle corrector for receiving the pair of external clock signals and generating the pair of second internal clock signals according to the pair of external clock signals; a phase detector coupled to the first duty cycle corrector to receive the one of the pair of first internal clock signals, and coupled to the second duty cycle corrector to receive the one of the pair of second internal clock signals, and performing a phase comparison between the one of the pair of first internal clock signals and the one of the pair of second internal clock signals to generate the phase detection result; and A second switch is coupled between the phase detector and the digital-to-analog converter and is controlled by a second switching signal to be turned on or off. When the respective duty cycles of the pair of first internal clock signals are adjusted to the predetermined duty cycle, the second switch is controlled by the second switching signal to switch from off to on, and receives the phase detection result from the phase detector and transmits it to the digital-to-analog converter. When the digital-to-analog converter stores the digital code corresponding to the pair of analog signals, the second switch is controlled by the second switching signal to switch from on to off. A duty cycle correction device as described in claim 1, wherein the phase detection module performs a phase comparison between the one of the pair of first internal clock signals and the one of the pair of second internal clock signals, by comparing a rising edge position of a single cycle of the one of the pair of first internal clock signals and the one of the pair of second internal clock signals. The duty cycle correction device as described in claim 1, wherein the digital-to-analog converter obtains the digital code based on the phase detection result and executes a binary search algorithm. The duty cycle correction device as described in claim 1, wherein the digital-to-analog converter comprises: A control circuit coupled to the third switch to receive the comparison result from the comparator and generate a plurality of pairs of control signals according to the comparison result; A plurality of bias circuits, each of which comprises a first transistor, a second transistor and a voltage source connected in series in sequence, the first transistor and the second transistor each having a first end, a second end, and a control end, the control end of the first transistor is used to receive an enable signal, the first end and the second end of the second transistor are respectively coupled to the second end of the first transistor and the voltage source, and the control end of the second transistor is used to receive a bias voltage; and A plurality of current mirror circuits, each of which includes a third transistor and a fourth transistor, each of which has a first end, a second end coupled to the first end of the first transistor, and a control end, the first ends of the third transistor and the fourth transistor are used to cooperate to output the pair of analog signals, the control ends of the third transistor and the fourth transistor are coupled to the control circuit and cooperate to receive a pair of control signals from the plurality of pairs of control signals, and are controlled by the corresponding pair of control signals to conduct or not conduct. The duty cycle correction device as described in claim 1, wherein the integrator comprises: a pump circuit coupled to the first duty cycle corrector to receive the pair of first internal clock signals and generate the pair of feedback clock signals according to the pair of first internal clock signals; a first capacitor coupled between the pump circuit and a ground terminal; and a second capacitor coupled between the pump circuit and the ground terminal. The duty cycle correction device as described in claim 1, wherein the first duty cycle corrector comprises: A bias circuit; An input-output pair, comprising a first transistor and a second transistor, the first transistor and the second transistor each having a first end, a second end coupled to the bias circuit, and a control end, the first ends of the first transistor and the second transistor cooperate to output the pair of first internal clock signals, and the control ends of the first transistor and the second transistor cooperate to receive the pair of external clock signals; A first input pair, including a third transistor and a fourth transistor, each of the third transistor and the fourth transistor has a first end, a second end coupled to the bias circuit, and a control end, the control ends of the third transistor and the fourth transistor cooperate to receive the pair of feedback clock signals, the first end of the third transistor is coupled to the first end of the first transistor, and the first end of the fourth transistor is coupled to the first end of the second transistor; and A second input pair includes a fifth transistor and a sixth transistor. The fifth transistor and the sixth transistor each have a first end for receiving a supply voltage, a second end, and a control end. The control ends of the fifth transistor and the sixth transistor cooperate to receive the pair of analog signals. The second end of the fifth transistor is coupled to the first end of the first transistor, and the second end of the sixth transistor is coupled to the first end of the second transistor. A duty cycle correction device as described in claim 1, wherein the pair of external clock signals are complementary signals, the pair of first internal clock signals are complementary signals, the pair of feedback clock signals are complementary signals, the pair of second internal clock signals are complementary signals, the pair of analog signals are complementary signals, and the predetermined duty cycle is 50%.