JPH04910A - Delay circuit - Google Patents

Abstract

PURPOSE:To obtain high-accurate delay time equally devided by the number of tandem circuits by controlling the operational current of a circuit by comparing the phase of a pulse to an inverter in the first step of the tandem circuits with the phase of an output signal in the final step. CONSTITUTION:A clock pulse CLK is supplied to the input of a first-step inverter circuit IV1 constituting the delay circuit. This CLK and a delay output signal DLN in the final step are inputted to a phase comparator circuit. Phase comparison output signals (up) and (down) are inputted to a voltage control circuit so as to generate a control voltage VC integrated into these (up) and (down). This control voltage VC is fed back to the current control terminals of inverter circuits IV1-IVN constituting the delay circuit so as to control the operational currents of these tandem inverter circuits. The delay time equally N-dividing one cycle of the clock pulse CLK can be obtained by the respective inverter circuits.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a delay circuit, and can be effectively applied to, for example, a delay circuit mounted on a semiconductor integrated circuit device constituted by a MOSFET (insulated gate field effect transistor). It is related to technology.

[Conventional technology]

As a delayed pulse generation circuit using an MO3 type inverter circuit, there is "Practical Electronic Handbook (1)" published by CQ Publishing, June 1, 1978, 1 page 360.

[Problem to be solved by the invention]

In the MO3 type inverter circuit as mentioned above, MOSFE
There is a problem in that the delay time cannot be set with high precision due to relatively large process variations in T and the element characteristics of the capacitor.

An object of the present invention is to provide a delay circuit that can set a delay time with high accuracy without being affected by process variations.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a voltage signal is formed by using multiple inverter circuits connected in series and comparing the phase of periodic pulses supplied to the input of the first-stage inverter circuit with the output signal of the final-stage inverter circuit. The operating current of the inverter circuit is controlled, and a delay signal is obtained from the output of any one of the plurality of inverter circuits.

[Function] According to the above-described means, it is possible to obtain a highly accurate delay time equally divided by the cascaded inverter circuit without being affected by process variations, based on one period of the periodic pulse signal. can.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a delay circuit according to the present invention. Each circuit in the figure is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon using known semiconductor integrated circuit manufacturing techniques.

Inverter circuits IVI to IVN are connected in series and used as a delay circuit. However, if things continue as they are, the characteristics of the elements constituting the inverter circuit will vary relatively greatly due to the influence of process variations, and the delay time will vary accordingly.

In this embodiment, a clock pulse CLK is supplied to the input of the first stage inverter circuit 1rV1 constituting the delay circuit. This clock pulse CLK and the delayed output signal DLN of the final stage inverter circuit IVN are input to the phase comparison circuit. This phase comparator circuit compares both the above signals CLK and D.
An up signal up and a down signal dwn are formed corresponding to the phase difference with LN. These phase comparison output signals up and dwn are input to the voltage control circuit.

The voltage control circuit corresponds to a loop filter in a known PLL (phase locked loop), and generates a control voltage VC integrated with the phase comparison outputs up and dwn.

This control voltage VC is fed back to the current side m terminals of the inverter circuits IVI to IVN constituting the delay circuit as described above, and controls the operation t''& of these cascade-connected inverter circuits IVI to IVN.

FIG. 2 shows a specific circuit diagram of one embodiment of the above inverter circuit.

In the figure, one inverter circuit is exemplarily shown as a representative. Although not particularly limited, P channel MO
3FETQ2 and N-channel MO3FETQ3 constitute a CMOS inverter circuit. That is, both M.O.
The gates of SFETQ2 and Q3 are commonly connected to form the input terminal IN, and the common drains are connected to the output terminal OUT.
Configure.

This output terminal is connected to the input of the next-stage CMOS inverter circuit as shown in FIG. 1, and is used as a delay signal terminal if necessary.

Although not particularly limited, the above P-channel MO3FETQ
2 is a P-channel MO3F ETQ of the same conductivity type.
1 are connected in series and supplied with an operating voltage Vcc. This MO3FETQI has a voltage of /'f! It acts as an L-flow conversion element, and the above-mentioned control pressure (C) is supplied to its gate.

That is, the operating current of MO3FETQ1 is increased as the limiting at pressure VC supplied to its gate is decreased. P-channel MO3FETQ2 and N-channel MO3F receive clock pulses supplied to input terminal IN
ETQ3 performs switching operations in a complementary manner. When the P-channel MO3FET Q2 is in the on state, a charge-up operation is performed according to the operating current of the MO3FET QI using the parasitic capacitance of its output terminal and the input capacitance of the next stage CMOS inverter circuit as a load. Since the charge amplifier time is controlled by the operating current of the MO3FETQI, it is possible to adjust the delay time of the inverter circuit using the control voltage VC.

Note that when P-channel MOSFET Q2 is off and N-channel MO3FET Q3 is on, the discharge time is determined by the conductance characteristics of N-channel MOSFET Q3 and the load capacitance.

Therefore, instead of the P-channel MO5FETQ1, an N-channel MOS FET may be provided in series with the MO3FETQ3, and the above-described control pressure VC may be supplied to its gate.

However, it must be noted that as the control #tEEVC decreases, the discharge current of the load capacitor decreases accordingly, so the delay time changes to become longer.

Above system? MOS FETQ 1 receiving ilt pressure VC
is the P channel M that constitutes the CMOS inverter P.
It is sufficient if it is connected in series with O5FETQ2. Therefore, the power supply voltage Vcc is supplied to the source of P-channel MO3FETQ2, and the control voltage is applied between its drain and the drain of N-channel MO3FETQ3, in other words, between the drain of P-channel MO3FETQ2 and the output terminal OUT. A configuration may also be adopted in which a P-channel MOSFET Q1 that receives VC is provided. This also applies to the case where the delay time is controlled using an N-channel MO3FET.

FIG. 3 shows a specific circuit diagram of one embodiment of the phase comparison circuit and voltage control circuit.

The phase comparator circuit is composed of the following circuits. Clock pulse CLK and delay signal DLN are connected to exclusive OR circuit EX
is input. The output signal of this exclusive OR circuit EX is an AND signal using the mask signal MSK as a control signal.
The signal is supplied to one input of two AND gate circuits G2 and G3 through the gate circuit G1. AND gate circuit G2
The other input of is supplied with the delay signal DLN. The other input of the AND gate circuit G3 is an inverter circuit I.
A delay signal DLN inverted by VO is supplied. An amplifier signal is output from the output of the gate circuit G2,
A down signal is output from the output of the gate circuit 1IiG3.

The voltage control circuit consists of the following circuits. The amplifier signal formed by the AND gate circuit G2 of the phase comparison circuit described above is supplied to the gate of the N-channel type switch MO3FETQ4. A constant current source C3I for charging up is provided on the drain side of this MO5FETQ4. The down signal formed by the AND gate circuit G3 of the above phase comparator circuit is connected to the N-channel type switch MO3.
Supplied to the gate of FETQ5. This MO5FETQ
A constant current source C32 for discharging is provided on the source side of the transistor 5. The constant current sources C3I and C32 are set so that their current values are equal, although not particularly limited. A capacitor C is provided at the connection point between the switch MO3FET Q4 and G5, and a control voltage VC is formed by charging and discharging the capacitor C.

In FIG. 1, the phase comparator circuit uses the clock pulse CLK.
When the phase of the delayed signal DLN is ahead of the
Since the delay signal DLN reaches the high level (logic "1°") first, the AND gate circuit G2 opens its gate and generates a pulse with a pulse width corresponding to the phase difference formed by the exclusive OR circuit EX. is output as an amplifier signal.As a result, the capacitor C is charged up for a time corresponding to the pulse width, increasing the control pressure.When the control pressure V C increases, the P channel M
The current flowing through OS FETQ i etc. becomes smaller and its delay time increases. Thereby, as shown in the timing diagram of FIG. 4, the two CLK and DLN are correctly brought into phase alignment.

Furthermore, when the phase of the delay signal DLN is delayed with respect to the clock pulse CLK, the phase comparator circuit detects the delay signal D
Since LN becomes high level (logic @01) with a delay, the output of the inverter circuit IVO becomes high level. As a result, the AND gate circuit G3 opens its gate, and a pulse having a pulse width corresponding to the phase difference formed by the exclusive OR circuit EX is output as a down signal. As a result, the capacitor C is discharged for a time corresponding to the pulse width, and the control voltage is lowered. When the above control it pressure VC becomes low, the P channel MO
The current flowing through the 3FETQ1 etc. becomes larger and its delay time is reduced. As a result, the phases of the two CLK and DLN are matched as shown in the timing diagram of FIG. 4.

In this way, as shown in the timing chart shown in FIG. 4, the clock pulse CLK and the delay signal DLN are brought into phase with each other after being delayed by one cycle of the clock pulse CLK. However, the number of inverter circuit arrays is an even number, and they are in phase with the delay signal DLN and the clock pulse.

At this time, each inverter circuit IVI to IVN can obtain a delay time obtained by dividing one period of the clock pulse CLK into N equal parts.

For example, if there is data that is input in synchronization with the clock pulse CLK, the internal clock pulse to capture the data is an appropriate integral multiple of the period T of the clock pulse divided into N equal parts. A timing pulse can be obtained. Note that when forming the delayed signal DLN input to the phase comparator circuit by using an odd number of inverter circuits, the clock pulse CL
A delay time unit obtained by dividing K half periods into N equal parts can be obtained from each inverter circuit.

Although not particularly limited, a masking function is added to the phase comparator circuit. In this embodiment, a mask signal MSK is formed from a clock pulse with a certain period of time before and after the clock pulse, with its rising edge being the midpoint.
The operation of the phase comparison circuit is enabled when K is at a high level. That is, when the mask signal MSK is at a low level, the gate circuit G1 shown in FIG. 3 is closed to prohibit transmission of the mismatch output formed by the exclusive OR circuit. This makes it possible to eliminate the influence of noise and the like.

The effects obtained from the above examples are as follows. That is, (1) Using a plurality of inverter circuits connected in series, the periodic pulses supplied to the input of the first-stage inverter circuit are compared in phase with the output signal of the final-stage inverter circuit to generate a voltage signal. one of the periodic pulse signals by controlling the operating current of the inverter circuit.
The effect is that it is possible to obtain a highly accurate delay time equally divided by the number of cascaded inverter circuits without being affected by process variations on a period or half period basis.

(2) Since it can be constructed using MOSFETs, it is possible to obtain a delay circuit suitable for semiconductor integrated circuit devices.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist thereof. For example, the delay circuit may be one that includes a capacitor to increase the delay time, or a C circuit that omits the MOSFET for current control.
A circuit that forms a fixed delay time, such as a MOS inverter circuit, may be inserted. Furthermore, the means for changing the delay time of the inverter circuit using the control voltage may use a variable capacitance element as its load.

The clock pulse CLK is a basic pulse for forming a non-overramp, and may form a clock pulse whose non-overramp time is set with high precision from an arbitrary output terminal of the delay circuit. .

The present invention can be widely used as a delay circuit mounted on a semiconductor integrated circuit device.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a voltage signal is formed by using multiple inverter circuits connected in series and comparing the phase of periodic pulses supplied to the input of the first-stage inverter circuit with the output signal of the final-stage inverter circuit. By controlling the operating current of the inverter circuit, a high-precision signal can be generated based on one period or half period of the periodic pulse signal, which is not affected by process variations and is equally divided by the number of inverter circuits in the cascade configuration. You can get the delay time.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the delay circuit according to the present invention, Fig. 2 is a specific circuit diagram showing an embodiment of the inverter circuit, and Fig. 3 shows the phase comparison circuit and voltage A specific circuit diagram showing one embodiment of the control circuit. The fourth panel is a timing chart for explaining an example of its operation. ', ■1~IVN...Inverter circuit, Q1~Q5...
・MOSFET, EX・・Exclusive OR circuit, G1-G
3...AND gate circuit, C3I, C32... constant current source, C... capacitor.

Claims (1)

[Claims] 1. A phase comparator circuit that receives a plurality of inverter circuits connected in series and a periodic pulse supplied to the input of the first-stage inverter circuit and an output signal of the final-stage inverter circuit. , a voltage control circuit that receives the output signal of the phase comparison circuit and forms a voltage signal for controlling the delay time of the inverter circuit, and generates a delay signal from the output of any one of the plurality of inverter circuits. A delay circuit characterized by obtaining. 2. The above inverter circuit consists of a CMOS inverter circuit and one MOSFE that constitutes the CMOS inverter circuit.
MOSFET of the same conductivity type as T and installed in series
2. The delay circuit according to claim 1, wherein the voltage signal is supplied to the gates of the MOSFETs arranged in series. 3. The phase comparison circuit is provided with a mask function, and the comparison operation is enabled in synchronization with the change timing of the input periodic pulse. Or the delay circuit according to item 2.