TWI883661B - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor structure includes a wafer, which includes a scribe lane region; first alignment marks, which are disposed in the scribe lane region of the wafer; a patterned dielectric layer, which is disposed on the wafer, wherein the patterned dielectric layer includes a first recess directly above the first alignment marks; a metal signal barrier, which is disposed in the first recess and covers the first alignment marks; and second alignment marks, which are disposed on the metal signal barrier. The second alignment marks at least partially overlap the first alignment marks.

Description

Semiconductor structure and method for manufacturing the same

The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a semiconductor structure including a metal signal barrier layer and a manufacturing method thereof.

In the semiconductor manufacturing process, many alignment marks are set in the cutting area to help the process go smoothly. When alignment is performed using alignment marks, light will illuminate the alignment marks to generate reflected light, and the alignment signal can be obtained by detecting the reflected light.

However, the alignment marks may occupy most of the space in the cutting area, so that if other marks need to be set in the subsequent process, in order to avoid interference from the reflected light of the alignment marks, they must avoid overlapping with the alignment marks, and the area that can be selected is limited. Therefore, how to increase the available space in the cutting area and avoid mutual interference between alignment marks requires further consideration and improvement.

The present invention provides a semiconductor structure and a manufacturing method thereof, which can avoid the alignment mark set on the wafer from generating reflected light, so as to increase the space for setting other marks in the dicing area in the subsequent process.

A semiconductor structure of the present invention comprises: a wafer, a first alignment mark, a patterned dielectric layer, a metal signal blocking layer and a second alignment mark. The wafer comprises a cutting track area. The first alignment mark is arranged in the cutting track area of the wafer. The patterned dielectric layer is arranged on the wafer, wherein the patterned dielectric layer comprises a first recessed portion directly above the first alignment mark. The metal signal blocking layer is arranged in the first recessed portion and covers the first alignment mark. And the second alignment mark is arranged on the metal signal blocking layer, and the second alignment mark at least partially overlaps with the first alignment mark.

In one embodiment of the present invention, the wafer further includes a chip region surrounded by the scribe line region, and the semiconductor structure further includes a top circuit disposed in the chip region.

In one embodiment of the present invention, the patterned dielectric layer further includes a second recessed portion, wherein the second recessed portion exposes the top wiring.

In an embodiment of the present invention, the width of the first recessed portion is greater than the width of the second recessed portion.

In an embodiment of the present invention, the semiconductor structure further includes a via window disposed in the second recessed portion and connected to the top circuit, and the via window is coplanar with the metal signal blocking layer.

In an embodiment of the present invention, the thickness of the metal signal blocking layer is less than or equal to the thickness of the via window.

In one embodiment of the present invention, the thickness of the metal signal blocking layer is greater than 20 nm.

In one embodiment of the present invention, the second alignment mark completely overlaps with the first alignment mark.

The present invention further provides a method for manufacturing a semiconductor structure, comprising: providing a wafer, the wafer including a dicing area and having a first alignment mark in the dicing area; forming a dielectric layer on the wafer to cover the first alignment mark; patterning the dielectric layer to form a first recessed portion directly above the first alignment mark; forming a metal signal blocking layer in the first recessed portion; and forming a second alignment mark on the metal signal blocking layer, the second alignment mark at least partially overlapping with the first alignment mark.

In another embodiment of the present invention, the wafer further includes a chip region, and a top circuit is provided in the chip region.

In another embodiment of the present invention, the step of patterning the dielectric layer further includes: simultaneously forming a second recessed portion to expose the top wiring.

In another embodiment of the present invention, the step of forming the metal signal blocking layer in the first recessed portion further includes: simultaneously forming a via window in the second recessed portion and connecting it to the top circuit.

In another embodiment of the present invention, the steps of forming the via window and the metal signal blocking layer include: depositing a metal material on the dielectric layer to simultaneously fill the second recess and the first recess; and performing a planarization process on the metal material until the top surface of the dielectric layer is exposed.

In another embodiment of the present invention, the thickness of the metal signal blocking layer is less than or equal to the thickness of the via window.

Based on the above, the semiconductor structure provided by the present invention can reuse the space of the cutting channel area, and does not need to occupy additional space in the chip area to set the alignment mark. The present invention can also increase the freedom of circuit design by flexibly adjusting the coverage range of the metal signal blocking layer. In addition, the metal signal blocking layer can be formed simultaneously with the via window in the chip area, so no additional process is required. Moreover, in the process of non-damascene structure, the metal signal blocking layer of the present invention can also be used as a protective layer to prevent the underlying structural layer from being damaged by the etching process.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

The present invention can be understood by referring to the following detailed description in conjunction with the attached drawings. It should be noted that, in order to make it easy for readers to understand and for the simplicity of the drawings, the multiple drawings in the present invention only depict a portion of the electronic device, and the specific components in the drawings are not drawn according to the actual scale. In addition, the number and size of each component in the figure are only for illustration and are not used to limit the scope of the present invention. Furthermore, the directional terms mentioned in the text, such as "on", "upper", etc., are only used to refer to the direction of the drawings and are not used to limit the present invention. In the following specification and claim items, "including" or similar terms should be interpreted as "including but not limited to..."

FIG1 is a cross-sectional view of a semiconductor structure 10 according to a first embodiment of the present invention.

Please refer to FIG1 , the semiconductor structure 10 includes: a wafer 100, a first alignment mark 102, a first patterned dielectric layer 104, a metal signal blocking layer 106, and a second alignment mark 114. The wafer 100 can be a silicon wafer or other suitable semiconductor wafer, but is not limited thereto. The first alignment mark 102 is, for example, a metal material or other high reflectivity material. For example, the metal material can be titanium, nickel, gold, aluminum, tungsten, platinum, or a combination thereof. The high reflectivity material can be a material having a reflectivity of greater than 90% for incident light or a combination thereof, but is not limited thereto. The second alignment mark 114 can be disposed on the second patterned dielectric layer 108, but is not limited thereto. The second patterned dielectric layer 108 has a recess or an opening, which serves as a second alignment mark 114. The materials of the first patterned dielectric layer 104 and the second patterned dielectric layer 108 may be, but are not limited to, silicon oxide, silicon oxynitride, silicon nitride, high-k dielectric metal oxide (e.g., einsteinium oxide, zirconium oxide, einsteinium zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, tantalum oxide, aluminum oxide, etc.), or a combination thereof. The materials of the first patterned dielectric layer 104 and the second patterned dielectric layer 108 may be the same or different. The material of the metal signal blocking layer 106 may be a conductive material, such as tungsten, titanium, tantalum, platinum, copper, gold, aluminum, titanium nitride, or a combination thereof, but is not limited thereto.

The wafer 100 includes a scribe line region SL. The first alignment mark 102 is disposed in the scribe line region SL of the wafer 100. The first patterned dielectric layer 104 is disposed on the wafer 100, wherein the first patterned dielectric layer 104 includes a first recess R1 located directly above the first alignment mark 102. The metal signal blocking layer 106 is disposed in the first recess R1 and covers the first alignment mark 102. The second alignment mark 114 is disposed on the metal signal blocking layer 106, and the second alignment mark 114 at least partially overlaps with the first alignment mark 102. In another embodiment, the second alignment mark 114 may completely overlap with the first alignment mark 102.

Please continue to refer to FIG. 1 , the wafer 100 further includes a chip region CR surrounded by the scribe line region SL, and the chip region CR has a semiconductor element (not shown), and has a top line 110 connected to the back-end line at its top. The material of the top line 110 can be a conductive material, such as titanium, tantalum, platinum, copper, gold, aluminum, titanium nitride, or a combination thereof, but is not limited thereto.

1 , the first patterned dielectric layer 104 further includes a second recessed portion R2, and the second recessed portion R2 exposes the top circuit 110. The width W1 of the first recessed portion R1 is greater than the width W2 of the second recessed portion R2.

Please continue to refer to FIG. 1 . The semiconductor structure 10 further includes a via window 112, which is disposed in the second recess R2 and connected to the top circuit 110. The via window 112 and the metal signal blocking layer 106 are coplanar and can be regarded as two parts of the same metal layer. The thickness D1 of the metal signal blocking layer 106 is less than or equal to the thickness D2 of the via window 112. The material of the via window 112 can be a conductive material, such as titanium, tantalum, platinum, copper, gold, aluminum, titanium nitride, or a combination thereof, but is not limited thereto.

The second patterned dielectric layer 108 may have a recess or an opening disposed on the via window 112 to serve as a via mark 116 .

Please continue to refer to FIG. 1 . The thickness D1 of the metal signal blocking layer 106 described above depends on the n/k value (n: refractive index, k: extinction coefficient) of the metal signal blocking layer 106 and the reflectivity of the reflected light generated by the first alignment mark 102 . In a simulation experiment in which the material of the metal signal blocking layer 106 is tungsten, when the thickness D1 of the metal signal blocking layer 106 is 30 nm, only less than 5% of the light can penetrate the metal signal blocking layer 106 and illuminate the first alignment mark 102. Under this condition, the reflectivity of the reflected light generated by the first alignment mark 102 is less than 0.3%; and when the thickness D1 of the metal signal blocking layer 106 is 20 nm, only less than 10% of the light can penetrate the metal signal blocking layer 106 and illuminate the first alignment mark 102. Under this condition, the reflectivity of the reflected light generated by the first alignment mark 102 is less than 1%. The above light is, for example, visible light or infrared light. Therefore, it can be known that if the material of the metal signal blocking layer 106 is tungsten, the thickness D1 of the metal signal blocking layer 106 is greater than 20 nm to effectively block light and prevent the first alignment mark 102 of the wafer 100 from generating a reflection signal.

In this embodiment, since the metal signal blocking layer 106 completely covers the first alignment mark 102, it is possible to prevent the first alignment mark 102 of the wafer 100 from generating reflected light. Therefore, the space of the cutting lane area SL can be reused multiple times in subsequent processes without occupying additional space in the chip area CR to set other marks, such as the second alignment mark 114.

FIG. 2 is a cross-sectional view of a semiconductor structure 20 according to a second embodiment of the present invention, wherein the same element symbols as those in the first embodiment are used to represent the same or similar parts and components, and the relevant contents of the related or similar parts and components can also refer to the contents of the first embodiment, which will not be repeated.

Specifically, the present embodiment is different from the first embodiment mainly in that the second alignment mark 220 of the present embodiment is a patterned metal layer, wherein the material of the second alignment mark 220 may be, but is not limited to, titanium, tantalum, platinum, copper, gold, aluminum, titanium nitride, other metal materials or a combination thereof. The second alignment mark 220 is disposed on the metal signal blocking layer 106, and the second alignment mark 220 at least partially overlaps with the first alignment mark 102. In another embodiment, the second alignment mark 220 may completely overlap with the first alignment mark 102.

In order to form the second alignment mark 220, a metal layer (not shown) may be first formed on the first patterned dielectric layer 104 and the metal signal blocking layer 106, and then a patterned hard mask layer 222 may be formed thereon, and the patterned hard mask layer 222 may be used as an etching mask to etch the metal layer, wherein the material of the patterned hard mask layer 222 may be, but is not limited to, silicon oxide, silicon nitride, tin nitride, or other hard mask materials. The metal layer may also be disposed on the via 112 as a part of the connection.

It should be noted that a person skilled in the art can still adjust the specific composition of the second alignment mark according to product requirements, and the present invention is not limited thereto.

FIG3C, FIG4, FIG5, FIG6, FIG7A, FIG8 and FIG9A are cross-sectional schematic diagrams of the manufacturing process of the semiconductor structure according to the third embodiment of the present invention. FIG3A is a plan view of the process of FIG3C in the third embodiment, wherein the same element symbols as those in the first embodiment are used to represent the same or similar parts and components, and the relevant contents of the related or similar parts and components can also refer to the contents of the first embodiment, and no further description is given.

Please refer to FIG. 3A to FIG. 3C , wherein FIG. 3B is a partial enlarged view of FIG. 3A . A method for manufacturing a semiconductor structure 30 according to a third embodiment of the present invention includes: providing a wafer 100, wherein the wafer 100 includes a scribe line region SL and a chip region CR, and wherein the scribe line region SL has a first alignment mark 102, and the chip region CR has a top circuit 110 (only shown in FIG. 3C ).

In FIG. 3B , a first alignment mark 102 is set in the dicing lane area SL to serve as an alignment mark for each process. However, the first alignment mark 102 may occupy most of the space in the dicing lane area SL, so that when other marks need to be set in the subsequent process, the remaining area is limited, and the marks cannot be automatically generated through CAD software, and must be set manually by CAD; it may even be necessary to divert space from the chip area CR. Therefore, in order to prevent the above loss, the following steps are performed.

Referring to FIG. 4 , a first dielectric layer 104′ is first formed on the wafer 100 to cover the first alignment mark 102. The material of the first dielectric layer 104′ may be, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, high-k dielectric metal oxide (e.g., einsteinium oxide, zirconium oxide, einsteinium zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, tantalum oxide, aluminum oxide, etc.), or a combination thereof.

Next, referring to FIG. 5 , the first dielectric layer 104′ in FIG. 4 is patterned to form a first patterned dielectric layer 104, and a first recess R1 is formed directly above the first alignment mark 102. The method of patterning the first dielectric layer 104′ may include a first photolithography process. Specifically, the first photolithography process may include, for example, forming a first mask layer (not shown) on the first dielectric layer 104′, then patterning the first mask layer, and then etching the first dielectric layer 104′ using the patterned first mask layer as an etching mask. After the first patterned dielectric layer 104 is formed, the first mask layer may be removed.

The step of patterning the first dielectric layer 104' can utilize the same photomask process to form the second recess R2 to expose the top circuit 110. Since the width W1 of the first recess R1 is much larger than the width W2 of the second recess R2, an etching loading effect will be generated during the same etching process, thereby etching through the second recess R2 but not the first recess R1. The width W1 is, for example, 60 μm to 80 μm, but not limited thereto. The width W2 is, for example, less than 100 nm, but not limited thereto. The depth (i.e., thickness D1) of the first recess R1 is less than or equal to the depth (i.e., thickness D2) of the second recess R2.

Then, referring to FIG. 6 , a metal material is deposited on the first patterned dielectric layer 104 to form a first metal layer 106' that fills both the second recess R2 and the first recess R1.

Next, please refer to FIG7A , the first metal layer 106′ of FIG6 is planarized to form a metal signal blocking layer 106 in the first recess R1. The thickness D1 of the metal signal blocking layer 106 depends on the n/k value of the metal signal blocking layer 106 and the reflectivity of the reflected light generated by the first alignment mark 102, wherein the thickness D1 is, for example, greater than 20 nm, but not limited thereto. In some embodiments, the material of the metal signal blocking layer 106 is tungsten, and the thickness D1 of the metal signal blocking layer 106 is, for example, greater than 20 nm; specifically, the step of forming the metal signal blocking layer 106 includes: performing a planarization process on the first metal layer 106' until the top surface of the first dielectric layer 104' is exposed, so as to simultaneously form the metal signal blocking layer 106 in the first recess R1 and form a via window 112 in the second recess R2. The via window 112 is connected to the top line 110.

According to the manufacturing process of Figures 5 to 7A, the metal signal blocking layer 106 of the dicing area SL can be completed together with the via 112 process of the chip area CR, so no additional lithography and etching processes are required, making this embodiment simple in process and cost-saving.

Then, please refer to Fig. 7B, which is a schematic plan view of Fig. 7A, and omits the structure in the chip region CR. As can be seen from Fig. 7A, the metal signal blocking layer 106 can completely cover the scribe line region SL, but the present invention is not limited thereto.

Next, referring to FIG8 , a second dielectric layer 108′ is formed on the first patterned dielectric layer 104 to cover the metal signal blocking layer 106 and the via window 112. The material of the second dielectric layer 108′ may be, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, high-k dielectric metal oxide (e.g., einsteinium oxide, zirconium oxide, einsteinium zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, tantalum oxide, aluminum oxide, etc.), or a combination thereof.

Next, referring to FIG. 9A , a second alignment mark 114 is formed on the metal signal blocking layer 106 , and the second alignment mark 114 at least partially overlaps with the first alignment mark 102 .

Specifically, the method of forming the second alignment mark 114 may include: patterning the second dielectric layer 108' in FIG. 8. The method of patterning the second dielectric layer 108' is, for example but not limited to, first forming a second mask layer (not shown) on the second dielectric layer 108', then patterning the second mask layer, and then etching the second dielectric layer 108' using the patterned second mask layer as an etching mask. After forming the second patterned dielectric layer 108, the second mask layer may be removed. The recess or opening in the second patterned dielectric layer 108 may be used as the second alignment mark 114. In addition, the second patterned dielectric layer 108 in the chip region CR has another recess or opening located on the via window 112, which serves as the via window mark 116. The subsequent process may also include other processes, which will not be explained here.

It should be noted that a person skilled in the art can adjust the number of metal signal blocking layers 106 disposed on the semiconductor structure 30 according to product requirements, such as one layer, two layers, or more than two layers, and the present invention is not limited thereto.

Then, please refer to FIG. 9B and FIG. 3B at the same time, and FIG. 9B omits the structure in the chip region CR. In this embodiment, since the metal signal blocking layer 106 of the semiconductor structure 30 can completely cover the scribe line region SL, and the metal signal blocking layer 106 can completely prevent the first alignment mark 102 of the wafer 100 from generating reflected light, the space of the scribe line region SL can be reused multiple times, and there is no need to occupy additional space in the chip region CR to set other marks (second alignment mark 114). The semiconductor structure and the manufacturing method thereof provided by the present invention can also increase the degree of freedom of circuit design by flexibly adjusting the coverage range of the metal signal blocking layer 106.

FIG. 10 and FIG. 11 are schematic cross-sectional views of the manufacturing process of the semiconductor structure 40 according to the fourth embodiment of the present invention, wherein the same element symbols as those in the first embodiment are used to represent the same or similar parts and components, and the relevant contents of the manufacturing process can also refer to the contents of the third embodiment and will not be repeated here.

Please refer to FIG. 10 and FIG. 8 simultaneously. The manufacturing process of the semiconductor structure 40 of this embodiment is similar to the manufacturing process of the semiconductor structure 30 in FIG. 8 , but the main difference between the two is that: in this embodiment, a second metal layer 220' is further formed on the first patterned dielectric layer 104 to cover the metal signal blocking layer 106, wherein the material of the second metal layer 220' can be, but is not limited to, titanium, tantalum, platinum, copper, gold, aluminum, titanium nitride, other metal materials or a combination of the foregoing.

Then, referring to FIG11, a patterned hard mask layer 222 is first formed on the second metal layer 220' of FIG10, and then the patterned hard mask layer 222 is used as an etching mask to perform etching to form a second alignment mark 220. The second alignment mark 220 at least partially overlaps with the first alignment mark 102.

The method for patterning the second metal layer 220' may include a self-aligning double patterning (SADP) process. Since the SADP process is a well-known technology in the art, it will not be further described here. Subsequently, other processes may also be included, which will not be described here.

FIG. 12 and FIG. 13 are schematic cross-sectional views of the manufacturing process of the semiconductor structure 50 according to the fifth embodiment of the present invention, wherein the same element symbols as those in the first embodiment are used to represent the same or similar parts and components, and the relevant contents of the manufacturing process can also refer to the contents of the fourth embodiment and will not be repeated here.

Please refer to FIG. 12 and FIG. 10 simultaneously. The manufacturing process of the semiconductor structure 50 of this embodiment is similar to the manufacturing process of the semiconductor structure 40 in FIG. 10, but the main difference between the two is that the cutting line area SL also includes a non-mark area NA. The non-mark area NA refers to an area where the second alignment mark is not configured, but the non-mark area NA may have a first alignment mark 102. In this embodiment, the metal signal blocking layer 106 also covers the first alignment mark 102 of the non-mark area NA. Compared with the non-mark area NA not covered by the metal signal blocking layer 106, the non-mark area NA not covered by the metal signal blocking layer 106 has only the first patterned dielectric layer 104 above the first alignment mark 102.

Then, please refer to FIG. 13 , in the process of etching the patterned hard mask layer 222 by the SADP process, since the SADP process requires several etching processes, the dicing line area SL without the metal signal blocking layer 106 will cause structural layer damage (or depression) UD. In particular, in the non-mark area NM without the metal signal blocking layer 106, the first patterned dielectric layer 104 may be etched through, and even the first alignment mark 102 may be exposed and damaged. Therefore, it can be seen that the metal signal blocking layer 106 can also be used as a protective layer to prevent structural layer damage UD caused by the etching process.

In this embodiment, the scribe line region SL may include a damascene structure region or a non-damascene structure region. The metal signal blocking layer 106 may be applied to the damascene structure region or the non-damascene structure region. When the metal signal blocking layer 106 is disposed in the non-damascene structure region, it may also serve as a protective layer to prevent the structural layer UD from being damaged during the etching process.

In summary, the semiconductor structure and the manufacturing method thereof provided by the present invention can avoid the first alignment mark of the wafer from generating reflected light, so that the space of the cutting path area can be reused multiple times, and there is no need to occupy the space of the chip area to set other marks, that is, the second alignment mark can partially overlap the first alignment mark, or completely overlap the first alignment mark. The semiconductor structure and the manufacturing method thereof provided by the present invention can also increase the freedom of circuit design by flexibly adjusting the coverage range of the metal signal blocking layer. The metal signal blocking layer can be formed simultaneously with the via window in the chip area, without the need for additional steps, and has the effect of simple process and cost saving. The metal signal blocking layer can be applied to the inlay structure area or the non-inlay structure area. When the metal signal blocking layer is disposed in the non-inlay structure area, it can also be used as a protective layer to prevent the structural layer from being damaged during the etching process.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

10, 20, 30, 40, 50: semiconductor structure 100: wafer 102: first alignment mark 104: first patterned dielectric layer 104’: first dielectric layer 106: metal signal blocking layer 106’: first metal layer 108: second patterned dielectric layer 108’: second dielectric layer 110: top line 112: via 114: second alignment mark 116: via mark 220: second alignment mark 220’: second metal layer 222: patterned hard mask layer CR: chip area D1, D2: thickness NA: non-marking area NM: Non-marked area without metal signal blocking layer R1, R2: Depression SL: Cutting track area UD: Structural layer damage W1, W2: Width

FIG. 1 is a cross-sectional view of a semiconductor structure according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view of a semiconductor structure according to the second embodiment of the present invention. FIG. 3C, FIG. 4, FIG. 5, FIG. 6, FIG. 7A, FIG. 8 and FIG. 9A are cross-sectional schematic views of the manufacturing process of the semiconductor structure according to the third embodiment of the present invention. FIG. 3A is a plan view of the process of FIG. 3C in the third embodiment. FIG. 3B is a partially enlarged schematic view of FIG. 3A. FIG. 7B is a plan view of the process of FIG. 7A in the third embodiment. FIG. 9B is a plan view of the process of FIG. 9A in the third embodiment. FIG. 10 and FIG. 11 are cross-sectional schematic views of the manufacturing process of the semiconductor structure according to the fourth embodiment of the present invention. Figures 12 and 13 are schematic cross-sectional views of the manufacturing process of the semiconductor structure according to the fifth embodiment of the present invention.

10:Semiconductor structure

100: Wafer

102: First alignment mark

104: First patterned dielectric layer

106: Metal signal blocking layer

108: Second patterned dielectric layer

110: Top line

112:Interface window

114: Second alignment mark

116:Interface window mark

CR: Chip area

D1, D2: thickness

R1, R2: Depression

SL: Cutting area

W1, W2: Width

Claims (14)

A semiconductor structure, comprising: a wafer, the wafer comprising a sawing zone; a first alignment mark, disposed in the sawing zone of the wafer; a first patterned dielectric layer, disposed on the wafer, wherein the first patterned dielectric layer comprises a first recessed portion directly above the first alignment mark; a metal signal blocking layer, disposed in the first recessed portion and covering the first alignment mark, wherein the material of the metal signal blocking layer is tungsten; and The second alignment mark is disposed on the metal signal blocking layer, wherein the second alignment mark is in direct contact with the metal signal blocking layer, and the second alignment mark at least partially overlaps with the first alignment mark, and the material of the second alignment mark is titanium, tantalum, platinum, copper, gold, aluminum, titanium nitride, or a combination thereof. A semiconductor structure as described in claim 1, wherein the wafer further includes a chip area surrounded by the cutting line area, and the semiconductor structure further includes a top circuit disposed in the chip area. A semiconductor structure as described in claim 2, wherein the first patterned dielectric layer further includes a second recessed portion, wherein the second recessed portion exposes the top circuit. A semiconductor structure as described in claim 3, wherein the width of the first recess is greater than the width of the second recess. The semiconductor structure as described in claim 3 further includes a via window disposed in the second recess and connected to the top circuit, and the via window is coplanar with the metal signal blocking layer. A semiconductor structure as described in claim 5, wherein the thickness of the metal signal blocking layer is less than or equal to the thickness of the via window. A semiconductor structure as described in claim 1, wherein the thickness of the metal signal blocking layer is greater than 20 nm. A semiconductor structure as described in claim 1, wherein the second alignment mark completely overlaps with the first alignment mark. A method for manufacturing a semiconductor structure, comprising: Providing a wafer, the wafer comprising a dicing area and having a first alignment mark in the dicing area; Forming a first dielectric layer on the wafer to cover the first alignment mark; Patterning the first dielectric layer to form a first recessed portion directly above the first alignment mark; Forming a metal signal blocking layer in the first recessed portion, wherein the material of the metal signal blocking layer is tungsten; and A second alignment mark is formed on the patterned first dielectric layer using a self-aligned double patterning (SADP) process, wherein the second alignment mark is in direct contact with the metal signal blocking layer, and the second alignment mark at least partially overlaps with the first alignment mark, wherein the material of the second alignment mark is titanium, tantalum, platinum, copper, gold, aluminum, titanium nitride, or a combination thereof. A method for manufacturing a semiconductor structure as described in claim 9, wherein the wafer further includes a chip area and has a top circuit in the chip area. The method for manufacturing a semiconductor structure as described in claim 10, wherein the step of patterning the first dielectric layer further includes: simultaneously forming a second recess to expose the top circuit. The method for manufacturing a semiconductor structure as described in claim 11, wherein the step of forming the metal signal blocking layer in the first recess further includes: simultaneously forming a via window in the second recess and connecting it to the top circuit. The method for manufacturing a semiconductor structure as described in claim 12, wherein the steps of forming the via window and the metal signal blocking layer include: Depositing a metal material on the first dielectric layer to simultaneously fill the second recess and the first recess; and Performing a planarization process on the metal material until the top surface of the first dielectric layer is exposed. A method for manufacturing a semiconductor structure as described in claim 13, wherein the thickness of the metal signal blocking layer is less than or equal to the thickness of the via window.

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