TWI882809B - Fan-out semiconductor packaging integrating micro-coil and packaging method thereof - Google Patents

Abstract

The present invention relates to a fan-out semiconductor packaging structure integrating micro-coil and packaging method thereof. A chip and a micro-coil unit are formed in a redistribution layer. The micro-coil unit at least locates between two opposite outsides of the chip and is electrically connected to the redistribution layer and chip. An encapsulant encapsulates the chip and the micro-coil unit therein. Therefore, the micro-coil does not only locate one of the outsides of the chip to decrease a warpage of the fan-out semiconductor package can be decreased.

Description

Fan-out semiconductor package structure integrating micro-coils and packaging method thereof

The present invention relates to a fan-out semiconductor package structure and a packaging method thereof, and in particular to a fan-out semiconductor package structure integrating micro-coils and a packaging method thereof.

Currently, for special function applications, semiconductor package structures are required to further integrate passive components in the packaging process. However, without careful planning, passive components are simply added to the packaging process, for example, a single micro coil is offset to one side of the chip. Although this meets the needs of special function applications, the coil occupies a larger size of the package body, making the warp problem of the thin fan-out semiconductor package structure more prominent.

Therefore, the warp problem of the current fan-out semiconductor package structure integrating passive components such as coils needs to be further improved.

In view of the warp problem of the fan-out semiconductor package structure integrating passive components such as coils, the main purpose of the present invention is to provide a fan-out semiconductor package structure integrating micro-coils and a packaging method thereof to reduce product warp.

The main technical means used to achieve the above purpose is to make the fan-out semiconductor package structure with integrated micro-coils include: A first redistribution wiring layer, which has a first internal connection surface and a first external connection surface, and the first external connection surface is electrically connected to multiple external connectors; A chip is arranged on the first internal connection surface of the first redistribution wiring layer and electrically connected to it; A micro-coil unit is arranged on the first internal connection surface of the first redistribution wiring layer, and is at least spaced at at least two opposite outer sides of the chip, and is electrically connected to the first redistribution wiring layer and the chip; and A first encapsulation layer is arranged on the first internal connection surface of the first redistribution wiring layer and covers the chip and the micro-coil unit.

From the above description, it can be seen that the micro-coil units of the fan-out semiconductor package structure of the present invention are at least spaced apart at at least two opposite outer sides of the chip and are not offset to one outer side of the chip, so as to reduce the warp of the fan-out semiconductor package structure.

The main technical means used to achieve the above-mentioned purpose is to make the fan-out semiconductor packaging method of the integrated micro-coil include: (a) preparing a carrier; (b) forming a lower redistribution wiring layer on the carrier; (c) forming a plurality of micro-coil units on the lower redistribution wiring layer; (d) adhering a plurality of chips to the lower redistribution wiring layer with their backs, and each of the chips is located in a plurality of micro-coil units; (e) forming a sealing layer on the lower redistribution wiring layer to cover the micro-coil units and the chips on the lower redistribution wiring layer; (f) grinding the sealing layer to provide a coplanar surface; (g) forming an upper redistribution wiring layer on the coplanar surface; and (h) A plurality of independent fan-out semiconductor package structures are cut out according to the cutting paths; wherein the micro-coil units of each fan-out semiconductor package structure are at least spaced apart and located at least two opposite outer sides of the chip.

As can be seen from the above description, the fan-out semiconductor packaging method of the present invention is to place multiple chips in the corresponding micro-coil units respectively. After cutting a single fan-out semiconductor package structure, the micro-coil units are at least spaced apart at at least two opposite outer sides of the chip; in this way, the micro-coil units will not be biased to one outer side of the chip, so as to reduce the warp of the fan-out semiconductor package structure.

The present invention is directed to improving a fan-out semiconductor package structure integrating micro-coils and a packaging method thereof. The present invention is described in detail below with reference to several embodiments and drawings.

First, please refer to FIG. 1, which is a partial structural three-dimensional schematic diagram of the first embodiment of the fan-out semiconductor package structure 1a of the present invention, and FIG. 3D (which is exactly the top and bottom inverted with FIG. 1) shows that the fan-out semiconductor package structure 1a includes a first redistribution layer 10, a chip 20, a micro-coil unit 30 and a first encapsulation layer 40; in addition, the fan-out semiconductor package structure 1a may further include a second redistribution layer 50. The micro-coil unit 30 shown in FIG. 3D is only drawn with two circles for illustration.

The first redistribution layer 10 has a first internal connection surface 11 and a first external connection surface 12. The first external connection surface 12 is electrically connected to a plurality of external connectors 13. In this embodiment, the external connectors 13 are solder balls or bumps, but are not limited thereto.

The chip 20 is disposed on the first internal connection surface 11 of the first redistribution layer 10 and is electrically connected thereto. In this embodiment, the chip 20 has an active surface 21 and a back surface 22 opposite to the active surface, and the active surface 21 faces the first internal connection surface 11 and is welded to the first internal connection surface 11 by a plurality of bumps 211.

The micro-coil unit 30 is disposed on the first inner connection surface 11 of the first redistribution wiring layer 10, and is at least spaced apart at at least two opposite outer sides 201 of the chip 20, and is electrically connected to the first redistribution wiring layer 10 and the chip 20. In this embodiment, the micro-coil unit 30 includes a first micro-coil 31, and the first micro-coil 31 surrounds the chip 20 therein. As shown in FIG1 , the first micro-coil 31 is a single spiral metal plate, which can be a square or circular spiral, and its innermost circle part surrounds the outer periphery of the chip 20, that is, spaced apart at multiple outer sides 201 of the chip 20. As shown in FIG3D , the micro-coil unit 30 further includes a ferromagnetic material layer 32 to cover the multiple plate bodies 311 of the single spiral metal plate.

The first encapsulation layer 40 is disposed on the first inner connection surface of the first redistribution layer and covers the chip, the first micro-coil 31 and the ferromagnetic material layer 32.

The second redistribution layer 50 includes a second inner connection surface 51 and a second outer connection surface 52. The second inner connection surface 51 is electrically connected to the first micro-coil 31. In this embodiment, the back surface 22 of the chip 20 is adhered to the second inner connection surface 51 of the second redistribution layer 50 by an adhesive layer 23.

As shown in FIG. 2 and FIG. 3D (which is reversed from FIG. 2 ), a second embodiment of the fan-out semiconductor package structure 1b of the present invention is shown. Most of its structures are the same as those of the first embodiment, but a first micro-coil 31 of the present embodiment includes a plurality of ring plates 33 and a ferromagnetic material layer 32. The ring plates 33 are concentrically arranged, and the innermost ring plate 33 surrounds the periphery of the chip 20. Each of the ring plates 33 has a longitudinal opening 331, so that each of the ring plates 33 has two free ends 332 when viewed from above or from above; the free ends 332 of the ring plates 33 are electrically connected to the first inner connection surface 11 of the first redistribution layer 10 or the second inner connection surface 51 of the second redistribution layer 50 to form a micro-coil. The two different dashed lines in FIG2 are equivalent schematic diagrams of the circuits of the first and/or second inner connection surfaces, which are equivalent to the input end (IN) and output end (OUT) of the micro coil, and are not physical circuit layout diagrams. The ferromagnetic material layer 32 shown in FIG3D is disposed on the first inner connection surface 11 of the first redistribution layer 10 to cover the plurality of ring plates 33 and is covered by the first sealing layer 40.

In addition, the longitudinal openings 331 of the above-mentioned rings 33 can be further staggered and not aligned in the same direction. As shown in Figure 4B, a metal layer 34 can be further provided at each joint between the ferromagnetic material layer 32 and the first sealing layer 40, and at least the metal layer 34 closest to the periphery of the chip 20 is electrically connected to the grounding line 53 of the first redistribution layer 10 or the second redistribution layer 50, so as to provide signal shielding for the chip 20 through electrical grounding, thereby preventing the chip 20 from being disturbed by the micro-wire unit 30.

Figure 5B is another structure of the micro-coil unit 30, which includes the first micro-coil 31 as shown in Figure 1 or Figure 2 and multiple ferromagnetic material layers 32. The ferromagnetic material layers 32 are arranged on the first internal connection surface 11 of the first redistribution layer to respectively cover the multiple plate bodies 311 of the first micro-coil 31 as shown in Figure 1, or respectively cover the multiple ring plates 33 as shown in Figure 2, and the ferromagnetic material layers 32 are all covered by the first sealing layer 40. Similarly, each joint between the ferromagnetic material layer 32 and the first encapsulation layer 40 may be further provided with a metal layer 34, and at least one metal layer 34 is electrically connected to the grounding line 53 of the first redistribution layer 10 or the second redistribution layer 50, so as to provide signal shielding for the chip 20 through electrical grounding, thereby preventing the chip 20 from being disturbed by the micro-wire unit 30.

As can be seen from the first and second embodiments of the fan-out semiconductor package structure, the micro-coil unit 30 adopts a single first micro-coil 31 to surround the chip 20 therein, and is spaced at multiple outer sides 201 of the chip 20, so that it is no longer biased at one of the outer sides 201 of the chip 20, effectively reducing the warp of the fan-out semiconductor package structures 1a, 1b.

Please refer to FIG. 6A , which is a partial top plan view of the third embodiment of the fan-out semiconductor package structure 1c of the present invention, which is substantially the same as the second embodiment shown in FIG. 2 , except that the micro-coil unit 30 includes at least two micro-coils 31′, and the two micro-coils 31′ are respectively spaced apart and located at the two opposite outer sides 201 of the chip 20; in this embodiment, the two micro-coils 31′ are electrically connected in parallel with the chip 20 through the first and second redistribution layers (corresponding to the two different equivalent lines of the dotted lines in the figure); as shown in FIG. 6B , the two micro-coils 31′ are electrically connected in series with the chip 20 through the first and second redistribution layers (corresponding to the two different equivalent lines of the dotted lines in the figure). The fan-out semiconductor package structure 1d integrates a micro-coil unit with a relatively large inductance. Similarly, the two micro-coils 31' can also adopt the micro-coils 31 shown in FIG. 1, that is, two micro-coils 31 as shown in FIG. 1 are prepared and electrically connected in series or in parallel with the chip 20 through the first and second redistribution wiring layers.

Please refer to FIG. 7 , which is another fan-out semiconductor package structure 1e with large inductance. Most of its structures are the same as those of the embodiments of FIG. 2 in conjunction with FIG. 3D , FIG. 4B or FIG. 5B , except that a second micro-coil 35 is further provided on the second external connection surface 52 of the second redistribution layer 50 . The second micro-coil 35 is provided on the second external connection surface 52 of the second redistribution layer 50 and is electrically connected thereto, and is also covered by a ferromagnetic material layer 36 , and then another second encapsulation layer 41 covers the second micro-coil layer 35 and the ferromagnetic material layer 36 therein. Similarly, the second micro-coil 35 can also be electrically connected in series or in parallel with the chip 20 through the second redistribution layer 50 in coordination with the first and second redistribution layers 10, 50. The second micro-coil 35 can be a structure similar to the first micro-coil 31 shown in FIG. 1 and FIG.

The packaging method of the fan-out semiconductor package structure of FIG. 3D , FIG. 4B and FIG. 5B is further described below.

Please refer to Figure 3A. First, a carrier board 60 is prepared, and a lower redistribution wiring layer 70 is formed on the carrier board 60. Then, a plate body 311 of multiple single spiral metal plates as shown in Figure 1 or multiple groups of ring plates 33 as shown in Figure 2 are formed on the lower redistribution wiring layer 70. Since a portion of each single spiral metal plate or a portion of each ring plate 33 is directly formed on the corresponding pad 701 of the lower redistribution wiring layer 70, the single spiral metal plate or the ring plates 33 are electrically connected to the lower redistribution wiring layer 70.

As shown in FIG3B , a plurality of ferromagnetic material layers 32 are formed on the lower redistribution layer 70 to respectively cover a plurality of single spiral metal plates as shown in FIG1 or a plurality of groups of ring plates 33 as shown in FIG2 to form the micro-coil units 31, 31' as shown in FIGS. 1 , 2 , 6A and 6B .

As shown in FIG3C , a plurality of chips 20 are disposed on the lower redistribution layer 70, and each chip 20 is located in the middle of each single spiral metal plate as shown in FIG1 , or in the middle of each group of ring plates 33 as shown in FIG2 ; in this embodiment, the chips 20 are adhered to the lower redistribution layer 70 with their back sides 22 through an adhesive layer 23, so that the active surface 21 of the chip 20 faces upward. Next, a sealing layer 71 is formed on the lower redistribution wiring layer 70 to cover all components on the lower redistribution wiring layer 70. The sealing layer 71 can be further ground to expose the chip pads 211 on the active surface 21 of the chips 20, the plates 311 of the single spiral metal plate or the ring plates 33, and the ferromagnetic material layers 32 and form a coplanar surface. If the fan-out semiconductor package structure 1c, 1d shown in FIG. 6A and FIG. 6B is to be realized, the chip is located in the middle of the adjacent single spiral metal plate, or in the middle of two adjacent sets of the ring plates 33.

As shown in FIG3D , an upper redistribution wiring layer 72 is formed on the coplanar surface of FIG3C , and a plurality of pads 721 of the upper redistribution wiring layer 72 are connected to the chip pads 211 on the active surface 21 of the chips 20, the parts of the plate bodies 311 of the single spiral metal plate, or the parts of the ring plates 33, so the active surface 21 of the chips 20, the plates 311 of the single spiral metal plate, or the ring plates 33 are electrically connected through the upper redistribution wiring layer 72. A plurality of external connectors 13, such as solder balls or bumps, are further formed on the upper redistribution wiring layer 72, but not limited thereto. Finally, a plurality of independent fan-out semiconductor package structures 1a, 1b of the present invention are cut out by the cutting lane L shown in FIG3D .

As shown in FIG. 4A, in the step corresponding to FIG. 3B, after a plurality of ferromagnetic material layers 32 are formed on the lower redistribution wiring layer 70, a metal layer 80 is formed on the outer side of each ferromagnetic material layer 32, which is generally in the shape of a letter "U". Subsequently, in conjunction with FIG. 3C and FIG. 4B, a plurality of chips 20 are placed on the lower redistribution wiring layer 70, and a sealing layer 71 is formed. In the grinding step, The metal layer portion 81 on the top surface of each ferromagnetic material layer 32 is removed together, so that the metal layer 34 is formed at the joint between each ferromagnetic material layer 32 and the encapsulation layer 71, and is coplanar with the chip pads 211 on the active surface 21 of the chips 20, each plate body 311 of the single spiral metal plate or each ring plate 33, so as to form the upper redistribution layer 72 as shown in Figure 4B. Finally, as shown in Figure 4B, the cutting road L is cut out to cut out multiple independent fan-out semiconductor package structures 1a and 1b of the present invention.

As shown in FIG. 5A, it is substantially the same as FIG. 4A, except that the adjacent plate 311 in each of the single spiral metal plates shown in FIG. 1 or the adjacent ring plate 33 shown in FIG. 2 corresponding to each of the ferromagnetic material layers 32 is further removed, so that each of the plate 311 in each of the single spiral metal plates shown in FIG. 1 or each of the ring plates 33 shown in FIG. 2 is covered with an independent ferromagnetic material layer 32, and then a metal layer 80 is formed on the outer side of each of the ferromagnetic material layers 32, which is generally in the shape of a letter U; thereafter, in conjunction with FIG. 3C and FIG. 5 As shown in FIG. 5B , after placing multiple chips 20 on the lower redistribution wiring layer 70 and forming a sealing layer 71, the metal layer portion on the top surface of each ferromagnetic material layer 32 can be removed together in the grinding step, so that the metal layer 34 is formed at the joint between each ferromagnetic material layer 32 and the sealing layer 71, and the chip pads 211 on the active surface 21 of the chips 20, each plate body 311 of the single spiral metal plate or each ring plate 33 are in a coplanar state, so as to form the upper redistribution wiring layer 72 as shown in FIG. 5B . Finally, as shown in FIG. 5B , the cutting road is cut out to cut out multiple independent fan-out semiconductor package structures 1a and 1b of the present invention.

In summary, the fan-out semiconductor package structure integrating micro-coils of the present invention mainly places its micro-coil units at least at intervals on at least two relatively outer sides of the chip, and not offset to one outer side of the chip, so as to reduce the warp of the fan-out semiconductor package structure.

The above is only an embodiment of the present invention and does not constitute any form of limitation on the present invention. Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes or modifications to the technical contents disclosed above into equivalent embodiments within the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

1a, 1b, 1c, 1d, 1e: Fan-out semiconductor package structure 10: First redistribution layer                                        11: First internal connection surface 12: First external connection surface                                       13: External connector 20: Chip                                                   201: External side 21: Active surface                                                   211: Chip pad 22: Back side                                                       23: Adhesive layer 30: Microcoil unit                                           31, 31’: First microcoil 311: Board                                                     32: Ferromagnetic material layer 33: Ring plate                                                       331: Longitudinal opening 332: Free end                                             34: Metal layer 35: Second micro coil                                           36: Ferromagnetic material layer 40: First sealing layer                                            41: Second sealing layer 50: Second redistribution layer                                        51: Second inner connection surface 52: Second outer connection surface                                        53: Ground line 60: Carrier board                                                   70: Lower redistribution layer 701: Pads                                                         71: Sealing layer 72: Upper redistribution layer                                               721: Pads 80: Metal layer                                                   81: Metal layer part

Figure 1: A partial three-dimensional diagram of a first embodiment of a fan-out semiconductor package structure of the present invention; Figure 2: A partial top view of a second embodiment of a fan-out semiconductor package structure of the present invention; Figures 3A to D: Schematic diagrams of structural cross-sections corresponding to different steps in a fan-out semiconductor package method of the present invention; Figures 4A and B: Schematic diagrams of structural cross-sections corresponding to different steps in another fan-out semiconductor package method of the present invention; Figures 5A and B: Schematic diagrams of structural cross-sections corresponding to different steps in another fan-out semiconductor package method of the present invention; Figure 6A: A partial top view of a third embodiment of a fan-out semiconductor package structure of the present invention; Figure 6B: A partial top view of a fourth embodiment of a fan-out semiconductor package structure of the present invention; Figure 7: A cross-sectional schematic diagram of a fifth embodiment of the fan-out semiconductor package structure of the present invention.

1a: Fan-out semiconductor package structure

10: First redistribution layer

11: First internal connection surface

20: Chip

201:Outer side

30: Micro coil unit

31: The first micro coil

Claims (24)

A fan-out semiconductor package structure with integrated micro-coils comprises: a first redistribution wiring layer having a first internal connection surface and a first external connection surface, wherein the first external connection surface is electrically connected to a plurality of external connectors; a chip disposed on the first internal connection surface of the first redistribution wiring layer and electrically connected thereto; a micro-coil unit disposed on the first internal connection surface of the first redistribution wiring layer and at least spaced apart on at least two opposite outer sides of the chip and electrically connected to the first redistribution wiring layer and the chip; and a first encapsulant layer disposed on the first internal connection surface of the first redistribution wiring layer and covering the chip and the micro-coil unit. A fan-out semiconductor package structure as described in claim 1, wherein the micro-coil unit includes a first micro-coil which surrounds the chip therein. The fan-out semiconductor package structure as described in claim 2 further includes a second redistribution layer, which is opposite to the first redistribution layer and is arranged on the chip, the first microcoil and the first encapsulation layer to be electrically connected to the first microcoil. A fan-out semiconductor package structure as described in claim 3, wherein: The second redistribution layer includes a second internal connection surface and a second external connection surface, and the second internal connection surface is electrically connected to the first micro-coil; and The chip is adhered to the second internal connection surface of the second redistribution layer by an adhesive layer. The fan-out semiconductor package structure as described in claim 4 further comprises: A second micro-coil disposed on the second external connection surface of the second redistribution layer and electrically connected thereto; and A second encapsulation layer disposed on the second external connection surface of the second redistribution layer and covering the second micro-coil layer. A fan-out semiconductor package structure as described in any one of claims 3 to 5, wherein the first microcoil comprises: a single spiral metal plate, the innermost part of which is wound around the periphery of the chip; and a ferromagnetic material layer, which covers the single spiral metal plate; wherein the first encapsulation layer is the ferromagnetic material layer covering the first microcoil. A fan-out semiconductor package structure as described in any one of claims 3 to 5, wherein the first microcoil comprises: A plurality of ring plates, which are concentrically arranged, and the innermost ring plate is encircled around the periphery of the chip; wherein each of the ring plates has a longitudinal opening, so that each of the ring plates has two free ends, and the free ends are electrically connected to the first internal connection surface of the first redistribution layer or the second redistribution layer to form a microcoil; and A ferromagnetic material layer, which is arranged on the first internal connection surface of the first redistribution layer and covers the plurality of ring plates; wherein the first encapsulation layer is the ferromagnetic material layer covering the first microcoil. A fan-out semiconductor package structure as described in any one of claims 3 to 5, wherein the first microcoil comprises: A plurality of ring plates, which are arranged concentrically, and the innermost ring plate is encircled around the periphery of the chip; wherein each of the ring plates has a longitudinal opening, so that each of the ring plates has two free ends, and the free ends are electrically connected to the first internal connection surface of the first redistribution layer or the second redistribution layer to form a microcoil; and A plurality of ferromagnetic material layers, which are arranged on the first internal connection surface of the first redistribution layer and respectively cover the plurality of ring plates; wherein the first encapsulation layer covers the ferromagnetic material layers of the first microcoil. A fan-out semiconductor package structure as described in claim 7, wherein: the longitudinal openings of the ring plates are staggered; and a metal layer is further provided at each joint between the ferromagnetic material layer and the first encapsulation layer; wherein at least the metal layer closest to the periphery of the chip is electrically connected to the first redistribution layer or the second redistribution layer. A fan-out semiconductor package structure as described in claim 8, wherein: the longitudinal openings of the ring plates are staggered; and a metal layer is further provided at each joint between the ferromagnetic material layer and the first encapsulation layer; wherein at least the metal layer closest to the periphery of the chip is electrically connected to the first redistribution layer or the second redistribution layer. A fan-out semiconductor package structure as described in claim 5, wherein the second microcoil comprises: a single spiral metal plate; and a ferromagnetic material layer covering the single spiral metal plate; wherein the second encapsulation layer covers the ferromagnetic material layer of the second microcoil. The fan-out semiconductor package structure as described in claim 5, wherein the second micro-coil comprises: A plurality of ring plates, which are arranged concentrically, each of which has a longitudinal opening, so that each of the ring plates has two free ends, and the free ends are electrically connected to the second external connection surface of the second redistribution layer to form a micro-coil; and A ferromagnetic material layer, which is arranged on the second external connection surface of the second redistribution layer and covers the plurality of ring plates; wherein the second encapsulation layer covers the ferromagnetic material layer of the second micro-coil. A fan-out semiconductor package structure as described in claim 1, wherein the micro-coil unit includes at least two micro-coils, and the two micro-coils are respectively spaced apart and located on two relatively outer sides of the chip. The fan-out semiconductor package structure as described in claim 13 further includes a second redistribution layer, which is opposite to the first redistribution layer and is arranged on the chip, the two microcoils and the first encapsulation layer to be electrically connected to the two microcoils; wherein the two microcoils are electrically connected to the chip in series or in parallel through the first and second redistribution layers. A fan-out semiconductor package structure as described in claim 13 or 14, wherein each of the microcoils comprises: a single spiral metal plate, the outermost portion of which is located on the corresponding outer side of the chip; and a ferromagnetic material layer covering the single spiral metal plate; wherein the first encapsulation layer covers each of the ferromagnetic material layers. The fan-out semiconductor package structure as described in claim 14, wherein each of the micro-coils comprises: A plurality of ring plates, which are arranged concentrically, and the outermost ring plate is located on the corresponding outer side of the chip; wherein each of the ring plates has a longitudinal opening, so that each of the ring plates has two free ends, and the free ends are electrically connected to the first inner connection surface of the first redistribution layer or the second redistribution layer to form a micro-coil; and A ferromagnetic material layer, which is arranged on the first inner connection surface of the first redistribution layer and covers the plurality of ring plates; wherein the first encapsulation layer covers the ferromagnetic material layer of each of the micro-coils. A fan-out semiconductor package structure as described in claim 14, wherein each of the micro-coils comprises: A plurality of ring plates, which are arranged concentrically, and the outermost ring plate is located on the corresponding outer side of the chip; wherein each of the ring plates has a longitudinal opening, so that each of the ring plates has two free ends, and the free ends are electrically connected to the first inner connection surface of the first redistribution layer or the second redistribution layer to form a micro-coil; and A plurality of ferromagnetic material layers, which are arranged on the first inner connection surface of the first redistribution layer and respectively cover the plurality of ring plates; wherein the first encapsulation layer covers the ferromagnetic material layers of each of the micro-coils. A fan-out semiconductor package structure as described in claim 16, wherein: the longitudinal openings of the ring plates are staggered; and a metal layer is further provided at each joint between the ferromagnetic material layer and the first encapsulation layer; wherein at least the metal layer closest to the periphery of the chip is electrically connected to the first redistribution layer or the second redistribution layer. A fan-out semiconductor package structure as described in claim 17, wherein: the longitudinal openings of the ring plates are staggered; and a metal layer is further provided at each joint between the ferromagnetic material layer and the first encapsulation layer; wherein at least the metal layer closest to the periphery of the chip is electrically connected to the first redistribution layer or the second redistribution layer. A method for packaging a fan-out semiconductor integrated micro-coil comprises the following steps: (a) preparing a carrier; (b) forming a lower redistribution wiring layer on the carrier; (c) forming a plurality of micro-coil units on the lower redistribution wiring layer; (d) adhering a plurality of chips to the lower redistribution wiring layer with their back surfaces, and each of the chips is located in a corresponding micro-coil unit; (e) forming a sealing layer on the lower redistribution wiring layer to cover the micro-coil units and the chips on the lower redistribution wiring layer; (f) grinding the sealing layer to provide a coplanar surface; (g) forming an upper redistribution wiring layer on the coplanar surface; and (h) A plurality of independent fan-out semiconductor package structures are cut out according to the cutting paths between the micro-coil units; each of the fan-out semiconductor package structures includes a single micro-coil unit, and the micro-coil units are at least spaced apart and located at least two opposite outer sides of the chip. A fan-out semiconductor packaging method as described in claim 20, wherein: The step (c) comprises: (c1) forming a plurality of microcoils on the lower redistribution wiring layer; ; wherein a single or a plurality of microcoils constitute each of the microcoil units and (c2) forming a plurality of ferromagnetic material layers on the lower redistribution wiring layer to respectively cover the microcoils; and The chips of the step (e) are respectively located in the middle of a single microcoil of the corresponding microcoil unit or between adjacent microcoils. A fan-out semiconductor packaging method as described in claim 21, wherein: The step (c1) is to form multiple plates of multiple single spiral metal plates, or multiple sets of concentric ring plates with longitudinal openings on the lower redistribution layer to form the micro coils correspondingly; wherein a portion of each single spiral metal plate or a portion of each ring plate is directly formed on the corresponding pad of the lower redistribution layer; The step (f) is to grind the encapsulation layer to expose the chip pads on the active surfaces of the chips, each plate of each single spiral metal plate or each ring plate, and the ferromagnetic material layers to form the coplanar surface; and In step (g), the multiple pads of the upper redistribution layer are connected to the chip pads on the active surfaces of the chips, the local plates of the single spiral metal plate, or the local ring plates. A fan-out semiconductor packaging method as described in claim 22, wherein in the step (c2), the ferromagnetic material layers formed on the lower redistribution layer respectively cover the plate body of each single spiral metal plate or the microcoil of each ring plate. A fan-out semiconductor packaging method as described in claim 22 or 23, wherein: The step (c2) is to further form a metal layer on the outer side of each of the ferromagnetic material layers; and The step (f) is to grind away the portion of the metal layer located on the top surface of each of the ferromagnetic material layers when grinding the encapsulation layer.

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