TWI881749B - Metal-insulator-metal capacitor and method of manufacturing the same - Google Patents

Abstract

A metal-insulator-metal (M-I-M) capacitor structure is provided by embodiments of this disclosure, including an interconnect structure on a substrate and a capacitor on the interconnect structure. The capacitor includes a bottom intermetal dielectric layer, a bottom electrode layer, a plurality of bottom electrode units, a plurality of upper dielectric units, a first upper electrode layer and an upper intermetal dielectric layer. The bottom intermetal dielectric layer and the bottom electrode layer are disposed on the interconnect structure. The bottom electrode units and the upper dielectric units surrounding the bottom electrode units are disposed in a layout pattern on the bottom intermetal dielectric layer and the bottom electrode layer in a middle area. The first upper electrode layer and the upper intermetal dielectric layer surrounding the first upper electrode layer are disposed on the bottom intermetal dielectric layer in a peripheral region. In addition, a method of manufacturing a M-I-M capacitor structure is also disclosed in this disclosure.

Description

Metal-insulator-metal capacitor and manufacturing method thereof

The present disclosure relates to a metal-insulator-metal capacitor and a manufacturing method thereof.

Current metal-insulator-metal (M-I-M) or metal-oxide-metal (M-O-M) capacitors mostly have a finger-type stacked structure.

However, since the lower electrode layer and the upper electrode layer of the interdigitated stacked structure metal-insulator-metal capacitor are located in the same layer of interconnect metal, and the metal-to-metal dielectric layer in the back-end-of-line (BEOL) process is used as the metal-to-metal dielectric layer between the electrode layers, the effective capacitance area of the metal-insulator-metal capacitor is limited.

The disclosed embodiment provides a method for manufacturing a capacitor structure, the method comprising the following steps. A lower intermetallic dielectric layer is formed above a substrate, and the substrate defines a middle region and a peripheral region. A finger-shaped opening is formed in the lower intermetallic dielectric layer and penetrates the lower intermetallic dielectric layer. A lower electrode layer is formed in the finger-shaped opening. A blocking layer is formed on the lower electrode layer and the lower intermetallic dielectric layer. An upper intermetallic dielectric layer is formed on the blocking layer. A plurality of mutually staggered trenches and a plurality of columnar openings are formed in the upper intermetallic dielectric layer in the middle region, and an annular recess is formed in the upper intermetallic dielectric layer in the peripheral region, and the columnar opening exposes the top surface of the lower electrode layer. Conductive material is filled in the columnar opening, the annular recess, and the staggered trenches to form a lower electrode unit, a first upper electrode layer, and a plurality of second upper electrode layers, respectively, and the bottom surface of the lower electrode unit contacts the top surface of the lower electrode layer.

The disclosed embodiments provide a capacitor structure, including a substrate, an interconnection structure, and a capacitor. The substrate defines a middle region and a peripheral region surrounding the middle region. The interconnection structure is disposed above the substrate. The capacitor is disposed on the interconnection structure and includes a lower intermetallic dielectric layer, a lower electrode layer, a plurality of lower electrode units, a plurality of upper intermetallic dielectric units, a first upper electrode layer, and an upper intermetallic dielectric layer. The lower intermetallic dielectric layer is disposed on the interconnection structure. The lower electrode layer is disposed in the lower intermetallic dielectric layer and is electrically connected to the interconnection structure. The lower electrode unit is located on the lower intermetallic dielectric layer and the lower electrode layer, and is arranged in the middle area with a layout pattern, and the lower electrode unit is electrically connected to the lower electrode layer. The upper intermetallic dielectric unit is located on the lower intermetallic dielectric layer and the lower electrode layer, and is arranged in the middle area with a layout pattern, and the upper intermetallic dielectric unit surrounds the lower electrode unit. The first upper electrode layer is located on the lower intermetallic dielectric layer, and is arranged in the peripheral area to surround the upper intermetallic dielectric unit. The upper intermetallic dielectric layer is arranged on the lower intermetallic dielectric layer, and surrounds the first upper electrode layer.

Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

In addition, for ease of description, spatially related terms such as "on", "above", "below", "between", etc. may be used in the present disclosure to describe the relationship between one element or feature and another element as shown in the accompanying drawings) or function. In addition to the orientation depicted in the accompanying drawings, spatially related terms are intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other directions), and the spatially related descriptors used in the present disclosure can also be interpreted accordingly. The terms "including", "having", "comprising", etc. used in the present disclosure are open terms, meaning including but not limited to.

In order to increase the effective area of a metal-insulator-metal (M-I-M) capacitor, the present invention redesigns the layout and structure of the electrode layer and the intermetallic dielectric layer of the capacitor, thereby enhancing the total surface area between the electrode layer and the intermetallic dielectric layer, thereby increasing the effective capacitance.

Please refer to Figures 1 to 7, which are schematic diagrams of various stages of the manufacturing method of the metal-insulator-metal (M-I-M) capacitor according to some embodiments of the present disclosure, wherein Figure 5 is a top view of one of the stages of the manufacturing method of the metal-insulator-metal (M-I-M) capacitor according to Figure 6.

As shown in FIG. 1 , for the sake of clarity, although the substrate 102 includes a plurality of functional components, they are omitted in the figure. The substrate 102 defines a middle region MR and a peripheral region PR surrounding the middle region MR. Specifically, the substrate 102 includes an interconnect structure 104 above, and a lower intermetallic dielectric layer 110 is formed on the interconnect structure 104. In some embodiments, the material forming the lower intermetallic dielectric layer 110 includes an oxide, such as silicon dioxide. Subsequently, through a lithography process and an etching process, the lower intermetallic dielectric layer 110 is penetrated to form a finger-shaped opening OP1 in the lower intermetallic dielectric layer 110.

Next, as shown in FIG. 2 , a conductive material is filled in the interdigitated opening OP1 (as shown in FIG. 1 ) to form a lower electrode layer 112, and the lower electrode layer 112 is electrically connected to the interconnect structure 104. In some embodiments, the conductive material of the lower electrode layer 112 includes copper (Cu), aluminum (Al), tungsten (W), or other conductive materials. In some embodiments, the lower electrode layer 112 is formed, for example, by a deposition process (e.g., physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition processes) and a subsequent planarization process (e.g., an etch-back process and/or a chemical mechanical polishing (CMP) process).

3 , a blocking layer 120 is formed on the lower intermetallic dielectric layer 110 and the lower electrode layer 112. In some embodiments, the blocking layer 120 includes a dielectric material, such as oxide.

As shown in FIG. 4 , an upper intermetallic dielectric layer 130 is formed on the blocking layer 120. Furthermore, the lower intermetallic dielectric layer 110 has a first thickness TH1, and the upper intermetallic dielectric layer 130 has a second thickness TH2, and the second thickness TH2 is greater than the first thickness TH1. In some embodiments, the material of the upper intermetallic dielectric layer 130 includes oxide, low-k material or other possible dielectric materials.

Please refer to FIG. 5 and FIG. 6. Through lithography and etching processes, a plurality of columnar openings OP2 and a plurality of staggered trenches TR are formed in the upper intermetallic dielectric layer 130 of the middle region MR, and a ring-shaped recess RS is formed in the upper intermetallic dielectric layer 130 of the peripheral region PR. Specifically, in the top view of FIG. 5, the columnar openings OP2 of the middle region MR are, for example, rectangular or circular. Some of the trenches TR are staggered with another portion of the trenches TR to form a checkerboard pattern or a hexagonal pattern, and an upper intermetallic dielectric unit 132 is formed between the staggered trenches TR, and the columnar openings OP2 are located in the upper intermetallic dielectric unit 132. Further, the annular recess RS of the peripheral region PR is formed around the middle region MR, and the annular recess RS is connected to the trench TR extending to the peripheral region PR. Further, taking the X direction as an example, the columnar opening OP2 has a first width W1, the annular recess RS has a second width W2, and the trench TR has a third width W3. The first width W1 is greater than the second width W2, and the second width W2 is greater than the third width W3. Similarly, the area of the columnar opening OP2 is greater than the unit area of the annular recess RS, and the unit area of the annular recess RS is greater than the unit area of the trench TR. It is worth mentioning that the width of the trench TR in the X direction may be different from the width of the trench TR in the Y direction to increase the capacitance of the metal-insulator-metal capacitor 100 (as shown in FIG. 7 ). In some embodiments, a cleaning process is performed after the etching process.

Furthermore, as shown in FIG. 6 , as mentioned above, based on the loading effect, the first width W1 of the columnar opening OP2 is greater than the second width W2 of the annular recess RS, and the second width W2 of the annular recess RS is greater than the third width W3 of the trench TR (or, the area of the columnar opening OP2 is greater than the unit area of the annular recess RS, and the unit area of the annular recess RS is greater than the unit area of the trench TR), so as to control the etching depths of the columnar opening OP2, the annular recess RS and the trench TR respectively. Specifically, since the first width W1 and the area of the columnar opening OP2 are larger than those of the annular recess RS and the trench TR, the etching rate of the columnar opening OP2 is greater than those of the annular recess RS and the trench TR. Therefore, the first depth D1 of the columnar opening OP2 reaches the top surface of the exposed lower electrode layer 112, while the second depth D2 of the annular recess RS only reaches the top surface of the exposed blocking layer 120. In addition, since the second width W2 and the unit area of the annular recess RS are larger than those of the trench TR, the etching rate of the annular recess RS is greater than that of the trench TR. Therefore, when the first depth D1 of the columnar opening OP2 reaches the top surface of the lower electrode layer 112 exposed, and the second depth D2 of the annular recess RS reaches the top surface of the exposed blocking layer 120, the third depth D3 of the trench TR is still in the upper intermetallic dielectric layer 130 of the middle region MR, and the upper intermetallic dielectric layer 130 of the third thickness TH3 is still retained between the trench TR and the blocking layer 120, that is, a bottom intermetallic dielectric layer 134 is formed to connect the upper intermetallic dielectric units 132 to each other. As can be seen from the foregoing, the first depth D1 is greater than the second depth D2, and the second depth D2 is greater than the third depth D3. In some embodiments, the etching process is a dry etching process.

Next, as shown in FIG. 7 , a conductive material is filled in the columnar opening OP2, the annular recess RS, and the trench TR (as shown in FIG. 6 ) to respectively form a lower electrode unit 152, a first upper electrode layer 154, and a second upper electrode layer 156, that is, to form a metal-insulator-metal (MIM) capacitor 100. In some embodiments, the conductive material filling the columnar opening OP2, the annular recess RS, and the trench TR includes Ta/TaN, Ti/TiN , Cu, Al, W, or other conductive materials. In some embodiments, the lower electrode unit 152, the first upper electrode layer 154, and the second upper electrode layer 156 are formed, for example, by a deposition process (e.g., a physical vapor deposition process (PVD), an atomic layer deposition process (ALD), or a plating process, or a combination thereof) and a subsequent planarization process (e.g., an etch-back process and/or a chemical mechanical polishing (CMP) process).

Specifically, the metal-insulator-metal capacitor 100 shown in FIG. 7 includes a substrate 102, an interconnect structure 104 disposed on the substrate 102, a blocking layer 120 disposed on the interconnect structure 104, and a capacitor CP disposed on the interconnect structure 104. In addition, the capacitor CP defines a middle region MR and a peripheral region PR surrounding the middle region MR, and the capacitor CP includes a lower intermetal dielectric layer 110, a lower electrode layer 112, a plurality of lower electrode units 152, a plurality of upper intermetal dielectric units 132, a first upper electrode layer 154, a second upper electrode layer 156, and an upper intermetal dielectric layer 130.

The lower intermetal dielectric layer 110 is disposed on the interconnect structure 104. The lower electrode layer 112 is disposed in the lower intermetal dielectric layer 110 in an interdigitated shape and is located in the middle region MR and is electrically connected to the interconnect structure 104.

The lower electrode unit 152 is located on the lower intermetal dielectric layer 110 and the lower electrode layer 112 and is arranged in a checkerboard pattern in the middle region MR. The bottom surface of the lower electrode unit 152 contacts the interdigitated lower electrode layer 112, that is, the lower electrode unit 152 is electrically connected to the lower electrode layer 112. In addition, the lower electrode unit 152 has a first height H1.

The upper intermetal dielectric unit 132 is located on the lower intermetal dielectric layer 110 and the lower electrode layer 112, and is arranged in the middle region MR in a layout pattern, and the bottom of the upper intermetal dielectric unit 132 is connected to each other by the bottom intermetal dielectric layer 134 of the third thickness TH3. In addition, the upper intermetal dielectric unit 132 surrounds the sidewall of the lower electrode unit 152. In some embodiments, the layout pattern is a checkerboard pattern or a hexagonal pattern.

The first upper electrode layer 154 is located on the lower intermetallic dielectric layer 110 and is disposed in the peripheral region PR to surround the upper intermetallic dielectric unit 132 disposed in the layout pattern. In addition, the bottom surface of the first upper electrode layer 154 contacts the top surface of the blocking layer 120, and the first upper electrode layer 154 has a second height H2. In some embodiments, the layout pattern is a checkerboard pattern or a hexagonal pattern. In some embodiments, the second height H2 is less than the first height H1.

The second upper electrode layer 156 is staggered in the middle region MR on the lower intermetal dielectric layer 110 and the lower electrode layer 112, and extends to the peripheral region PR to connect with the first upper electrode layer 154. In addition, the staggered second upper electrode layer 156 surrounds the sidewall of the upper intermetal dielectric unit 132. In addition, the bottom of the second upper electrode layer 156 contacts the top surface of the bottom intermetal dielectric layer 134, and the second upper electrode layer 156 has a third height H3. In some embodiments, the third height H3 is less than the second height H2, and the third height H3 is less than the first height H1. In other words, the bottom surface of the lower electrode unit 152 is lower than the bottom surface of the first upper electrode layer 154 , and the bottom surface of the first upper electrode layer 154 is lower than the bottom surface of the second upper electrode layer 156 .

The upper IMD layer 130 is disposed on the lower IMD layer 110 and in the peripheral region PR, and surrounds the outer sidewall of the first upper electrode layer 154.

In summary, through the metal-insulator-metal capacitor and the manufacturing method thereof disclosed in the present invention, the metal-insulator-metal capacitor is designed as a vertical structure spanning adjacent electrode layers and intermetallic dielectric layers, thereby increasing the total surface area between the electrode layers and the intermetallic dielectric layers to increase the effective capacitance.

Although some embodiments of the present disclosure have been described in considerable detail, other embodiments are possible. Therefore, the spirit and scope of the claims should not be limited to the embodiments described herein.

The above briefly describes the features of the various embodiments of the present disclosure, so that those skilled in the art can more easily understand the present disclosure. Any skilled in the art should understand that the present disclosure can easily serve as a basis for the modification or design of other structures or processes to achieve the same purpose and/or obtain the same advantages as the embodiments of the present disclosure. Any skilled in the art can also understand that structures equivalent to the above do not deviate from the spirit and scope of protection of the present disclosure, and can be changed, replaced and modified without departing from the spirit and scope of the present disclosure.

100                     : Metal-Insulator-Metal Capacitor 102                     : Substrate 104                     : Interconnect Structure 110                     : Lower Intermetal Dielectric Layer 112                     : Lower Electrode Layer 120                     : Blocking Layer 130                     : Upper Intermetal Dielectric Layer 132                     : Upper Intermetal Dielectric Unit 134                     : Bottom Intermetal Dielectric Layer 152                     : Lower Electrode Unit 154                     : First Upper Electrode Layer 156                     : Second upper electrode layer CP                      : Capacitor D1                      : First depth D2                      : Second depth D3                      : Third depth H1                          : First height H2                          : Second height H3                          : Third height MR                         : Middle region PR                      : Peripheral region OP1                        : Interdigitated opening OP2                        : Columnar opening RS                         : Ring-shaped depression TH1                      : First thickness TH2                       : Second thickness TH3                       : Third thickness TR                         : Trench W1                      : First width W2                      : Second width W3                      : Third width X, Y                    : Direction

The following embodiments are read with the accompanying figures to clearly understand the viewpoints of the present disclosure. It should be noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the sizes of the various features may be arbitrarily enlarged or reduced for the sake of clarity of discussion. Figures 1 to 7 are schematic diagrams of various stages of the manufacturing method of the metal-insulator-metal capacitor according to some embodiments of the present disclosure, wherein Figure 5 is a top view of one of the stages of the manufacturing method of the metal-insulator-metal capacitor according to Figure 6.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100: Metal-Insulator-Metal Capacitor

102: Substrate

104: Interconnection structure

110: Lower intermetallic dielectric layer

112: Lower electrode layer

120: barrier layer

130: Upper intermetallic dielectric layer

132: Upper intermetallic dielectric unit

134: Bottom intermetallic dielectric layer

152: Lower electrode unit

154: First upper electrode layer

156: Second upper electrode layer

CP: Capacitor

H1: First height

H2: Second height

H3: The third height

MR: Middle Zone

PR: surrounding area

TH3:Third thickness

W1: First width

W2: Second width

W3: Third width

Claims (9)

A method for manufacturing a metal-insulator-metal capacitor structure, comprising: Forming a lower intermetallic dielectric layer above a substrate, wherein the substrate defines a middle region and a surrounding region surrounding the middle region; Forming a finger-shaped opening penetrating the lower intermetallic dielectric layer in the lower intermetallic dielectric layer; Forming a lower electrode layer in the finger-shaped opening; Forming a blocking layer on the lower electrode layer and the lower intermetallic dielectric layer; Forming an upper intermetallic dielectric layer on the blocking layer; A plurality of mutually staggered trenches and a plurality of columnar openings are formed in the upper intermetallic dielectric layer in the middle region, and an annular recess is formed in the upper intermetallic dielectric layer in the peripheral region, wherein each of the columnar openings exposes the top surface of the lower electrode layer; and a conductive material is filled in the columnar openings, the annular recess and the staggered trenches to respectively form a lower electrode unit, a first upper electrode layer and a plurality of second upper electrode layers, wherein the bottom surface of the lower electrode unit contacts the top surface of the lower electrode layer. A method as described in claim 1, wherein since a first width of each of the columnar openings is greater than a second width of the annular recess, when forming the columnar openings and the annular recess, a first depth of each of the columnar openings is greater than a second depth of the annular recess. The method of claim 2, wherein the annular recess exposes a top surface of the barrier layer. A method as described in claim 1, wherein since a second width of the annular recess is greater than a third width of each of the grooves, when forming the annular recess and the grooves, a second depth of the annular recess is greater than a third depth of each of the grooves. A method as described in claim 1, wherein the grooves extend to the surrounding area and communicate with the annular recess. A metal-insulator-metal capacitor structure comprises: a substrate defining a middle region and a surrounding region surrounding the middle region; an interconnection structure disposed above the substrate; a capacitor disposed on the interconnection structure and comprising: a lower intermetallic dielectric layer disposed on the interconnection structure; a lower electrode layer disposed in the lower intermetallic dielectric layer and electrically connected to the interconnection structure; a plurality of lower electrode units located on the lower intermetallic dielectric layer and the lower electrode layer and disposed in the middle region in a layout pattern, wherein each of the lower electrode units is electrically connected to the lower electrode layer; A plurality of upper intermetallic dielectric units are located on the lower intermetallic dielectric layer and the lower electrode layer and are arranged in the middle area with the layout pattern, wherein each of the upper intermetallic dielectric units surrounds each of the lower electrode units; A first upper electrode layer is located on the lower intermetallic dielectric layer and is arranged in the peripheral area to surround the upper intermetallic dielectric units; and An upper intermetallic dielectric layer is arranged on the lower intermetallic dielectric layer and surrounds the first upper electrode layer; and A blocking layer is disposed between the lower intermetallic dielectric layer and the upper intermetallic dielectric layer and between each of the upper intermetallic dielectric units and the lower intermetallic dielectric layer, wherein the top surface of the blocking layer contacts the first upper electrode layer. The metal-insulator-metal capacitor structure as described in claim 6 further comprises: A plurality of second upper electrode layers, staggeredly disposed on the lower intermetal dielectric layer and the middle region on the lower electrode layer, and extending to the peripheral region to connect to the first upper electrode layer, wherein the staggered second upper electrode layers surround each of the upper intermetal dielectric units. A metal-insulator-metal capacitor structure as described in claim 6, wherein the bottom surface of each lower electrode unit is lower than the bottom surface of the first upper electrode layer. A metal-insulator-metal capacitor structure as described in claim 7, wherein the bottom surface of the first upper electrode layer is lower than the bottom surface of each of the second upper electrode layers.

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