TWI880769B - Method of forming opening - Google Patents

Abstract

A method of forming an opening is provided. The method of forming an opening includes the following steps: providing a substrate with contact pads formed thereon; forming a first buffer layer and a first passivation layer sequentially on the substrate; performing an etching process on the first buffer layer and the first passivation layer to form a first opening and expose part of contact pads; depositing a filling material on the first passivation layer and in the first opening to form a second buffer layer; performing a chemical mechanical polishing of the second buffer layer; forming a second passivation layer on the second buffer layer; and performing an opening process on the second buffer layer and the second passivation layer to form a second opening and expose part of contact pads. A position of the part of contact pads exposed by the first opening is the same as a position of the part of contact pads exposed by the second opening.

Description

Method of forming the opening

The present invention relates to a method for forming an opening.

In the semiconductor manufacturing process, some products need to conduct electrical tests on the openings that expose the pads before deciding on the subsequent process. For example, after the electrical test, it can be determined whether the component needs to undergo a redistribution process. If not, the component must be reprocessed. However, reprocessing can use materials such as polyimide to open the pads a second time, which will result in material residues at the bottom of the opening and exposure and development problems, and it is easy to cause the edge of the original opening to peel off, affecting the size after the second opening.

To solve this problem, the following method of forming an opening is proposed to improve the size of the secondary opening. For example, Patent Document 1 describes a wafer-level method for fine-pitch, high-aspect-ratio chip interconnection, including forming a multi-layer passivation layer and filling an under-bump metal (UMB) into the opening formed for the first time, so that the size of the opening formed for the second time is only increased by about 5% compared to the size of the opening formed for the first time.

In addition, Patent Document 2 describes a method for forming a semiconductor device, including forming a single-layer passivation layer and not filling any material into the opening formed for the first time, so that the size of the opening formed for the second time is smaller than the size of the opening formed for the first time; and filling a seed layer into the opening formed for the second time, so that the size of the opening formed for the third time is larger than the size of the opening formed for the first time and the size of the opening formed for the second time.

[Prior art literature]

[Patent document 1] US20040007779A1

[Patent Document 2] CN106328627B

The present invention provides a method for forming an opening by performing a second etching process at substantially the same position so that the opening sizes formed by the two etching processes are substantially the same.

The present invention provides a method for forming an opening, comprising: providing a substrate, on which a pad has been formed; sequentially forming a first buffer layer and a first passivation layer on the substrate; performing an etching process on the first buffer layer and the first passivation layer to form a first opening and expose a portion of the pad; depositing a filling material on the first passivation layer and in the first opening to form a second buffer layer; performing a planarization process on the second buffer layer; forming a second passivation layer on the second buffer layer; and performing an opening process on the second buffer layer and the second passivation layer to form a second opening and expose a portion of the pad. The position of the portion of the pad exposed by the first opening is the same as the position of the portion of the pad exposed by the second opening.

In an embodiment of the present invention, the size of the portion of the pad exposed by the first opening is the same as the size of the portion of the pad exposed by the second opening.

In one embodiment of the present invention, the thickness of the second buffer layer is greater than the sum of the thickness of the first buffer layer and the thickness of the first passivation layer.

In one embodiment of the present invention, the thickness of the second buffer layer is more than 1.2 times the sum of the thickness of the first buffer layer and the thickness of the first passivation layer.

In an embodiment of the present invention, the method further comprises: forming a photoresist layer on the first passivation layer to perform an etching process; and removing the photoresist layer after forming the first opening and exposing a portion of the pad.

In one embodiment of the present invention, the step of planarizing the second buffer layer is used to remove excess material so that the upper surface of the second buffer layer is coplanar with the upper surface of the first passivation layer.

In one embodiment of the present invention, the filling material includes high density plasma, silane, tetraethoxysilane, silicon dioxide or a combination thereof.

In one embodiment of the present invention, the material of the second passivation layer includes polyimide, silicon nitride, silicon oxynitride or a combination thereof.

In one embodiment of the present invention, the second passivation layer has no contact with the pad.

In one embodiment of the present invention, the method further comprises: after forming the second opening and exposing a portion of the pad, performing an ashing step or a cleaning step.

Based on the above, the method for forming an opening of the present invention includes depositing a filling material on the first passivation layer and in the first opening formed by an etching process to form a second buffer layer; and performing an opening process on the second buffer layer and the second passivation layer formed on the second buffer layer to form a second opening and expose a portion of the pad, and the position of the portion of the pad exposed by the first opening is substantially the same as the position of the portion of the pad exposed by the second opening. In this way, openings of substantially the same size can be formed at substantially the same position after a secondary etching process, so that the secondary etching process does not affect the size of the formed opening and the exposure and development process, and is suitable for manufacturing semiconductor devices.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

The present invention is more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

It should be understood that when an element is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or there may be an intermediate element. If an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connection" may refer to physical and/or electrical connection, and "electrical connection" or "coupling" may be the presence of other elements between two elements. As used herein, "electrical connection" may include physical connection (e.g., wired connection) and physical disconnection (e.g., wireless connection).

As used herein, "about", "approximately" or "substantially" includes the referenced value and the average value within an acceptable deviation range of a specific value that can be determined by a person of ordinary skill in the art, taking into account the measurement in question and the specific amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately" or "substantially" can select a more acceptable deviation range or standard deviation depending on the optical properties, etching properties or other properties, and can apply to all properties without a single standard deviation.

The terms used herein are used to describe exemplary embodiments only, rather than to limit the present disclosure. In this case, unless otherwise explained in the context, the singular form includes the plural form.

Fig. 1A to Fig. 6B are schematic top views and cross-sectional views of a method for forming an opening in a manufacturing process of a semiconductor element according to an embodiment of the present invention. Fig. 1B is a cross-sectional view taken along the section line I-I' of Fig. 1A. Fig. 2B is a cross-sectional view taken along the section line I-I' of Fig. 2A. Fig. 3B is a cross-sectional view taken along the section line I-I' of Fig. 3A. Fig. 4B is a cross-sectional view taken along the section line I-I' of Fig. 4A. Fig. 5B is a cross-sectional view taken along the section line I-I' of Fig. 5A. Fig. 6B is a cross-sectional view taken along the section line I-I' of Fig. 6A. In the schematic top view of the present embodiment, some components in the cross-sectional view are omitted to clearly illustrate the positional relationship between the components in the schematic top view.

Referring to FIG. 1A and FIG. 1B , first, a substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. In addition, although not shown in FIG. 1B , the substrate 100 may have required components such as a doped region and/or an isolation structure, and the substrate 100 may have required components such as a semiconductor element (such as an active element such as a transistor), a dielectric layer and/or an internal connection structure, etc., which are omitted here.

A pad 102 is formed on the substrate 100. The material of the pad 102 may include a conductive material, such as a conductive metal material. For example, the conductive metal material may include tungsten (W), aluminum (Al), copper (Cu), gold (Au), nickel (Ni), a combination thereof, or other suitable metals. The formation method of the pad 102 may include a deposition process, an electroplating process, a lithography process, and an etching process.

Next, a first buffer layer 110 is formed on the substrate 100. The first buffer layer 110 covers the pad 102. The material of the first buffer layer 110 may include silicon dioxide ( _SiO2 ), tantalum nitride, silicon carbide nitride, a combination thereof or other suitable materials, preferably silicon dioxide. The formation method of the first buffer layer 110 may include chemical vapor deposition or other suitable methods. The first buffer layer 110 may have a buffer function or a function of filling a gap between pads. The thickness of the first buffer layer 110 may be about 0.3 microns to about 1.2 microns, for example, about 1.0 microns. The thickness of the first buffer layer 110 may be greater than or approximately equal to the thickness of the pad 102. For example, when the first buffer layer 110 has a buffering function, its thickness may be approximately equal to the thickness of the pad 102, such as about 0.3 microns to about 0.5 microns; when the first buffer layer 110 has a function of filling a gap between pads, its thickness may be greater than the thickness of the pad 102, such as about 0.8 microns to about 1.2 microns.

Then, a first passivation layer 120 is formed on the first buffer layer 110. The material of the first passivation layer 120 may include silicon oxynitride (SiON), silicon nitride (SiN), a combination thereof or other suitable materials, preferably silicon oxynitride. The formation method of the first passivation layer 120 may include chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable methods. The formation method of the first passivation layer 120 may be the same as or different from the formation method of the first buffer layer 110. The thickness of the first passivation layer 120 may be about 0.5 microns to about 0.7 microns, for example, about 0.6 microns. The sum T1 of the thickness of the first buffer layer 110 and the thickness of the first passivation layer 120 can be selected as appropriate according to requirements, such as about 0.3 micrometers to about 2.0 micrometers, preferably about 1.5 micrometers to about 1.6 micrometers.

Referring to FIG. 2A and FIG. 2B , a photoresist layer 130 may be formed on the first passivation layer 120 to perform an etching process to form a first opening 120a. The material and thickness of the photoresist layer 130 may be selected appropriately according to the conditions of the lithography process (e.g., using i-Line or deep ultraviolet lithography (DUV)) and the etching process. There is no particular limitation on the method for forming the photoresist layer 130. For example, a well-known photoresist formation method may be used, which will not be described in detail herein.

The etching process may be performed to pattern the first passivation layer 120 and the first buffer layer 110 to form a first opening 120a. The first opening 120a exposes a portion of the pad 102a. The width W1 of the portion of the pad 102a may be selected appropriately according to the result of the electrical test and the bonding requirement.

Then, the remaining photoresist layer 130 is removed to expose the surface of the first passivation layer 120. The method of removing the remaining photoresist layer 130 may include dry ashing, wet etching or other suitable methods to remove the remaining photoresist layer and the unformed material.

Referring to FIG. 3A and FIG. 3B , a second buffer layer 140 is formed on the first passivation layer 120. The material of the second buffer layer 140 is a filling material, and the filling material may include high-density plasma, monosilane, tetraethoxysilane, silicon dioxide (SiO ₂ ), a combination thereof or other suitable materials, preferably tetraethoxysilane, silicon dioxide or a combination thereof. Tetraethoxysilane may be used as a precursor for deposition to form a silicon dioxide film. The material of the second buffer layer 140 may be the same as or different from the material of the first buffer layer 110. The method for forming the second buffer layer 140 may include chemical vapor deposition or other suitable methods. The forming method of the second buffer layer 140 may be the same as or different from the forming method of the first buffer layer 110.

The second buffer layer 140 is formed on the first passivation layer 120 and fills the first opening 120a. The second buffer layer 140 contacts the portion of the pad 102a exposed by the first opening 120a. In this embodiment, the thickness T2 of the second buffer layer 140 is greater than the sum of the thickness T1 of the first buffer layer 110 and the first passivation layer 120. In this way, the subsequent planarization process can be performed well. The thickness T2 of the second buffer layer 140 can be more than 1.2 times the sum of the thickness T1 of the first buffer layer 110 and the first passivation layer 120, preferably 1.2 to 1.5 times. For example, the thickness T2 of the second buffer layer 140 may be greater than about 0.36 micrometers, preferably about 0.36 micrometers to about 3 micrometers (eg, about 0.45 micrometers, about 2.4 micrometers, etc.), and more preferably about 0.5 micrometers to about 2.5 micrometers.

4A and 4B , the second buffer layer 140 may be subjected to a planarization process to remove a portion of the filling material so that the upper surface 140u of the second buffer layer 140 is coplanar with the upper surface 120u of the first passivation layer 120. The planarization process may include a wet polishing process, a dry polishing process, a grinding process, an etching process, or other suitable processes. The wet polishing process may include a chemical-mechanical polishing (CMP) process.

5A to 6B, after forming the second passivation layer 150 on the second buffer layer 140, an opening process is performed to form the second opening 150b. The second passivation layer 150 can be formed on the upper surface 140u of the second buffer layer 140 and the upper surface 120u of the first passivation layer 120. The second passivation layer 150 does not contact the pad 102. The second passivation layer 150 does not contact the portion of the pad 102a exposed by the first opening 120a. The material of the second passivation layer 150 may include polyimide or other suitable materials. In this embodiment, the material of the second passivation layer 150 and the material of the first passivation layer 120 are preferably different from each other. The second passivation layer 150 may be formed by a spin coating method using a lithography machine or other suitable methods.

In the present embodiment, the opening process may include first performing a photo process on the second passivation layer 150 to form an opening 150a (as shown in FIGS. 5A and 5B ). Then, an etching process is performed on the second buffer layer 140 in the opening 150a to form a second opening 150b. There is no particular restriction on the conditions of the photo process, and appropriate process conditions can be selected according to needs. In the present embodiment, the conditions of a general photo process can be used when performing the photo process, and the amount of light can be selected according to the thickness and/or width W2 of the second passivation layer 150. The etching process can use dry etching to control the cross-sectional shape of the opening. The second opening 150b exposes a portion of the pad 102b (as shown in FIGS. 6A and 6B ). The position of the portion of the pad 102b exposed by the second opening 150b is substantially the same as the position of the portion of the pad 102a exposed by the first opening 120a. The width W2 of the portion of the pad 102b is slightly greater than or approximately equal to the width W1 of the portion of the pad 102a, replacing the width W1 as the final opening size of the portion of the pad 102b. The width W2 (size) of the portion of the pad 102b exposed by the second opening 150b may be substantially the same as the width W1 (size) of the portion of the pad 102a exposed by the first opening 120a.

Finally, after forming the second opening 150b and exposing a portion of the pad 102b, an ashing step, a cleaning step or other appropriate steps may be performed to remove impurities and moisture generated during the process of forming the opening, clean the photoresist, and improve the flatness of the edge of the opening.

In summary, the method for forming an opening of the present invention includes depositing a filling material in a first opening to form a second buffer layer; performing an opening process on the second buffer layer and a second passivation layer formed thereon to form a second opening and expose a portion of the pad. Thus, the position and size of the portion of the pad exposed by the first opening can be substantially the same as the position and size of the portion of the pad exposed by the second opening, thereby improving the problem that the secondary etching process affects the size of the formed opening and the exposure and development process, that is, improving the alignment and size consistency of the secondary opening, and thus being suitable for manufacturing semiconductor devices.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

100: substrate 102: pad 102a, 102b: part of pad 110: first buffer layer 120: first passivation layer 120a: first opening 120u, 140u: upper surface 130: photoresist layer 140: second buffer layer 150: second passivation layer 150a: opening 150b: second opening I-I’: section line T1, T2: thickness W1, W2: width

1A to 6B are schematic top views and cross-sectional views of a method for forming an opening in a semiconductor device manufacturing process according to an embodiment of the present invention.

100: Base

102:Pad

102b: Partial pad

110: First buffer layer

120: First passivation layer

140: Second buffer layer

150: Second passivation layer

150b: Second opening

I-I’: section line

W2: Width

Claims (10)

A method for forming an opening, comprising: Providing a substrate on which a pad has been formed; Sequentially forming a first buffer layer and a first passivation layer on the substrate; Etching the first buffer layer and the first passivation layer to form a first opening and expose a portion of the pad; Depositing a filling material on the first passivation layer and in the first opening to form a second buffer layer; Performing a planarization process on the second buffer layer; Forming a second passivation layer on the second buffer layer; and The second buffer layer and the second passivation layer are subjected to an opening process to form a second opening and expose a portion of the pad, wherein the position of the portion of the pad exposed by the first opening is the same as the position of the portion of the pad exposed by the second opening. A method for forming an opening as described in claim 1, wherein the size of the portion of the pad exposed by the first opening is the same as the size of the portion of the pad exposed by the second opening. The method for forming an opening as described in claim 1, wherein the thickness of the second buffer layer is greater than the sum of the thickness of the first buffer layer and the thickness of the first passivation layer. The method for forming an opening as described in claim 1, wherein the thickness of the second buffer layer is more than 1.2 times the sum of the thickness of the first buffer layer and the thickness of the first passivation layer. The method for forming an opening as described in claim 1 further includes: forming a photoresist layer on the first passivation layer to perform the etching process; and removing the photoresist layer after forming the first opening and exposing the portion of the pad. A method for forming an opening as described in claim 1, wherein: In the step of performing a planarization process on the second buffer layer, a portion of the material is removed so that the upper surface of the second buffer layer is coplanar with the upper surface of the first passivation layer. A method for forming an opening as described in claim 1, wherein the filling material includes high-density plasma, silane, tetraethoxysilane, silicon dioxide or a combination thereof. The method for forming an opening as described in claim 1, wherein the material of the second passivation layer includes polyimide, silicon nitride, silicon oxynitride or a combination thereof. The method for forming an opening as described in claim 1, wherein the second passivation layer has no contact with the pad. The method for forming an opening as described in claim 1 further includes: After forming the second opening and exposing the portion of the pad, performing an ashing step or a cleaning step.

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