TWI880605B - Manufacturing method of semiconductor structure - Google Patents

Abstract

A manufacturing method of a semiconductor structure including the following steps is provided. A substrate is provided. The substrate includes a scribe line region and a device region. A dielectric structure is formed on the substrate. An interconnect structure is formed in the dielectric structure of the device region. A passivation layer is formed on the dielectric structure. The passivation layer and the dielectric structure are patterned to form a scribing trench in the dielectric structure of the scribe line region and to form an opening in the dielectric structure of the device region. An isolation material layer is formed in the scribing trench and the opening and on the passivation layer. A photoresist layer is formed on the isolation material layer in the scribing trench. A first etch back process is performed on the isolation material layer to form a first isolation layer in the scribing trench and to form a second isolation layer in the opening. The first isolation layer covers the surface of the dielectric structure exposed by the scribing trench. The photoresist layer is removed.

Description

Method for manufacturing semiconductor structure

The present invention relates to a method for manufacturing a semiconductor structure, and in particular to a method for manufacturing a semiconductor structure including a dicing trench.

After the fabrication of some semiconductor structures is completed, the dielectric structures exposed by the scribe trenches in the sawing area are exposed to the air. While the semiconductor structures are stored in the warehouse waiting for further processing by the packaging and testing factory, the components in the dielectric structures (e.g., fluorine (F)) may diffuse into the air and contaminate the topmost conductive layer (e.g., pad) exposed to the air. However, how to prevent the topmost conductive layer from being contaminated is a goal of continuous efforts.

The present invention provides a method for manufacturing a semiconductor structure, which can effectively prevent the topmost conductive layer from being contaminated.

The present invention provides a method for manufacturing a semiconductor structure, comprising the following steps. Provide a substrate. The substrate includes a cutting track area and a component area. Form a dielectric structure on the substrate. Form an internal connection structure in the dielectric structure of the component area. The internal connection structure includes multiple conductive layers. Form a protective layer on the dielectric structure. Pattern the protective layer and the dielectric structure, and form a dicing groove in the dielectric structure of the cutting track area, and form an opening in the dielectric structure of the component area. The opening exposes the topmost conductive layer. Form an isolation material layer in the dicing groove and the opening and on the protective layer. Form a photoresist layer on the isolation material layer in the dicing groove. After forming the photoresist layer, the isolation material layer is subjected to a first etching back process to form a first isolation layer in the scribe trench and a second isolation layer in the opening. The first isolation layer covers the surface of the dielectric structure exposed by the scribe trench. The photoresist layer is removed.

According to one embodiment of the present invention, in the method for manufacturing the semiconductor structure, the conductive layer may include a metal layer.

According to an embodiment of the present invention, in the manufacturing method of the semiconductor structure, the internal connection structure may further include multiple plugs. The multiple plugs may be connected to multiple conductive layers.

According to one embodiment of the present invention, in the manufacturing method of the above-mentioned semiconductor structure, the top surface of the photoresist layer can be lower than the bottom surface of the protective layer.

According to an embodiment of the present invention, in the manufacturing method of the semiconductor structure, the first etching process is, for example, a dry etching process.

According to an embodiment of the present invention, in the manufacturing method of the semiconductor structure, the method for forming the photoresist layer may include the following steps. A photoresist material layer is formed on the isolation material layer. The photoresist material layer may be filled into the scribe groove and the opening. The photoresist material layer is subjected to a second etching back process to completely remove the photoresist material layer in the opening and partially remove the photoresist material layer in the scribe groove to form a photoresist layer.

According to an embodiment of the present invention, in the manufacturing method of the semiconductor structure, the photoresist material layer is formed by, for example, a spin coating method.

According to an embodiment of the present invention, in the manufacturing method of the semiconductor structure, the second etching process is, for example, a dry etching process.

According to an embodiment of the present invention, in the manufacturing method of the semiconductor structure, the cross-sectional shape of the first isolation layer may include a U shape.

According to an embodiment of the present invention, in the manufacturing method of the above-mentioned semiconductor structure, the second isolation layer can expose the topmost conductive layer.

Based on the above, in the manufacturing method of the semiconductor structure proposed by the present invention, since the first isolation layer covers the surface of the dielectric structure exposed by the scribe groove, it can effectively prevent the components in the dielectric structure exposed by the scribe groove from diffusing into the air, thereby effectively preventing the topmost conductive layer from being contaminated.

In order to make the above features and advantages of the present invention more clearly understood, the following is a detailed description of the embodiments with the accompanying drawings.

10:Semiconductor structure

100: Base

102: Dielectric structure

104: Internal connection structure

106: Conductive layer

108: Plug

110: Protective layer

112: Isolation material layer

112a,112b: Isolation layer

114: Photoresist layer

114a: Photoresist layer

OP1: Open mouth

R1: Cutting area

R2: Component area

S1: Top surface

S2: Bottom surface

T1: Slice groove

Figures 1A to 1G are cross-sectional views of the manufacturing process of a semiconductor structure according to some embodiments of the present invention.

The following examples are listed and illustrated in detail, but the examples provided are not intended to limit the scope of the invention. For ease of understanding, the same components will be indicated by the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn in original size. In fact, the size of various features can be arbitrarily increased or decreased for the sake of clarity.

Figures 1A to 1G are cross-sectional views of the manufacturing process of a semiconductor structure according to some embodiments of the present invention.

Referring to FIG. 1A , a substrate 100 is provided. The substrate 100 includes a cutting path region R1 and a device region R2. In some embodiments, the device region R2 may be a region for forming active devices and/or passive devices. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In addition, although not shown in the figure, the required semiconductor devices (such as active devices and/or passive devices) may be formed on and/or in the substrate 100, and their description is omitted here.

Next, a dielectric structure 102 is formed on the substrate 100. In some embodiments, the dielectric structure 102 may be a multi-layer structure. In some embodiments, the material of the dielectric structure 102 may include fluorosilicate glass (FSG), silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the dielectric structure 102 is formed by, for example, chemical vapor deposition.

In addition, an interconnect structure 104 is formed in the dielectric structure 102 of the device region R2. In some embodiments, the interconnect structure 104 can be electrically connected to a semiconductor device (not shown) in the device region R2. The interconnect structure 104 includes a plurality of conductive layers 106. In some embodiments, the topmost conductive layer 106 can be used as a pad. In some embodiments, the conductive layer 106 can include a metal layer. In addition, the interconnect structure 104 can further include a plurality of plugs 108. The plurality of plugs 108 can be connected to the plurality of conductive layers 106. In some embodiments, the material of the plugs 108 is, for example, a conductive material such as metal. In addition, the number of conductive layers 106 and the number of plugs 108 are not limited to the numbers shown in the figure. As long as the number of conductive layers 106 and plugs 108 is multiple, it falls within the scope of the present invention. In some embodiments, the interconnect structure 104 can be formed by an interconnect process.

Next, a protective layer 110 is formed on the dielectric structure 102. The protective layer 110 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the protective layer 110 is, for example, silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the method of forming the protective layer 110 is, for example, chemical vapor deposition.

Referring to FIG. 1B , the protective layer 110 and the dielectric structure 102 are patterned, and a scribe trench T1 is formed in the dielectric structure 102 in the scribe area R1, and an opening OP1 is formed in the dielectric structure 102 in the device area R2. The scribe trench T1 may expose the surface of the dielectric structure 102 in the scribe area R1. The opening OP1 may expose the topmost conductive layer 106. In some embodiments, the scribe trench T1 and the opening OP1 may pass through the protective layer 110. In some embodiments, the protective layer 110 and the dielectric structure 102 may be patterned by a lithography process and an etching process (e.g., a dry etching process). In some embodiments, the trench T1 and the opening OP1 can be formed by the same mask. Therefore, the dicing trench T1 and the opening OP1 can be formed simultaneously without adding an additional mask, thereby effectively reducing the manufacturing cost.

Referring to FIG. 1C , an isolation material layer 112 is formed in the dicing trench T1 and the opening OP1 and on the protective layer 110. The isolation material layer 112 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the isolation material layer 112 is, for example, silicon nitride, silicon oxynitride (SiON) or a combination thereof. In some embodiments, the isolation material layer 112 is formed by, for example, chemical vapor deposition.

Referring to FIG. 1D , a photoresist material layer 114 may be formed on the isolation material layer 112. The photoresist material layer 114 is filled into the scribe trench T1 and the opening OP1. In some embodiments, the photoresist material layer 114 is formed by, for example, a spin coating method.

Referring to FIG. 1E , the photoresist layer 114 may be subjected to an etching back process to completely remove the photoresist layer 114 in the opening OP1 and partially remove the photoresist layer 114 in the scribe trench T1 to form a photoresist layer 114a. Thus, the photoresist layer 114a may be formed on the isolation material layer 112 in the scribe trench T1. In some embodiments, the top surface S1 of the photoresist layer 114a may be lower than the bottom surface S2 of the protective layer 110. In some embodiments, the etching back process performed on the photoresist layer 114 is, for example, a dry etching process.

1F, after forming the photoresist layer 114a, the isolation material layer 112 is etched back to form an isolation layer 112a in the scribe trench T1 and an isolation layer 112b in the opening OP1. The isolation layer 112a covers the surface of the dielectric structure 102 exposed by the scribe trench T1. In some embodiments, the cross-sectional shape of the isolation layer 112a may include a U-shape. In some embodiments, the isolation layer 112b may expose the topmost conductive layer 106. In addition, since the isolation layer 112a covers the surface of the dielectric structure 102 exposed by the scribe trench T1, it can effectively prevent the components (such as fluorine) in the dielectric structure 102 exposed by the scribe trench T1 from diffusing into the air, thereby effectively preventing the topmost conductive layer 106 from being contaminated. In some embodiments, the etching back process performed on the isolation material layer 112 is, for example, a dry etching process.

Please refer to FIG. 1G to remove the photoresist layer 114a. In some embodiments, the photoresist layer 114a is removed by, for example, plasma ashing.

Based on the above embodiments, it can be known that in the manufacturing method of the semiconductor structure 10, since the isolation layer 112a covers the surface of the dielectric structure 102 exposed by the scribe trench T1, it can effectively prevent the components in the dielectric structure 102 exposed by the scribe trench T1 from diffusing into the air, thereby effectively preventing the topmost conductive layer 106 from being contaminated.

In summary, in the method for manufacturing the semiconductor structure of the above embodiment, since the isolation layer covers the surface of the dielectric structure exposed by the scribe groove, the components in the dielectric structure exposed by the scribe groove can be effectively prevented from diffusing into the air, thereby effectively preventing the topmost conductive layer from being contaminated.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the attached patent application.

100: Base

102: Dielectric structure

104: Internal connection structure

106: Conductive layer

108: Plug

110: Protective layer

112a,112b: Isolation layer

114a: Photoresist layer

OP1: Open mouth

R1: Cutting area

R2: Component area

S1: Top surface

S2: Bottom surface

T1: Slice groove

Claims (10)

A method for manufacturing a semiconductor structure, comprising: Providing a substrate, wherein the substrate comprises a cutting zone and a device zone; Forming a dielectric structure on the substrate; Forming an internal connection structure in the dielectric structure of the device zone, wherein the internal connection structure comprises a plurality of conductive layers; Forming a protective layer on the dielectric structure; Patterning the protective layer and the dielectric structure, and forming a dicing trench in the dielectric structure of the cutting zone, and forming an opening in the dielectric structure of the device zone, wherein the opening exposes the topmost conductive layer; Forming an isolation material layer in the dicing trench and the opening and on the protective layer; Forming a photoresist layer on the isolation material layer in the dicing trench; After forming the photoresist layer, performing a first etching back process on the isolation material layer to form a first isolation layer in the scribe trench and a second isolation layer in the opening, wherein the first isolation layer covers the surface of the dielectric structure exposed by the scribe trench; and removing the photoresist layer. A method for manufacturing a semiconductor structure as described in claim 1, wherein the conductive layer includes a metal layer. The method for manufacturing a semiconductor structure as described in claim 1, wherein the internal connection structure further includes: A plurality of plugs connected to a plurality of the conductive layers. A method for manufacturing a semiconductor structure as described in claim 1, wherein the top surface of the photoresist layer is lower than the bottom surface of the protective layer. A method for manufacturing a semiconductor structure as described in claim 1, wherein the first etching process includes a dry etching process. The method for manufacturing a semiconductor structure as described in claim 1, wherein the method for forming the photoresist layer comprises: forming a photoresist material layer on the isolation material layer, wherein the photoresist material layer fills the scribe groove and the opening; and performing a second etching back process on the photoresist material layer to completely remove the photoresist material layer in the opening and partially remove the photoresist material layer in the scribe groove to form the photoresist layer. A method for manufacturing a semiconductor structure as described in claim 6, wherein the method for forming the photoresist material layer includes a spin coating method. A method for manufacturing a semiconductor structure as described in claim 6, wherein the second etching process includes a dry etching process. A method for manufacturing a semiconductor structure as described in claim 1, wherein the cross-sectional shape of the first isolation layer includes a U-shape. A method for manufacturing a semiconductor structure as described in claim 1, wherein the second isolation layer exposes the topmost conductive layer.

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