TWI880530B - Photomask for semiconductor manufacturing and method for modifying photomask pattern - Google Patents

Abstract

A photomask for semiconductor manufacturing includes at least one line segment and a plurality of end-additional blocks. The line segment corresponds to the structure of a semiconductor device, and the end-additional blocks are disposed at ends of the line segment. Each of end additional blocks is a hollow structure surrounded by a first line, wherein the line width of the first line is less than the lithography resolution. A method for modifying photomask pattern includes providing an original pattern of a semiconductor device containing at least one line segment, and then performing de-rounding process on the line segment to output a mask pattern. The de-rounding process includes disposing a plurality of end-additional blocks at ends of the line segment. Each of end additional blocks is a hollow structure surrounded by a first line, wherein the line width of the first line is less than the lithography resolution.

Description

Semiconductor manufacturing mask and method for correcting mask pattern

The present invention relates to an optical lithography correction technology (OPC), and more particularly to a photomask for semiconductor manufacturing and a method for correcting a photomask pattern.

In the field of semiconductor manufacturing, in order to form a specific pattern on a substrate (including various component patterns, such as gates, contacts, etc.), the corresponding pattern is first designed in a computer system, then output to a mask after OPC, and then the pattern on the mask is transferred to the semiconductor component using lithography and etching steps.

However, the current OPC technology usually adds auxiliary patterns such as hammer heads and square serifs to the mask pattern to solve the problems of corner rounding and line-end shortening. Once there are dense patterns in the semiconductor device, it is difficult to place it between the dense patterns.

The present invention provides a photomask for semiconductor manufacturing, which can solve the problems of rounded corners of square imaging and shortened line ends, and is suitable for dense circuit patterns.

The present invention also provides a method for correcting a mask pattern, which can produce a mask with an OPC pattern.

The semiconductor manufacturing mask of the present invention includes at least one line segment and a plurality of end additional blocks. The line segment corresponds to the structure of a semiconductor element, and the end additional blocks are arranged at a plurality of ends of at least one line segment. Each end additional block is a hollow structure surrounded by a first line, wherein the line width of the first line is smaller than the lithography resolution.

The method for correcting a mask pattern of the present invention comprises first providing an original pattern of a semiconductor element, the original pattern comprising at least one line segment, and then performing a rounding process on the line segment to output a mask pattern. The rounding process comprises setting a plurality of end additional blocks at the end of at least one line segment, and each end additional block is a hollow structure surrounded by a first line, wherein the line width of the first line is less than the lithography resolution.

In various embodiments of the present invention, the size of one of the above-mentioned multiple end additional blocks is larger than the size of the corresponding end.

In various embodiments of the present invention, the width of one of the above-mentioned multiple end additional blocks is equal to the width of the corresponding end.

In various embodiments of the present invention, the at least one line segment is a plurality of line segments, and a plurality of end additional blocks are disposed at a plurality of ends of each line segment.

In various embodiments of the present invention, the at least one line segment is a plurality of line segments, and the distance between adjacent line segments in the plurality of line segments is lower than a predetermined value, then the adjacent line segments in the plurality of line segments share an end additional block.

In each embodiment of the present invention, the above-mentioned at least one line segment has a corner, and an inner additional block and an outer additional block are respectively provided on the inner side and the outer side of the corner, the inner additional block has a hollow structure surrounded by a second line, and the outer additional block has a hollow structure surrounded by a third line, wherein the line widths of the second line and the third line are both smaller than the lithography resolution.

In various embodiments of the present invention, the size of the inner additional block is larger than the size of the outer additional block.

In various embodiments of the present invention, the number of the above-mentioned external additional blocks is more than one.

Based on the above, the present invention uses a hollow structure surrounded by lines with a line width smaller than the lithography resolution as an additional block of the mask pattern, which can simultaneously solve the problems of rounding the corners of the imaging square and shortening the line ends.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

The following description provides a number of embodiments for implementing different features of the present invention. In addition, these embodiments are exemplary only and are not intended to limit the scope and application of the present invention. Moreover, for the sake of clarity, the relative sizes (e.g., length, width, spacing, etc.) and relative positions of regions or structural components may be reduced or enlarged. In addition, similar or identical element symbols used in different figures represent similar or identical components or features.

FIG. 1A is an exemplary layout diagram of a semiconductor manufacturing mask according to a first embodiment of the present invention.

The first embodiment of the present invention is to calibrate the pattern corresponding to the semiconductor element 102 and output it as a mask 100 for semiconductor manufacturing. For example, a line segment 104 in FIG. 1A corresponds to the structure of the semiconductor element 102. Then, in order to perform corner rounding and line-end shortening, an end additional block 106 can be set at the end 104a of the line segment 104. Each end additional block 106 is a hollow structure surrounded by a first line 108, wherein the line width l1 and the line width l2 of the first line 108 are both smaller than the lithography resolution. The line width l1 refers to the width of the first line 108 extending in the vertical direction, and the line width l2 refers to the width of the first line 108 extending in the horizontal direction. The line width l1 may be the same as or different from the line width l2.

In FIG1A , the width w of the end additional block 106 is equal to the width w of the corresponding end 104a. However, the present invention is not limited thereto; in another semiconductor manufacturing mask 110 in FIG1B , the line segment 104 corresponding to the semiconductor element 102 in FIG1A may also be provided with a larger end additional block 112 at the end 104a. The “size” in the text represents the covering area, width, height or radius of an area or figure; for example, the width w’ of the end additional block 112 in FIG1B is greater than the width w of the corresponding end 104a. Moreover, since the line width of the line of the additional block 112 at the end is smaller than the lithography resolution, the pattern of the patterned photoresist PR after exposure and development using the semiconductor manufacturing mask 110 at most leaves some photoresist residue at both ends, as shown in the middle of FIG1B. If the patterned photoresist PR is used as an etching mask, the final pattern FP obtained after etching will be as shown in the right of FIG1B, and its end has no obvious rounded corners and indentation, thereby improving the problems of corner rounding and line end shortening.

Fig. 2 is a schematic diagram of a semiconductor device layout with a dense pattern. Fig. 3 is an exemplary layout diagram of a semiconductor manufacturing mask according to a second embodiment of the present invention.

Please refer to FIG. 2 . When the structure of the semiconductor device 200 is composed of six long strips L1 to L6, the semiconductor manufacturing mask 300 has six corresponding line segments 302, 304, 306, 308, 310 and 312 as shown in FIG. 3 , and an end additional block 314 is set at each end. Moreover, if the distance between adjacent line segments among the line segments 302, 304, 306, 308, 310 and 312 is less than a predetermined value, the adjacent line segments share an end additional block. The so-called "predetermined value" in this article is related to the light source used by the lithography machine. For example, taking a four-fold miniaturized deep ultraviolet immersion lithography machine as an example, the predetermined value used on its mask is set to "less than 0.1 μm"; and so on. For example, line segment 306 and line segment 312 are arranged in sequence along the horizontal direction. If a four-fold zoom immersion deep ultraviolet lithography machine is used and the distance d1 between line segment 306 and line segment 312 is less than 0.1 μm, an end additional block 316 is shared between line segment 306 and line segment 312; and so on. In FIG. 3 , line segment 310 and line segment 312 are arranged in sequence along the vertical direction. If the distance d2 between line segment 310 and line segment 312 is also less than a predetermined value, an end additional block 318 can be shared between line segment 310 and line segment 312; and so on. The above-mentioned end additional blocks 314, 316 and 318 are hollow structures surrounded by the first line 320, wherein the line width l1 and the line width l2 of the first line 320 are both smaller than the lithography resolution. The definitions of the line width l1 and the line width l2 are the same as those in the first embodiment and will not be repeated. As the distance between adjacent line segments in dense circuit graphics is getting smaller and smaller, auxiliary graphics such as hammer heads and square serifs in traditional OPC graphics will be difficult to add between adjacent line segments. In comparison, the graphics improvement method of the present invention can solve the aforementioned problems, thereby correcting the problems of rounded corners and shortened line ends of semiconductor components 200 with dense circuit graphics.

In addition, in the second embodiment, the end additional blocks 314, 316 and 318 are disposed at the ends of each line segment 302, 304, 306, 308, 310 and 312. However, the present invention is not limited thereto, and the end additional block 314, the end additional block 316 or the end additional block 318 may be disposed only at the ends of some line segments according to design requirements.

Fig. 4 is a schematic diagram of a semiconductor device layout with a corner. Fig. 5 is an exemplary layout diagram of a semiconductor manufacturing mask according to a third embodiment of the present invention.

Please refer to FIG4 and FIG2 . When the semiconductor device 400 has a structure with a corner C1, the semiconductor manufacturing mask 500 also includes a line segment 502 with a corresponding corner C2 as shown in FIG5 , and an end additional block 504 is provided at both the end 502a and the end 502b of the line segment 502. In addition, in order to round the square corner, an inner side additional block 506 and an outer side additional block 508 are provided at the inner side and the outer side of the corner C2, respectively, wherein the inner side of the corner C2 refers to the side with a smaller angle, and the outer side of the corner C2 refers to the side with a larger angle. For example, if the angle of corner C2 is 90 degrees, the inner side refers to the side with an angle of 90 degrees, and the outer side refers to the side with an angle of 270 degrees, and so on.

The end additional block 504 has a hollow structure surrounded by a first line 510, wherein the line width l1 and the line width l2 of the first line 510 are both smaller than the lithography resolution. The definitions of the line width l1 and the line width l2 are the same as those in the first embodiment and will not be repeated. The inner additional block 506 has a hollow structure surrounded by a second line 512, and the outer additional block 508 has a hollow structure surrounded by a third line 514, wherein the line width l3 of the second line 512 and the line width l4 of the third line 514 are both smaller than the lithography resolution. The line width l3 may be the same as or different from the line width l4, for example, the line width l3 is larger than the line width l4. In this embodiment, the size of the inner additional block 506 is larger than the size of the outer additional block 508. Moreover, the number of the outer additional blocks 508 in this embodiment is 2. However, the present invention is not limited thereto, and only one or more than two outer additional blocks 508 may be provided according to design requirements.

FIG. 6 is a step diagram of a method for correcting a mask pattern according to a third embodiment of the present invention.

Please refer to FIG. 6 , firstly, step 600 is performed to provide an original graphic of a semiconductor element, where the original graphic includes a plurality of line segments.

Then, in step 610, the corresponding plurality of line segments are de-rounded to output a mask pattern. The detailed steps of the de-rounded processing can be referred to FIG. 7.

In FIG7 , step 700 is first performed to set an end additional block at the end of the line segment. Each end additional block is a hollow structure surrounded by a first line, wherein the line width of the first line is less than the lithography resolution. In one embodiment, the width of one of the end additional blocks may be equal to the width of the corresponding end, as shown in FIG1A . In another embodiment, the size of one of the end additional blocks may be larger than the size of the corresponding end, as shown in FIG1B . If the distance between two adjacent line segments among a plurality of line segments is less than a predetermined value, the adjacent line segments may share an end additional block, as shown in FIG3 .

Then in step 702, it is determined whether the line segment has a corner. If it does, step 704 is performed; if it does not, step 710 is performed to output the mask pattern.

In step 704, an inner additional block is set on the inner side of the corner of the line segment, wherein the inner side of the corner refers to the side with a smaller angle.

Then in step 706, it is determined whether the outer side of the corner is greater than 180 degrees. If the outer side of the corner is greater than 180 degrees, step 708 is performed; if the outer side of the corner is not greater than 180 degrees, step 710 is performed to output the mask pattern.

In step 708, an outer additional block is set outside the corner of the line segment, wherein the outer side of the corner refers to the side with a larger angle, and the number of the outer additional blocks is more than one, such as two outer additional blocks as shown in FIG5. Moreover, in one embodiment, the size of the outer additional block is smaller than the size of the inner additional block.

The following two embodiments are semiconductor manufacturing masks output according to the above method for correcting the mask pattern.

First, Fig. 8 is a schematic diagram of a semiconductor device layout with dense circuit patterns and corners. Fig. 9 is an exemplary layout diagram of a semiconductor manufacturing mask according to a fourth embodiment of the present invention.

8 , when the structure of the semiconductor device 800 includes the strip region L7 and the strip region L8 and a region 802 having corners C3 and C4 , a semiconductor manufacturing mask 900 is shown in FIG. 9 .

According to the steps of the rounding process in FIG. 7 , three corresponding line segments 902, 904 and 906 are first configured, wherein line segment 902 corresponds to the strip area L7, line segment 904 corresponds to the strip area L8, line segment 906 corresponds to the area 802, corner C5 corresponds to corner C3, and corner C6 corresponds to corner C4. Then, end additional blocks 908 are set at the ends of line segment 902, line segment 904 and line segment 906 (step 700). Moreover, the distance between line segment 902 and line segment 906 is very short, so the two line segments share an end additional block 908'; similarly, line segment 904 and line segment 906 also share an end additional block 908'. Then, an inner additional block 910 is set inside the corner C5 and the corner C6 of the line segment 906 (step 704). Since the outer sides of the corner C6 and the corner C6 are both greater than 180 degrees, an outer additional block should be set (step 708), but since the end additional block 908' already exists, the end additional block 908' is also used as the outer additional block, and the size of the inner additional block 910 is larger.

Fig. 10 is a schematic diagram of a layout of a semiconductor device with a complex shape. Fig. 11 is an exemplary layout diagram of a semiconductor manufacturing mask according to a fifth embodiment of the present invention.

10 , when the semiconductor device 1000 has a complex shape (including corners C7 and C8 ), a semiconductor manufacturing mask 1100 is shown in FIG. 11 .

According to the steps of the rounding treatment in FIG. 7 , firstly, a line segment 1102 corresponding to the semiconductor element 1000 is configured, wherein the corner C9 corresponds to the corner C7, and the corner C10 corresponds to the corner C8. Then, an end additional block 1104 is set at the end 1102a, the end 1102b, and the end 1102c of the line segment 1102 (step 700). Then, an inner additional block 1106 is set at the inner side of the corner C9 and the corner C10 of the line segment 1102 (step 704). Since the outer sides of the corners C9 and C10 are not greater than 180 degrees, the mask pattern can be directly output (step 710).

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

100, 110, 300, 500, 900, 1100: Photomask for semiconductor manufacturing 102, 200, 400, 800, 1000: Semiconductor element 104, 302, 304, 306, 308, 310, 312, 502, 902, 904, 906, 1102: Line segment 104a, 502a, 502b, 1102a, 1102b, 1102c: End 106, 112, 314, 316, 318, 504, 908, 908', 1104: End additional block 108, 320, 510: First line 506, 910, 1106: Inner additional block 508: External additional block 512: Second line 514: Third line 600, 610, 700, 702, 704, 706, 708, 710: Steps 802: Region C1, C2, C3, C4, C5, C6, C7, C8, C9, C10: Corner d1, d2: Distance FP: Final pattern l1, l2, l3, l4: Line width L1, L2, L3, L4, L5, L6, L7, L8: Strip area PR: Patterned photoresist w, w’: Width

FIG. 1A is an exemplary layout diagram of a semiconductor manufacturing mask according to the first embodiment of the present invention. FIG. 1B is another exemplary layout diagram of the semiconductor manufacturing mask of the first embodiment. FIG. 2 is a schematic diagram of a semiconductor element layout with a dense circuit pattern. FIG. 3 is an exemplary layout diagram of a semiconductor manufacturing mask according to the second embodiment of the present invention. FIG. 4 is a schematic diagram of a semiconductor element layout with a corner. FIG. 5 is an exemplary layout diagram of a semiconductor manufacturing mask according to the third embodiment of the present invention. FIG. 6 is a step diagram of a method for correcting a mask pattern according to the third embodiment of the present invention. FIG. 7 is a step diagram of a rounding treatment of the third embodiment. FIG8 is a schematic diagram of a semiconductor component layout with dense circuit patterns and corners. FIG9 is an exemplary layout diagram of a semiconductor manufacturing mask according to the fourth embodiment of the present invention. FIG10 is a schematic diagram of a semiconductor component layout with a complex shape. FIG11 is an exemplary layout diagram of a semiconductor manufacturing mask according to the fifth embodiment of the present invention.

100: Photomask for semiconductor manufacturing

102: Semiconductor components

104: Line segment

104a: End

106: Additional block at the end

108: The first line

11, 12: Line width

w: width

Claims (16)

A photomask for semiconductor manufacturing includes: At least one line segment, corresponding to the structure of a semiconductor element, wherein the at least one line segment has a corner; Multiple end additional blocks, arranged at multiple ends of the at least one line segment, and each of the end additional blocks is a hollow structure surrounded by a first line, wherein the line width of the first line is less than the lithography resolution; and An inner additional block, arranged on the inner side of the corner, the inner additional block has a hollow structure surrounded by a second line, wherein the line width of the second line is less than the lithography resolution. A semiconductor manufacturing mask as described in claim 1, wherein the size of one of the multiple end addition blocks is larger than the size of the corresponding end. A semiconductor manufacturing mask as described in claim 1, wherein the width of one of the multiple end addition blocks is equal to the width of the corresponding end. A semiconductor manufacturing mask as described in claim 1, wherein the at least one line segment is a plurality of line segments, and the plurality of end additional blocks are disposed at the plurality of ends of each of the line segments. As described in claim 1, in the semiconductor manufacturing mask, wherein the at least one line segment is a plurality of line segments, and the distance between adjacent line segments in the plurality of line segments is lower than a predetermined value, the adjacent line segments in the plurality of line segments share one end additional block. The semiconductor manufacturing mask as described in claim 1 further includes an outer additional block disposed on the outer side of the corner, wherein the outer additional block has a hollow structure surrounded by a third line, wherein the line width of the third line is smaller than the lithography resolution. A semiconductor manufacturing mask as described in claim 6, wherein the size of the inner additional area is larger than the size of the outer additional area. A semiconductor manufacturing mask as described in claim 6, wherein the number of the outer additional blocks is one or more. A method for correcting a mask pattern comprises: providing an original pattern of a semiconductor element, the original pattern comprising at least one line segment, wherein the at least one line segment has a corner; and performing a rounding process on the at least one line segment to output a mask pattern, wherein the rounding process comprises setting a plurality of end additional blocks at a plurality of ends of the at least one line segment and setting an inner additional block at the inner side of the corner, and each of the end additional blocks is a hollow structure surrounded by a first line, and the inner additional block has a hollow structure surrounded by a second line, wherein the line widths of the first line and the second line are both smaller than the lithography resolution. A method for correcting a mask pattern as described in claim 9, wherein a size of one of the multiple end additional blocks is larger than a size of the corresponding end. A method for correcting a mask pattern as described in claim 9, wherein a width of one of the plurality of end additional blocks is equal to a width of the corresponding end. A method for correcting a mask pattern as described in claim 9, wherein the at least one line segment is a plurality of line segments, and the plurality of end additional blocks are disposed at the plurality of ends of each of the line segments. In the method for correcting a mask pattern as described in claim 9, wherein the at least one line segment is a plurality of line segments, and the distance between adjacent line segments in the plurality of line segments is lower than a predetermined value, the adjacent line segments in the plurality of line segments share one end additional block. The method for correcting a mask pattern as described in claim 9, wherein the de-rounding process further includes: Providing an outer additional block on the outer side of the corner, wherein the outer additional block has a hollow structure surrounded by a third line, wherein the line width of the third line is less than the lithography resolution. A method for correcting a mask pattern as described in claim 14, wherein a size of the inner additional block is larger than a size of the outer additional block. A method for correcting a mask pattern as described in claim 14, wherein the number of the outer additional blocks is more than one.