TWI879662B - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, an etch stop layer, an intermediate layer, and a reaction layer. The etch stop layer is disposed on the substrate. The intermediate layer is disposed on the etch stop layer and has a plurality of first hollowed portions. The reaction layer is disposed on the intermediate layer and has a plurality of second hollowed portions. Each of the second hollowed portions communicates to each of the first hollowed portions. Each of the second hollowed portions has a first width. Each of the remaining portions of the reaction layer has a second width. A sum of the first width and the second width is greater than or equal to 300 nanometers.

Description

Semiconductor device and method for manufacturing the same

The present disclosure relates to a semiconductor device and a method for manufacturing the same.

In the semiconductor manufacturing process, the principle of alignment is that after the light hits the alignment mark, the sensor receives the light of different light orders reflected from the upper surface and the alignment mark pattern, and then the semiconductor machine determines whether the semiconductor machine is aligned with the semiconductor component to be processed.

However, sometimes the alignment mark may have poor alignment quality because the height difference between the upper surface of the alignment mark and the depression of the pattern is too small, resulting in interference between the signals reflected from the two layers.

Therefore, there is an urgent need in the art for a semiconductor device and a manufacturing method thereof that can solve the above problems.

In view of this, one purpose of the present disclosure is to provide a semiconductor device and a manufacturing method thereof that can solve the above-mentioned problems.

In order to achieve the above-mentioned purpose, according to one embodiment of the present disclosure, a semiconductor device includes a substrate, an etch stop layer, a reaction layer and an intermediate layer. The etch stop layer is disposed on the substrate. The reaction layer is disposed above the etch stop layer and has a plurality of first hollow portions. The intermediate layer is disposed between the etch stop layer and the reaction layer and has a plurality of second hollow portions. Each of the first hollow portions is connected to each of the second hollow portions. Each of the first hollow portions has a first width, and each of the remaining portions of the reaction layer has a second width. The second hollow portions penetrate the intermediate layer and expose the etch stop layer.

In one or more embodiments of the present disclosure, the second width is greater than or equal to 150 nanometers.

In one or more embodiments of the present disclosure, each of the first hollow portions has a third width, and the third width is the same as the second width.

In one or more embodiments of the present disclosure, the second hollow portions are substantially aligned with the first hollow portions in a direction perpendicular to the upper surface of the substrate.

In one or more embodiments of the present disclosure, the etching resistance of the reactive layer is less than or equal to the etching resistance of the intermediate layer, and the etching resistance of the intermediate layer is less than the etching resistance of the etch stop layer.

In one or more embodiments of the present disclosure, the etch stop layer and the reactive layer are dielectric anti-reflective coatings.

To achieve the above-mentioned purpose, according to an embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: sequentially forming a substrate, an etching stop layer, an intermediate layer, a reaction layer, and a patterned etching mask layer; forming a plurality of first hollow portions on the patterned etching mask layer, wherein each of the first hollow portions of the patterned etching mask layer has a first width, and the remaining portion of the patterned etching mask layer has a first width. Each of the positions has a second width, and the sum of the first width and the second width is greater than or equal to 300 nanometers; a plurality of second hollow portions are formed on the reaction layer by means of the first hollow portion of the patterned etching mask layer; a plurality of third hollow portions are formed on the middle layer by means of the second hollow portion of the reaction layer, wherein the third hollow portions penetrate the middle layer and expose the etching stop layer; and the patterned etching mask layer is removed.

In one or more embodiments of the present disclosure, the second width is greater than or equal to 150 nanometers.

In one or more embodiments of the present disclosure, the step of removing the patterned etching mask layer is performed after the step of forming a plurality of second hollow portions on the reaction layer through the first hollow portion of the patterned etching mask layer and before the step of forming a third hollow portion on the intermediate layer through the second hollow portion of the reaction layer.

In one or more embodiments of the present disclosure, the step of removing the patterned etching mask layer is performed after the step of forming a third hollow portion on the intermediate layer through the second hollow portion of the reactive layer.

In summary, in the semiconductor device and the manufacturing method thereof disclosed in the present invention, since the sum of the width of the remaining portion of the reaction layer and the width of the hollow portion of the reaction layer is greater than or equal to 300 nanometers, and the width of the hollow portion of the reaction layer is greater than or equal to 150 nanometers, it can help reduce the difficulty of etching downward. In the semiconductor device and the manufacturing method thereof disclosed in the present invention, since the etching stop layer is disposed between the substrate and the intermediate layer, it can be ensured that the hollow portion penetrates the reaction layer and the intermediate layer but does not penetrate the etching stop layer, thereby properly controlling the depth of each hollow portion. The disclosed semiconductor device configured as an alignment mark and the manufacturing method thereof effectively improve the strength of the alignment signal by increasing the difference between the hollow part and the remaining part.

The above description is only used to explain the problem to be solved by the present disclosure, the technical means for solving the problem, and the effects produced, etc. The specific details of the present disclosure will be introduced in detail in the following implementation method and related drawings.

The following will disclose multiple embodiments of the present disclosure with drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some commonly used structures and components will be depicted in the drawings in a simple schematic manner. The same reference numerals will be used to represent the same or similar components in all drawings.

Please refer to FIG. 1. FIG. 1 is a flow chart of a method M for manufacturing a semiconductor device 100 as shown in FIG. 6 according to an embodiment of the present disclosure. The method M shown in FIG. 1 includes step S101, step S102, step S103, step S104, and step S105. For a better understanding of step S101, please refer to FIG. 1 and FIG. 2. For a better understanding of step S102, please refer to FIG. 1 and FIG. 3. For a better understanding of step S103, please refer to FIG. 1 and FIG. 4. For a better understanding of step S104, please refer to FIG. 1 and FIG. 5. For a better understanding of step S105, please refer to FIG. 1 and FIG. 6.

The following describes step S101, step S102, step S103, step S104 and step S105 in detail.

In step S101, a substrate SUB, an etch stop layer 110, an intermediate layer 120, a reaction layer 130, and a patterned etch mask layer 140 are sequentially formed.

Please refer to FIG. 1 and FIG. 2. FIG. 2 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. As shown in FIG. 2, a substrate SUB is provided in the present embodiment. An etch stop layer 110 is formed on the substrate SUB. An intermediate layer 120 is formed on the etch stop layer 110. A reaction layer 130 is formed on the intermediate layer 120. A patterned etch mask layer 140 is formed on the reaction layer 130.

In some implementations, the substrate SUB may be, for example, a silicon wafer.

In some embodiments, the substrate SUB may include a material such as a silicon-based material. However, any suitable material may be used.

In some embodiments, the substrate SUB may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to be limited to the method of forming the substrate SUB.

In some implementations, the etch stop layer 110 may be configured as a dielectric anti-reflective coating (DARC).

In some embodiments, the etch stop layer 110 may include a silicon-rich material such as silicon oxide (SiO ₂ ). However, any suitable material may be used.

In some embodiments, the etch stop layer 110 may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to be limited to the method of forming the etch stop layer 110.

In some embodiments, the middle layer 120 may include, for example, a carbon-rich material, such as silicon carbide (SiC) or titanium carbide (TiC). However, any suitable material may be used. In some embodiments, the content of carbon in the middle layer 120 is greater than or equal to 80%, but the present disclosure is not limited thereto.

In some embodiments, the intermediate layer 120 may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to limit the method for forming the intermediate layer 120.

In some implementations, the reaction layer 130 may be configured as a dielectric anti-reflective coating (DARC).

In some embodiments, the reaction layer 130 may include an oxygen-rich material such as silicon oxide (SiO ₂ ). However, any suitable material may be used.

In some embodiments, the reaction layer 130 can be formed by any suitable method, for example, CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to limit the method for forming the reaction layer 130.

In some embodiments, the patterned etch mask layer 140 may be a material such as photoresist (PR) or quartz glass. However, any suitable material may be used.

In some embodiments, the patterned etch mask layer 140 can be formed by any suitable method, for example, CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to limit the method of forming the patterned etch mask layer 140.

In step S102 , a plurality of hollow portions HP1 are formed on the patterned etching mask layer 140 .

Please refer to FIG. 1 and FIG. 3. FIG. 3 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to one embodiment of the present disclosure. As shown in FIG. 3, in this embodiment, a plurality of hollow portions HP1 are formed on a patterned etching mask layer 140. Specifically, the hollow portions HP1 penetrate the patterned etching mask layer 140, so that the reaction layer 130 is exposed. As shown in FIG. 3, in some embodiments, the patterned etching mask layer 140 is formed by performing an etching process EH1, so that a plurality of hollow portions HP1 are formed on the patterned etching mask layer 140. In some embodiments, each hollow portion HP1 formed by performing the etching process EH1 has a width W _HP1 . In some implementations, since each hollow portion HP1 has a width W _HP1 through the etching process EH1 in step S102 , each remaining portion of the patterned etching mask layer 140 correspondingly has a width W _L .

In some embodiments, the sum of the width _WL of each remaining portion of the patterned etching mask layer 140 and the width _WHP1 of each hollow portion HP1 is greater than or equal to 300 nanometers. In some embodiments, the width _WHP1 of each hollow portion HP1 is greater than or equal to 150 nanometers. When the width WHP1 of each hollow portion _HP1 is larger, the etching process EH1 is easier to etch down to a deeper layer to form a recess with a large enough aspect ratio, thereby increasing the signal of light reflection.

In some implementations, the etching process EH1 may be, for example, wet etching, dry etching, a lithography process or other suitable methods.

In some embodiments, the hollow portion HP1 may be formed by any suitable method, such as photolithography or a similar method. The present disclosure is not intended to limit the method for forming the hollow portion HP1.

In step S103 , a plurality of hollow portions HP2 are formed on the reaction layer 130 by patterning and etching the hollow portions HP1 of the mask layer 140 .

Please refer to FIG. 1 and FIG. 4. FIG. 4 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to one embodiment of the present disclosure. As shown in FIG. 4, in this embodiment, a plurality of hollow portions HP2 are formed on the reaction layer 130. Specifically, the hollow portion HP2 penetrates the reaction layer 130, so that the middle layer 120 is exposed. As shown in FIG. 4, in some embodiments, the reaction layer 130 is formed by performing an etching process EH2, and a plurality of hollow portions HP2 are formed on the reaction layer 130 through the plurality of hollow portions HP1 of the reaction layer 130. In some embodiments, each hollow portion HP2 formed by performing the etching process EH2 has a width W _HP2 .

In some implementations, the etching process EH2 may be, for example, wet etching, dry etching, a lithography process, or other suitable methods.

In some embodiments, the width W _HP2 of each hollow portion HP2 is equal to the width W _HP1 of each hollow portion HP1.

In step S104 , a plurality of hollow portions HP3 are formed on the middle layer 120 through the hollow portions HP2 of the reaction layer 130 .

Please refer to FIG. 1 and FIG. 5. FIG. 5 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to one embodiment of the present disclosure. As shown in FIG. 5, in this embodiment, a plurality of hollow portions HP3 are formed on the middle layer 120. Specifically, the hollow portion HP3 penetrates the middle layer 120, so that the etch stop layer 110 is exposed. As shown in FIG. 5, in some embodiments, the middle layer 120 is formed by performing an etching process EH3, and a plurality of hollow portions HP3 are formed on the middle layer 120 through a plurality of hollow portions HP2 of the reaction layer 130. In some embodiments, each hollow portion HP3 formed by performing the etching process EH3 has a width W _HP3 .

Please continue to refer to FIG. 5. In this embodiment, the etching process EH3 is performed to etch the middle layer 120 but not the etch stop layer 110. In some embodiments, the etch resistance of the reaction layer 130 is less than or equal to the etch resistance of the middle layer 120, and the etch resistance of the middle layer 120 is less than the etch resistance of the etch stop layer 110. This ensures that the etching process EH2 and the etching process EH3 can respectively and sequentially etch down the reaction layer 130 and the middle layer 120 without etching the etch stop layer 110. In more detail, in some embodiments where the material of the etch stop layer 110 is a silicon-rich material and the material of the reaction layer 130 is an oxygen-rich material, the etch stop layer 110 has a greater anti-etching capability than the reaction layer 130 because the oxygen-rich material reacts more easily with, for example, an etchant used in etching than the silicon-rich material.

In some embodiments, each hollow portion HP1, each hollow portion HP2 and each hollow portion HP3 are connected to each other. In some embodiments, each hollow portion HP1, each hollow portion HP2 and each hollow portion HP3 are aligned with each other.

In some implementations, the etching process EH3 may be, for example, wet etching, dry etching, a lithography process, or other suitable methods.

In some embodiments, the width W _HP3 of each hollow portion HP3 is equal to the width W _HP2 of each hollow portion HP2, and the width W _HP3 of each hollow portion HP3 is equal to the width W _HP1 of each hollow portion HP1.

In step S105, the patterned etching mask layer 140 is removed.

Please refer to FIG. 1 and FIG. 6. FIG. 6 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. As shown in FIG. 6, in this embodiment, the patterned etching mask layer 140 located on the reaction layer 130 is removed by performing an etching process EH4, thereby forming the semiconductor device 100. As shown in FIG. 6, by performing steps S101 to S105, a semiconductor device 100 including a substrate SUB, an etching stop layer 110, an intermediate layer 120 having a plurality of hollow portions HP3, and a reaction layer 130 having a plurality of hollow portions HP2 can be manufactured.

In some implementations, the semiconductor device 100 is configured as an alignment mark. The recessed hollow portion HP2 and the hollow portion HP3 are configured as a pattern of the alignment mark of the semiconductor device 100.

In one use scenario, a semiconductor machine (not shown) is to be aligned with respect to a semiconductor sample to be processed (not shown), wherein the semiconductor sample to be processed includes one or more semiconductor devices 100 (e.g., alignment marks). First, the semiconductor machine is configured to emit light toward the semiconductor device 100. Then, after reaching the semiconductor device 100, the light is reflected by the upper surface of the reaction layer 130 and the upper surface of the etch stop layer 110 exposed by the hollow portion HP2 and the hollow portion HP3, respectively, and then the reflected light with different light levels is received by the photo sensor of the semiconductor machine. Specifically, the greater the step difference between the alignment mark pattern (i.e., the hollow portion HP2 and the hollow portion HP3) and the upper surface of the semiconductor element 100, the greater the light level difference of the reflected light received by the above-mentioned photo sensor. Therefore, the photo sensor can more easily distinguish the alignment mark pattern, and thus more accurately determine whether the semiconductor machine is aligned with respect to the semiconductor sample to be processed.

In some embodiments, each hollow portion HP2 is substantially aligned with each hollow portion HP3 in a direction perpendicular to the upper surface of the substrate SUB.

In some implementations, the etching process EH4 may be, for example, wet etching, dry etching, a lithography process or other suitable methods.

In some embodiments, step S105 is performed after step S104, but the present disclosure is not limited thereto. In other embodiments, step S105 may also be performed between step S103 and step S104. In other words, step S105 may be performed after step S103 is performed, and then step S104 is performed. In one use scenario, the patterned etching mask layer 140, the reaction layer 130, and the intermediate layer 120 may be formed on the hollow portion HP1, the hollow portion HP2, and the hollow portion HP3, respectively, before the patterned etching mask layer 140 is removed. In another usage scenario, after the hollow portion HP1 and the hollow portion HP2 are formed on the patterned etching mask layer 140 and the reaction layer 130 respectively, the patterned etching mask layer 140 is removed first, and then the hollow portion HP3 is formed on the middle layer 120 through the hollow portion HP2 of the reaction layer 130 .

By executing the method M shown in FIG. 1 of the present disclosure, a semiconductor device 100 having a stronger reflected alignment signal can be formed.

From the above detailed description of the specific implementation of the present disclosure, it can be clearly seen that in the semiconductor device and the manufacturing method thereof disclosed in the present disclosure, since the sum of the width of the remaining portion of the reaction layer and the width of the hollow portion of the reaction layer is greater than or equal to 300 nanometers, and the width of the hollow portion of the reaction layer is greater than or equal to 150 nanometers, it can help reduce the difficulty of etching downward. In the semiconductor device and the manufacturing method thereof disclosed in the present disclosure, since the etch stop layer is disposed between the substrate and the intermediate layer, it can be ensured that the hollow portion penetrates the reaction layer and the intermediate layer but does not penetrate the etch stop layer, thereby properly controlling the depth of each hollow portion. The disclosed semiconductor device configured as an alignment mark and the manufacturing method thereof effectively improve the strength of the alignment signal by increasing the discontinuity between the hollow portion and the remaining portion.

Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

The above content summarizes the features of several implementation methods so that those familiar with this technology can better understand the state of this case. Those familiar with this technology should understand that without departing from the spirit and scope of this case, the above content can be easily used as a basis for designing or modifying other changes to implement the same purpose and/or achieve the same advantages of the implementation methods introduced in this article. The above content should be understood as an example of this disclosure, and its protection scope should be based on the scope of the patent application.

100: semiconductor device 110: etching stop layer 120: intermediate layer 130: reaction layer 140: patterned etching mask layer EH1, EH2, EH3, EH4: etching process HP1, HP2, HP3: hollow portion M: method S101, S102, S103, S104, S105: step SUB: substrate W _HP1 , W _HP2 , W _HP3 , W _L : width

In order to make the above and other purposes, features, advantages and implementation methods of the present disclosure more clearly understandable, the attached drawings are described as follows: FIG. 1 is a flow chart showing a method for manufacturing a semiconductor element according to an implementation method of the present disclosure. FIG. 2 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor element according to an implementation method of the present disclosure. FIG. 3 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor element according to an implementation method of the present disclosure. FIG. 4 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor element according to an implementation method of the present disclosure. FIG. 5 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor element according to an implementation method of the present disclosure. FIG. 6 is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor element according to an implementation method of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100:Semiconductor components

110: Etch stop layer

120: Middle layer

130: Reaction layer

EH4: Etching process

HP2, HP3: hollow part

SUB: Substrate

W _HP3 ,W _L : Width

Claims (10)

A semiconductor device comprises: a substrate; an etch stop layer disposed on the substrate; a reaction layer disposed above the etch stop layer and having a plurality of first hollow portions; and an intermediate layer disposed between the etch stop layer and the reaction layer and having a plurality of second hollow portions, and the first hollow portions are respectively connected to the second hollow portions located directly below them, wherein each of the first hollow portions has a first width, each of a remaining portion of the reaction layer has a second width, and wherein the second hollow portions penetrate the intermediate layer and expose the etch stop layer. A semiconductor device as described in claim 1, wherein the second width is greater than or equal to 150 nanometers. A semiconductor device as described in claim 1, wherein each of the second hollow portions has a third width, and the third width is the same as the second width. A semiconductor element as described in claim 3, wherein the second hollow portions are respectively aligned with the first hollow portions substantially in a direction perpendicular to an upper surface of the substrate. A semiconductor device as described in claim 1, wherein an anti-etching capability of the reaction layer is less than or equal to an anti-etching capability of the intermediate layer, and the anti-etching capability of the intermediate layer is less than an anti-etching capability of the etch stop layer. A semiconductor device as described in claim 1, wherein the etch stop layer and the reaction layer are dielectric anti-reflective coatings. A method for manufacturing a semiconductor element, comprising: Sequentially forming a substrate, an etching stop layer, an intermediate layer, a reaction layer, and a patterned etching mask layer; Forming a plurality of first hollow portions on the patterned etching mask layer, wherein each of the first hollow portions of the patterned etching mask layer has a first width, each of a remaining portion of the patterned etching mask layer has a second width, and a sum of the first width and the second width is greater than or equal to 300 nanometers; Forming a plurality of second hollow portions on the reaction layer by means of the first hollow portions of the patterned etching mask layer; Forming a plurality of third hollow portions on the intermediate layer by means of the second hollow portions of the reactive layer, wherein the third hollow portions penetrate the intermediate layer and expose the etching stop layer; and removing the patterned etching mask layer. The method of claim 7, wherein the second width is greater than or equal to 150 nanometers. A method as described in claim 7, wherein the step of removing the patterned etching mask layer is performed after the step of forming the second hollow portions on the reaction layer through the first hollow portions of the patterned etching mask layer and before the step of forming the third hollow portions on the intermediate layer through the second hollow portions of the reaction layer. A method as described in claim 7, wherein the step of removing the patterned etching mask layer is performed after the step of forming the third hollow portions on the intermediate layer through the second hollow portions of the reactive layer.

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