TWI876641B - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

The implementation method of the present invention provides a semiconductor memory element and a manufacturing method thereof that can improve the reliability of memory cells. The semiconductor memory element of the present implementation method has a laminate, a semiconductor layer, a first insulating film, a second insulating film, a third insulating film and a fourth insulating film. The laminate is formed by alternately laminating insulating layers and conductive layers along a first direction. The semiconductor layer is arranged in the laminate along the first direction. The first insulating film is arranged between the laminate and the semiconductor layer. The second insulating film is arranged between the laminate and the first insulating film. The third insulating film is disposed between the laminate and the second insulating film. The first portion of the fourth insulating film is disposed between the conductive layer and the third insulating film, and the second portion of the fourth insulating film is disposed between the conductive layer and the insulating layer. The average concentration of deuterium in the first portion is higher than the average concentration of deuterium in the third insulating film. The ratio of the deuterium concentration to the hydrogen concentration in the first portion is lower than the ratio of the deuterium concentration to the hydrogen concentration in the third insulating film.

Description

Semiconductor memory device and manufacturing method thereof

The present embodiment relates to a semiconductor memory device and a method for manufacturing the same.

As a semiconductor memory device, a NAND (Not AND) flash memory is known in which memory cells are arranged three-dimensionally. In the NAND flash memory, a memory hole penetrating the laminated body is provided in a laminated body formed by alternately stacking a plurality of electrode layers and insulating layers. A blocking insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer (channel layer) are provided in the memory hole to form a memory string in which a plurality of memory cells are connected in series. Data is stored in the memory cell by controlling the amount of charge retained in the charge storage film.

The problem to be solved by the present invention is to provide a semiconductor memory element and a manufacturing method thereof which can improve the reliability of a memory cell.

The semiconductor memory element of the present embodiment comprises a laminate, a semiconductor layer, a first insulating film, a second insulating film, a third insulating film, and a fourth insulating film. The laminate is formed by alternately laminating insulating layers and conductive layers along a first direction. The semiconductor layer is arranged in the laminate along the first direction. The first insulating film is arranged between the laminate and the semiconductor layer along the first direction. The second insulating film is arranged between the laminate and the first insulating film along the first direction. The third insulating film is arranged between the laminate and the second insulating film along the first direction. The fourth insulating film has a first portion and a second portion. The first portion is disposed between the conductive layer and the third insulating film, and the second portion is disposed between the conductive layer and the insulating layer along a second direction intersecting the first direction and connected to the first portion. The average concentration of deuterium in the first portion is higher than the average concentration of deuterium in the third insulating film. The ratio of the deuterium concentration to the hydrogen concentration in the first portion is lower than the ratio of the deuterium concentration to the hydrogen concentration in the third insulating film.

Hereinafter, the embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. The drawings are schematic diagrams or conceptual diagrams, and the ratios of the various parts may not be the same as the actual objects. In the specification and drawings, the same symbols are used for the elements that have been described above with respect to the drawings that have appeared, and the detailed description is appropriately omitted.

(First Embodiment) Fig. 1 is a perspective view showing the structure of a semiconductor memory device according to a first embodiment. The semiconductor memory device in Fig. 1 is, for example, a three-dimensional NAND memory.

The semiconductor memory device of FIG1 includes a core insulating film 1, a channel semiconductor layer 2, a tunnel insulating film 3, a charge storage film 4, a blocking insulating film 5, and an electrode layer 6. The blocking insulating film 5 includes an insulating film 5a and an insulating film 5b. The electrode layer 6 includes a barrier metal layer 6a and an electrode material layer 6b. The tunnel insulating film 3, the charge storage film 4, and the blocking insulating film 5 are also referred to as cell stacking films.

The semiconductor memory element of the present embodiment is a semiconductor memory element that alternately stacks a plurality of electrode layers and a plurality of insulating layers on a substrate, and a memory hole H1 is provided in the electrode layers and the insulating layers. FIG1 shows one electrode layer 6 among the electrode layers. The electrode layers function as word lines of a NAND memory, for example. FIG1 shows the X direction and the Y direction that are parallel to the surface of the substrate and perpendicular to each other, and the Z direction that is perpendicular to the surface of the substrate. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not be consistent with the direction of gravity.

The core insulating film 1, the channel semiconductor layer 2, the tunnel insulating film 3, the charge storage film 4, and the insulating film 5a are formed in the memory hole H1 to constitute the memory cell of the NAND memory. The insulating film 5a is formed on the surface of the electrode layer and the insulating layer in the memory hole H1, and the charge storage film 4 is formed on the surface of the insulating film 5a. The charge storage film 4 can store charges between the outer side surface and the inner side surface. The tunnel insulating film 3 is formed on the surface of the charge storage film 4, and the channel semiconductor layer 2 is formed on the surface of the tunnel insulating film 3. The channel semiconductor layer 2 functions as a channel of the memory cell. The core insulating film 1 is formed in the channel semiconductor layer 2.

The insulating film 5a is, for example, a SiO film (silicon oxide film). The charge storage film 4 is, for example, a SiN film (silicon nitride film). The tunnel insulating film 3 is, for example, a SiON film (silicon oxynitride film). The channel semiconductor layer 2 is, for example, a polysilicon layer. The core insulating film 1 is, for example, a silicon oxide film.

The insulating film 5b, the barrier metal layer 6a, and the electrode material layer 6b are formed between the adjacent insulating layers, and are sequentially formed on the lower surface of the upper insulating layer, the upper surface of the lower insulating layer, and the side surface of the insulating film 5a. The insulating film 5b is, for example, a metal insulating film such as aluminum oxide. The barrier metal layer 6a is, for example, a titanium nitride film. The electrode material layer 6b is, for example, a W (tungsten) layer.

2 to 5 and FIG. 10 are cross-sectional views showing a method for manufacturing a semiconductor memory device according to the first embodiment.

First, an insulating film 12 is formed on a substrate 11, and a plurality of sacrificial layers 13 and a plurality of insulating layers 14 are alternately formed on the insulating film 12 (FIG. 2). As a result, a laminate film S1 is formed on the insulating film 12, which alternately includes a plurality of sacrificial layers 13 and a plurality of insulating layers 14. The substrate 11 is, for example, a semiconductor substrate such as a silicon substrate. The insulating film 12 is, for example, a silicon oxide film (SiO). The sacrificial layer 13 is, for example, a silicon nitride film (SiN), and the insulating layer 14 is, for example, a silicon oxide film (SiO).

Next, a memory hole H1 (FIG. 2) is formed through the stacked film S1 and the insulating film 12. As a result, the upper surface of the layer disposed between the substrate 11 and the insulating film 12 is exposed in the memory hole H1. The details of this layer will be described below.

Next, the insulating film 5a, the charge storage film 4, the tunnel insulating film 3, and a portion of the channel semiconductor layer 2 are sequentially formed in the memory hole H1 (FIG. 3). Next, the insulating film 5a, the charge storage film 4, the tunnel insulating film 3, and the portion of the channel semiconductor layer 2 are removed from the bottom of the memory hole H1 by etching, and then the remaining portion of the channel semiconductor layer 2 and the core insulating film 1 are sequentially formed in the memory hole H1 (FIG. 3). As a result, the insulating film 5a, the charge storage film 4, the tunnel insulating film 3, the channel semiconductor layer 2, and the core insulating film 1 are sequentially formed on the side surfaces of the laminate film S1 and the insulating film 12 in the memory hole H1.

Next, a slit (not shown) is formed in the laminate film S1, and the sacrificial layer 13 is removed by a chemical solution such as phosphoric acid through the slit. As a result, a plurality of cavities H2 are formed between the insulating layers 14 (FIG. 4).

Next, an insulating film 5b including aluminum oxide is formed on the surface of the insulating layer 14 and the insulating film 5a in the cavities H2 (FIG. 5). As a result, a blocking insulating film 5 including the insulating film 5a and the insulating film 5b is formed.

Next, as shown in FIG6 , free radical oxidation (free radical reforming) is performed. The free radical oxidation is performed using OH ^* or OD ^* , oxygen free radicals (O ^* ) in a heating furnace or RTP (Rapid Thermal Processing). The heat treatment environment is in the range of 800°C to 1100°C. In addition, oxygen free radicals (O ^* ) can also be generated from oxygen (O ₂ ) gas using a plasma generating mechanism.

The radical oxidation is performed, for example, at 900° C. for 30 seconds.

By radical oxidation, many trap levels (capture sites) T are formed in the insulating films 5a and 5b. In addition, in FIG6 , the trap levels T included in the charge storage film 4 and the tunnel insulating film 3 are omitted.

Next, RTP (Rapid Thermal Processing) is performed using deuterium (D ₂ ) gas and heavy water (D ₂ O) under a heat load condition of, for example, 1000° C. or higher. In this way, the insulating film 5 b including aluminum oxide (AlO) is crystallized and the film quality is improved, and as shown in FIG7 , deuterium (D) is introduced into the stacked films, such as the blocking insulating film 5, the charge storage film 4, and the tunnel insulating film 3. FIG7 is a cross-sectional view showing the introduction of deuterium (D) into a cavity H2.

RTP using deuterium (D ₂ ) gas and heavy water (D ₂ O) is performed, for example, at 1035° C. and for about 0 to 10 seconds. In addition, heavy water (D ₂ O) is introduced into the RTP device in a liquid state.

Furthermore, RTP using heavy water (D ₂ O) instead of deuterium (D ₂ ) gas can also be performed. RTP using heavy water (D ₂ O) can also include argon (Ar) or nitrogen (N ₂ ) gas as a carrier gas. By using argon or nitrogen, it is not necessary to use expensive deuterium (D ₂ ) gas. On the other hand, since heavy water (D ₂ O) has a high efficiency in replacing protium (H) in the insulating film with deuterium (D), deuterium (D) can be sufficiently introduced into the insulating film even in a small amount. That is, a deuterium (D) introduction process with excellent productivity can be provided.

As shown in Fig. 7, the dangling bond of the trap energy level T formed in the step of Fig. 6 is terminated with deuterium (D). Therefore, more deuterium (D) can be introduced into the insulating films 5a and 5b.

FIG8 shows the concentration distribution in the depth direction after deuterium (D) is introduced. The horizontal axis represents the X-direction depth (depth) from the insulating film 5b containing AlO, that is, the X-direction distance. That is, it represents the depth direction distance of the insulating film 5b, the insulating film 5a containing SiO, the charge storage film 4 containing SiN, the tunnel insulating film 3 containing SiON, and the channel semiconductor layer 2 from the surface of the insulating film 5b containing AlO. The vertical axis represents the concentration of deuterium (D).

According to the first embodiment of FIG. 8 , deuterium (D) is mainly introduced into the charge storage film 4 including SiN and the tunnel insulating film 3 including SiON. Moreover, the average concentration of deuterium (D) in the cell layer membrane becomes lower in the order of charge storage film 4>tunnel insulating film 3>insulating film 5b>insulating film 5a. In other words, it becomes lower in the order of charge storage film 4, the interface between the charge storage film 4 and the tunnel insulating film 3, and the tunnel insulating film 3. Here, the so-called average concentration of each film refers to the value obtained by integrating the concentration distribution along the depth direction of the corresponding film and dividing the integrated value by the thickness of the corresponding film (thickness in the X direction). Furthermore, the boundary between the charge storage film 4 including SiN and the tunnel insulating film 3 including SiON can be determined based on the SiN intensity and O intensity analysis curve in SIMS (Secondary Ion Mass Spectrometry) analysis.

As described above, the average concentration of deuterium (D) in the insulating film 5b is higher than the average concentration of deuterium (D) in the insulating film 5a.

FIG9 shows the distribution of the concentration ratio of deuterium (D) concentration to protium (H) concentration. The horizontal axis represents the X-direction depth (depth), i.e., the X-direction distance, from the insulating film 5b containing AlO, similarly to the horizontal axis of the graph shown in FIG8. The vertical axis represents the concentration ratio of deuterium (D) concentration to hydrogen (H) concentration (D/H concentration ratio).

As can be seen from FIG9, the distribution trend of the D/H concentration ratio from the charge storage film 4 to the channel semiconductor layer 2 is similar to the distribution trend of the deuterium (D) concentration shown in FIG8. On the other hand, the D/H concentration ratio in the insulating film 5b is lower than the D/H concentration ratio in the insulating film 5a. The D/H concentration ratio in the insulating film 5a may be greater than 100.

By referring to the steps described in FIG. 6 and FIG. 7 , the deuterium (D) concentration and the D/H concentration ratio in the insulating films 5a and 5b can be increased. In this way, more dangling bonds can be terminated with deuterium (D) in the insulating films 5a and 5b. In addition, the protium (H) termination with low reliability can be reduced. As a result, the charge can be suppressed from escaping from the charge storage film 4 to the blocking insulating film 5. Therefore, the data retention characteristics and cycle resistance can be improved, and the reliability of the memory cell can be improved.

As shown in FIG. 9 , the D/H concentration ratio in at least one of the portion of the insulating film 5b along the insulating film 5a and the insulating film 5a is greater than 1. More preferably, the D/H concentration ratio in at least one of the portion of the insulating film 5b along the insulating film 5a and the insulating film 5a is greater than 10. When the hanging bond that becomes a defect in the insulating film is terminated with protium (H), hydrogen (H) is separated due to electrical stress, and the charge retention characteristics as a memory element and the resistance as an insulating film are deteriorated due to the defect. When the dangling bonds in the insulating film are terminated with deuterium (D), deuterium (D) is stable and not easy to be separated even if electrical stress is applied. As a result, the dangling bonds that have become defects are stably terminated with deuterium (D), and the charge retention characteristics of the memory element and the tolerance of the insulating film are significantly improved. By not only introducing deuterium (D) but also reducing protium (H) to make the D/H concentration ratio above 10, the reliability of the memory cell can be significantly improved. When the D/H concentration ratio is above 10, the ratio of deuterium (D) termination in the dangling bonds D/(D+H) exceeds 10/(10+1)=90.9%. By increasing the deuterium (D) capping ratio in the insulating film to more than 90.9%, the characteristics of semiconductor devices can be significantly improved.

A high-k insulating film (High-k film) is used for the portion of the insulating film 5b along the insulating film 5a. Generally speaking, by using an insulating film with a higher dielectric constant k as a gate insulating film, the gate capacitance can be increased in the case of a thin film, and the reliability of the semiconductor can be improved. On the other hand, generally speaking, if the material has a higher dielectric constant k, there is a tendency for the band gap energy to decrease. Therefore, the charge accumulated by the charge storage film 4 is easy to leak through the portion of the insulating film 5b along the insulating film 5a and the insulating film 5a, resulting in the charge retention characteristics being easily deteriorated. Therefore, if the D/H concentration ratio in the High-k insulating film is set to 1 or more, the characteristics of the semiconductor device are improved. Preferably, if the D/H concentration ratio is set to 10 or more (deuterium termination ratio D/(D+H) exceeds 90.9%), the characteristics of the semiconductor device are significantly improved. In the insulating film 5b, as the High-k insulating film, AlO having a dielectric constant of 8 or more is preferred, and _ZrO2 , _Ta2O5 , _TiO2 , _HfO2 , _HfSiO4 , _{La2O3 , Y2O3} , and _ZrO2 may also be used _. By using such a high dielectric insulating film having a D/H concentration _ratio of 10 or more and a dielectric constant of 8 or more, the characteristics of the semiconductor device can be improved.

As described above, by making the D/H concentration ratio of the portion of the insulating film 5b along the insulating film 5a and the insulating film 5a to be 10 or more, the average D/H concentration ratio in the cell functional insulating film including the portion of the insulating film 5b along the insulating film 5a, the insulating film 5a, the charge storage film 4, and the tunnel insulating film 3 can be made to be 10 or more. The average deuterium (D) termination ratio (D/(D+H)) in the cell functional insulating film can exceed 90.9%. By improving the overall average D/H concentration ratio and deuterium (D) termination ratio in the cell functional insulating film in this way, the characteristics of the semiconductor memory element can be improved.

The comparative examples shown in FIG. 8 and FIG. 9 include examples of a plurality of manufacturing methods.

The first comparative example (E1) shows an example of forming an insulating film 5b (refer to FIG. 5), performing RTP of nitrogen (N ₂ ) annealing, performing radical oxidation, and performing annealing using deuterium (D ₂ ) gas. The RTP of nitrogen (N ₂ ) annealing is performed, for example, at 1035°C and for 10 seconds. The RTP of nitrogen (N ₂ ) annealing is performed, for example, for crystallization of the insulating film 5b. The annealing using deuterium (D ₂ ) gas is performed, for example, at 800°C and for 60 minutes. The annealing using deuterium (D ₂ ) gas is performed, for example, for the purpose of introducing deuterium (D).

In the second comparative example (E2), after the annealing using deuterium (D ₂ ) gas in the first comparative example, reactivation annealing is performed. The reactivation annealing is, for example, a spike annealing at 1015° C. The annealing using deuterium (D ₂ ) gas is performed in a temperature range that deactivates the dopant. The reactivation annealing is performed, for example, to reactivate the dopant deactivated by the annealing using deuterium (D ₂ ) gas.

As shown in Fig. 8, in the first embodiment, the deuterium (D) concentration in the insulating films 5a and 5b can be increased compared to the first and second comparative examples. As shown in Fig. 9, in the first embodiment, the D/H concentration ratio in the insulating films 5a and 5b can be increased compared to the first and second comparative examples.

In the first comparative example and the second comparative example, free radical oxidation is performed after the insulating film 5b is crystallized. When the insulating film 5b is crystallized, it is possible that it is difficult to form the trap energy level T in the insulating film 5b. In addition, in the first comparative example and the second comparative example, deuterium (D) is introduced after the insulating film 5b is crystallized. The insulating film 5b before crystallization is an amorphous form containing many dangling bonds. Since the number of dangling bonds in the insulating film 5b after crystallization is greatly reduced, there are fewer dangling bonds terminated with deuterium (D), and it is possible that it is difficult to terminate the dangling bonds with deuterium (D).

In the first comparative example and the second comparative example, deuterium (D) was introduced without using heavy water (D ₂ O).

In addition, in the first comparative example and the second comparative example, reactivation annealing was performed.

In contrast, in the first embodiment, the insulating film 5b is crystallized after the radical oxidation. It is believed that more trap energy levels T are formed in the insulating film 5a before crystallization, and more trap energy levels T remain after the crystallization of the insulating film 5b. In addition, in the first embodiment, the crystallization of the insulating film 5b and the introduction of deuterium (D) are performed at about the same time. In this way, the introduction of deuterium (D) is performed in a state where dangling bonds of the insulating film 5b remain. As a result, the dangling bonds can be easily terminated with deuterium (D).

In the first embodiment, deuterium (D) is introduced using heavy water (D ₂ O). Compared with relatively stable deuterium (D ₂ ), heavy water (D ₂ O) is more easily separated into free radicals and dangling bonds are terminated with deuterium (D) atoms. Moreover, heavy water (D ₂ O) is an oxidizing species. Since the OD bond is stable, compared with replacing the Si-H bond with the Si-D bond, it is more efficient to replace protium (H) with deuterium (D) by forming the Si-OD bond in the oxidation process. Therefore, by using heavy water (D ₂ O), the concentration of deuterium (D) can be easily increased. In addition, for a High-k insulating film such as AlO, the protium in the insulating films 5a and 5b can be easily replaced by deuterium by replacing the OH bonds with OD bonds. Before the heavy water (D ₂ O) treatment, OH ^* can be introduced into the High-k insulating film by free radical oxidation, and the OH bonds introduced by free radicals can be further replaced by OD bonds. In this way, a high dielectric insulating film with a D/H concentration ratio of 10 or more can be obtained.

Furthermore, in the first embodiment, the introduction of deuterium (D) is performed by RTP substantially simultaneously with the crystallization of the insulating film 5b. Thus, annealing using deuterium ( _D2 ) gas is not required. Therefore, the dopant is not deactivated, and reactivation annealing is not required.

In the third comparative example (E3), for example, free radical oxidation is performed after RTP using deuterium (D ₂ ) gas and heavy water (D ₂ O), that is, the step shown in FIG. 6 is performed after the step shown in FIG. 7 .

As shown in Fig. 8, in the first embodiment, the deuterium (D) concentration in the insulating films 5a and 5b can be increased compared to the third comparative example. As shown in Fig. 9, in the first embodiment, the D/H concentration ratio in the insulating films 5a and 5b can be increased compared to the third comparative example.

In the third comparative example, similarly to the first and second comparative examples, radical oxidation is performed after crystallization of the insulating film 5b.

In contrast, in the first embodiment, the insulating film 5b is crystallized after radical oxidation. It is considered that more trap energy levels T are formed in the insulating film 5a before crystallization, and more trap energy levels T remain after crystallization of the insulating film 5b.

In the first embodiment, a method of crystallizing the insulating film 5b after radical oxidation is described, but the substitution from protium to deuterium in crystallization and radical oxidation is a process with interaction, and it takes a lot of effort to combine process parameters (temperature, time, pressure, oxidation amount, heating/cooling rate, sequence of crystallization and radical oxidation and other annealing) to improve the reliability degradation of the device. On the other hand, by focusing on the D/H concentration ratio in the insulating films 5a and 5b, selecting a process that obtains a D/H concentration ratio of more than 10 in the portion of the insulating film 5b along the insulating film 5a, it is possible to suppress the reliability degradation of the device performance.

As described above, as in the present embodiment, a structure can be formed in which the interfaces of the insulating film 5a, the insulating film 5b, the charge storage film 4 and the tunnel insulating film 3 are terminated with deuterium (D). If the write/erase operation is repeated, defects are generated in the charge storage film 4 and the tunnel insulating film 3, and part of the charge accumulated in the charge storage film 4 escapes from the defects. This will cause data loss. The defects in the charge storage film 4 and the tunnel insulating film 3 are believed to be generated by the following situation, that is, the hydrogen (H) introduced intentionally or unintentionally when the memory cell is formed is released due to the electrical stress caused by the write/erase operation. In this embodiment, by further increasing the D/H concentration ratio in the insulating film 5a to more than 10, the hydrogen (H) component in the insulating film 5a that is separated due to the electrical stress during the write/erase operation can be reduced. As a result, it is possible to suppress the escape of part of the charge to the electrode layer 6, thereby improving the device characteristics.

Regarding SiN film and SiON film, when deuterium (D) is introduced into the film, the N-H bond in the film is replaced by an N-D bond. Compared with the N-H bond, the N-D bond has a much stronger resistance to electrical stress. That is, by replacing the portion that becomes a bond defect with deuterium (D), a strong bond that resists electrical stress can be formed. Therefore, as long as the N-H bonds in the charge storage film 4 and the tunnel insulating film 3 can be reduced and the N-D bonds can be increased, the degradation of the charge storage film 4 and the tunnel insulating film 3 due to the write/erase operation can be suppressed. In addition, it is possible to suppress erroneous writing during writing or reading. Furthermore, even when repeated write and erase operations are performed, the effect of suppressing reliability degradation can be obtained. Therefore, a semiconductor memory device capable of suppressing reliability degradation of a memory cell can be obtained.

Furthermore, in this embodiment, a structure using deuterium (D) termination can be formed at the interface between the charge storage film 4 and the insulating film 5a and the interface between the insulating film 5a and the insulating film 5b. There is a possibility that the charge accumulated in the charge storage film 4 also escapes to the insulating film 5a side. By actively introducing deuterium (D) into the insulating film 5a and the insulating film 5b, the charge escape in the charge storage film 4 can be further suppressed. In this way, the data retention characteristics and cycle resistance can be improved, thereby improving the reliability of the memory cell.

Furthermore, in this embodiment, the deuterium (D) concentration in the insulating films 5a and 5b is increased and the protium (H) concentration is decreased. This can improve the data retention characteristics and cycle resistance, thereby improving the reliability of the memory cell. Although the deuterium concentration in the charge storage film 4 and the tunnel insulating film 3 in the first, second, and third comparative examples is the same as that in the embodiment, the reliability of the memory cell is greatly improved in the first embodiment. When the memory cell reliability of the first comparison example is used as the standard, the memory cell reliability index of the second comparison example increases by 40, and stays at 280 in the third comparison example. In contrast, the memory cell reliability index in the first implementation method increases by 1080.

As a variation of the present embodiment, a process using deuterium (D ₂ ) gas and heavy water (D ₂ O) can be used as reactivation annealing. By performing a spike annealing process in a deuterium (D ₂ ) gas and heavy water (D ₂ O) environment, for example, at a treatment temperature of 1000° C. or higher and for a short retention time (for example, within 5 seconds), the D/H concentration ratio in the insulating films 5a and 5b can be increased. Furthermore, the spike annealing process is an annealing process in which the rate of temperature rise/fall is increased and the retention time at the peak temperature is reduced in RTP. Subsequent process treatments may reduce deuterium (D) termination. By placing the process using deuterium (D ₂ ) gas and heavy water (D ₂ O) at the end of a manufacturing step with a high heat load, a higher D/H concentration ratio can be maintained. For example, the process temperature using deuterium (D ₂ ) gas and heavy water (D ₂ O) is higher than all subsequent temperature processes in the manufacturing step. By performing such a process, a device with an improved D/H concentration ratio can be obtained, further suppressing reliability degradation. The reliability index of the memory cell in this variation is improved by 1240.

In this way, after RTP is performed using deuterium (D ₂ ) gas and heavy water (D ₂ O), a barrier metal layer 6a and an electrode material layer 6b are sequentially formed on the surface of the insulating film 5b in the cavities H2 using a conventional process ( FIG. 10 ). As a result, an electrode layer 6 including a barrier metal layer 6a and an electrode material layer 6b is formed in each cavity H2, and a laminate film S2 including a plurality of electrode layers 6 and a plurality of insulating layers 14 alternately is formed on the insulating film 12. The process of removing the sacrificial layer 13 to form the insulating film 5b, the barrier metal layer 6a, and the electrode material layer 6b is called a replacement process.

In this way, the semiconductor memory device of this embodiment is manufactured (FIG. 10). FIG. 1 shows a part of the semiconductor memory device shown in FIG.

As described above, according to this embodiment, a semiconductor memory element capable of suppressing reliability degradation of a memory cell can be obtained.

(Second Embodiment) A semiconductor memory device according to a second embodiment will be described with reference to Fig. 11 to Fig. 20. Fig. 11 to Fig. 20 are cross-sectional views showing a method for manufacturing a semiconductor memory device according to the second embodiment.

FIG11 shows a cross section after a slit (H5) is formed in the laminate film S1 in the step shown in FIG4 and before the sacrificial layer 13 is removed in the step shown in FIG4. FIG11 shows the insulating film 5a, the charge storage film 4, the tunnel insulating film 3, the channel semiconductor layer 2, and the core insulating film 1 formed in sequence in the memory hole H1. The insulating film 5a, the charge storage film 4, and the tunnel insulating film 3 in FIG11 are not removed from the bottom of the memory hole H1, but are retained. Such a structure is adopted, for example, when the laminate film S1 is thick.

FIG11 also shows an insulating film 21, a metal layer 22a, a lower semiconductor layer 22b, an insulating film 23, a semiconductor layer 24, an insulating film 25, an upper semiconductor layer 22c, an insulating film 26, and a gate layer 27 formed in sequence above the substrate 11. The insulating film 12 of the present embodiment is formed by interposing the insulating films or layers above the substrate 11 in the step of FIG2. The insulating film 21 is, for example, a silicon oxide film. The metal layer 22a is, for example, a W layer. The lower semiconductor layer 22b is, for example, a polysilicon layer. The insulating film 23 is, for example, a silicon oxide film. The semiconductor layer 24 is, for example, a polycrystalline silicon layer. The insulating film 25 is, for example, a silicon oxide film. The upper semiconductor layer 22c is, for example, a polycrystalline silicon layer. The insulating film 26 is, for example, a silicon oxide film. The gate layer 27 is, for example, a polycrystalline silicon layer. The metal layer 22a, the lower semiconductor layer 22b, and the upper semiconductor layer 22c constitute the source line 22. That is, the channel semiconductor layer 2 is electrically connected to the source line 22. Here, the so-called electrical connection between A and B means that A and B can be directly connected or indirectly connected via a conductor.

The memory hole H1 of the present embodiment is formed in the step of Fig. 2 by penetrating the stacking film S1, the insulating film 12, the gate layer 27, the insulating film 26, the upper semiconductor layer 22c, the insulating film 25, the semiconductor layer 24, and the insulating film 23, and reaching the lower semiconductor layer 22b. The insulating film 5a, the charge storage film 4, the tunnel insulating film 3, the channel semiconductor layer 2, and the core insulating film 1 are sequentially formed in the memory hole H1 in the step of Fig. 3.

In the step shown in FIG. 11 , a slit H5 is formed so as to penetrate the multilayer film S1, the insulating film 12, the gate layer 27, the insulating film 26, the upper semiconductor layer 22c, and the insulating film 25 and reach the semiconductor layer 24. The slit H5 is an example of the first recess. In the step of FIG. 11 , an insulating film 28 is also formed on the side and bottom surfaces of the slit H5. The insulating film 28 is, for example, a SiN film.

Next, the insulating film 28 is removed from the bottom of the slit H5 by etching, and the semiconductor layer 24 is removed by wet etching using the slit H5 (FIG. 12). As a result, a cavity H6 is formed between the insulating film 25 and the insulating film 23. Next, the insulating film 25 and the insulating film 23 are removed by CDE (Chemical Dry Etching) using the slit H5 and the cavity H6, and the insulating film 5a, the charge storage film 4, and the tunnel insulating film 3 exposed in the cavity H6 are processed (FIG. 10). As a result, the volume of the cavity H6 is enlarged, and the side surface of the channel semiconductor layer 2 is exposed in the cavity H6.

Next, an intermediate semiconductor layer 22d is formed in the cavity H6 (FIG. 13). As a result, the intermediate semiconductor layer 22d is formed between the lower semiconductor layer 22b and the upper semiconductor layer 22c, thereby forming a source line 22 that includes the metal layer 22a, the lower semiconductor layer 22b, the intermediate semiconductor layer 22d, and the upper semiconductor layer 22c in sequence. The intermediate semiconductor layer 22d is, for example, a polysilicon layer doped with phosphorus (P). The source line 22 is electrically connected to the channel semiconductor layer 2 using the intermediate semiconductor layer 22d.

Next, the insulating film 28 is removed from the slit H5 (FIG. 14). As a result, the side surface of the laminate film S1 is exposed in the slit H5.

Next, water vapor (H ₂ O) is supplied into the slit H5 to perform oxidation treatment ( FIG. 15 ). As a result, the surfaces of the upper semiconductor layer 22c, the middle semiconductor layer 22d, and the gate layer 27 exposed in the slit H5 are oxidized by the water vapor, and as shown in FIG. 16 , an oxide film 22e (e.g., SiO film) is formed by oxidation of the surface of the upper semiconductor layer 22c, an oxide film 22f (e.g., SiO film) is formed by oxidation of the surface of the middle semiconductor layer 22d, and an oxide film 27a (e.g., SiO film) is formed by oxidation of the surface of the gate layer 27.

Next, the sacrificial layer 13 is removed by using a solution such as phosphoric acid using the slit H5. As a result, a plurality of cavities H2 are formed between the insulating layers 14 (FIG. 17). Furthermore, the upper semiconductor layer 22c, the middle semiconductor layer 22d, and the gate layer 27 are covered by the oxide films 22e, 22f, and 27a, and therefore are not removed in the step of FIG. 17.

Next, an insulating film 5b including AlO is formed on the surface of the insulating layer 14 and the insulating film 5a in the cavity H2 (FIG. 18). Then, by performing the heat treatment described in the first embodiment, deuterium (D) is introduced into the insulating film 5b including AlO, the insulating film 5a including SiO, the charge storage film 4 including SiN, and the tunnel insulating film 3 including SiON (FIG. 19).

Next, a barrier metal layer 6a and an electrode material layer 6b are sequentially formed on the surface of the insulating film 5b in the cavity H2 (FIG. 20). As a result, a blocking insulating film 5 including the insulating film 5a and the insulating film 5b is formed. Furthermore, an electrode layer 6 including the barrier metal layer 6a and the electrode material layer 6b is formed in each cavity H2, and a laminate film S2 alternately including a plurality of electrode layers 6 and a plurality of insulating layers 14 is formed on the insulating film 12. Next, an insulating film 29 is formed in the slit H5 (FIG. 20). The insulating film 29 is, for example, a silicon oxide film.

In this way, a semiconductor memory device of the second embodiment is manufactured (FIG. 20). FIG1 shows a part of the semiconductor memory device shown in FIG20. The semiconductor memory device of the second embodiment can suppress the reliability degradation of the memory cell as in the first embodiment.

Several embodiments of the present invention are described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and can be omitted, replaced, and changed in various ways without departing from the scope of the invention. These embodiments or their variations are included in the scope or subject matter of the invention, and are also included in the invention described in the scope of the patent application and its equivalent. [References to related applications]

This application claims priority from Japanese Patent Application No. 2022-203628 (filing date: December 20, 2022). This application incorporates all the contents of the basic application by reference.

1: Core insulating film 2: Channel semiconductor layer 2a: Semiconductor layer 2b: Semiconductor layer 3: Tunnel insulating film 4: Charge storage film 5: Block insulating film 5a: Insulating film 5b: Insulating film 6: Electrode layer 6a: Barrier metal layer 6b: Electrode material layer 11: Substrate 12: Insulating film 13: Sacrificial layer 14: Insulating layer 15: Insulating film 16: Electrode layer 16a: Oxide film 17: Connection layer 7a: Oxide film 18: Insulating film 21: Insulating film 22: Source line 22a: Metal layer 22b: Lower semiconductor layer 22c: Upper semiconductor layer 22d: Intermediate semiconductor layer 22e: Oxide film 22f: Oxide film 23: Insulating film 24: Semiconductor layer 25: Insulating film 26: Insulating film 27: Gate layer 27a: Oxide film 28: Insulating film 29: Insulating film H1: Memory hole H2: Cavity H5: Slit H6: Cavity S1: Laminated film S2: Laminated film T: Trap energy level (trapping site)

FIG1 is a perspective view showing the structure of a semiconductor memory element of the first embodiment. FIG2 is a cross-sectional view showing the method for manufacturing a semiconductor memory element of the first embodiment. FIG3 is a cross-sectional view showing the method for manufacturing a semiconductor memory element of the first embodiment. FIG4 is a cross-sectional view showing the method for manufacturing a semiconductor memory element of the first embodiment. FIG5 is a cross-sectional view showing the method for manufacturing a semiconductor memory element of the first embodiment. FIG6 is a cross-sectional view illustrating the heat treatment in the method for manufacturing a semiconductor memory element of the first embodiment. FIG7 is a cross-sectional view illustrating the heat treatment in the method for manufacturing a semiconductor memory element of the first embodiment. FIG8 is a graph showing the distribution of deuterium introduced into a cell stacking film by the heat treatment shown in FIG7. Fig. 9 is a graph showing the distribution of the concentration ratio of the deuterium concentration to the hydrogen concentration in the cell stacking layer. Fig. 10 is a cross-sectional view showing the method for manufacturing a semiconductor memory element according to the first embodiment. Fig. 11 is a cross-sectional view showing the method for manufacturing a semiconductor memory element according to the second embodiment. Fig. 12 is a cross-sectional view showing the method for manufacturing a semiconductor memory element according to the second embodiment. Fig. 13 is a cross-sectional view showing the method for manufacturing a semiconductor memory element according to the second embodiment. Fig. 14 is a cross-sectional view showing the method for manufacturing a semiconductor memory element according to the second embodiment. Fig. 15 is a cross-sectional view showing the method for manufacturing a semiconductor memory element according to the second embodiment. FIG. 16 is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to the second embodiment. FIG. 17 is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to the second embodiment. FIG. 18 is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to the second embodiment. FIG. 19 is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to the second embodiment. FIG. 20 is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to the second embodiment.

1: Core insulating film 2: Channel semiconductor layer 3: Tunnel insulating film 4: Charge storage film 5: Block insulating film 5a: Insulating film 5b: Insulating film 6: Electrode layer 6a: Barrier metal layer 6b: Electrode material layer 11: Substrate 12: Insulating film 14: Insulating layer H1: Memory hole H2: Cavity S2: Laminating film

Claims (6)

A semiconductor memory element comprises: a laminated body formed by alternately laminating insulating layers and conductive layers along a first direction; a semiconductor layer arranged in the laminated body along the first direction; a first insulating film arranged between the laminated body and the semiconductor layer along the first direction; a second insulating film arranged between the laminated body and the first insulating film along the first direction; a third insulating film arranged between the laminated body and the second insulating film along the first direction; and The fourth insulating film has a first part and a second part, wherein the first part is disposed between the conductive layer and the third insulating film, and the second part is disposed between the conductive layer and the insulating layer along a second direction intersecting the first direction and connected to the first part; the average concentration of deuterium in the first part is higher than the average concentration of deuterium in the third insulating film, and the ratio of the deuterium concentration to the hydrogen concentration in the first part is lower than the ratio of the deuterium concentration to the hydrogen concentration in the third insulating film. A semiconductor memory element as claimed in claim 1, wherein the ratio of the deuterium concentration to the hydrogen concentration in at least one of the first part and the third insulating film is greater than 1. A semiconductor memory element as claimed in claim 2, wherein the ratio of the deuterium concentration to the hydrogen concentration in at least one of the first part and the third insulating film is greater than 10. The semiconductor memory element of claim 1 further comprises a first wiring arranged along the second direction, and the semiconductor layer is electrically connected to the first wiring. A semiconductor memory element as claimed in claim 1, wherein the first insulating film comprises silicon oxynitride, the second insulating film comprises silicon nitride, the third insulating film comprises silicon oxide, and the fourth insulating film comprises aluminum oxide. A semiconductor memory device as claimed in claim 1, wherein the first part has a High-k film, and the ratio of the deuterium concentration to the hydrogen concentration in the High-k film is greater than 10.