TWI874249B - Method for fabricating electronic package - Google Patents

Abstract

A method for manufacturing electronic packages, including: providing a first substrate, arranging electronic components on the first substrate, bonding a second substrate to the first substrate, and forming an encapsulation layer between the first substrate and the second substrate. When the first substrate is a core-less-layer substrate, before the electronic component is disposed on the first substrate, a heating process is performed on the first substrate to release stress. When the second substrate is a core-less-layer substrate, a heating process is performed on the second substrate before the second substrate is bonded to the first substrate to release stress.

Description

Method for manufacturing electronic packaging components

The present invention relates to a semiconductor packaging technology, in particular to a method for manufacturing electronic packaging components.

With the evolution of semiconductor packaging technology, semiconductor devices have developed different packaging types. In order to improve electrical performance and save packaging space, the industry has developed a packaging type that stacks multiple package structures to form a package stacking structure (Package on Package, referred to as POP). This packaging type can give play to the heterogeneous integration characteristics of the system package (SiP). Electronic components with different functions, such as memory, central processing unit, graphics processor, image application processor, etc., can be integrated into the system through stacking design, and are suitable for various thin and short electronic products.

FIG. 1 is a cross-sectional schematic diagram of a conventional package stacking structure 1, which includes a first semiconductor chip 10, a first package substrate 11, a second package substrate 12, a plurality of solder balls 13, a second semiconductor chip 14, and a packaging resin 15. The first package substrate 11 has a plurality of circuit layers 111, and the second package substrate 12 has a plurality of circuit layers 121. The first semiconductor chip 10 is disposed on the first package substrate 11 in a flip-chip manner, and the second semiconductor chip 14 is also disposed on the second package substrate 12 in a flip-chip manner. The solder balls 13 are used to connect and electrically couple the first package substrate 11 and the second package substrate 12. The packaging resin 15 covers the solder balls 13 and the first semiconductor chip 10. In addition, a primer 16 may be selectively formed between the first semiconductor chip 10 and the first packaging substrate 11.

Since the first substrate (substrate without core layer) is affected by external force or thermal process during the manufacturing process, residual stress is accumulated. If this residual stress is not eliminated during the packaging process, it will affect the final package stacking structure after packaging. The shape of the warp (smiley face or crying face), that is, the edge of the package stacking structure will bend upward or downward.

Furthermore, the morphology of the final package stacking structure must conform to the morphology of the subsequently connected printed circuit board (PCB). If it does not match the morphology of the printed circuit board, solder ball non-wetting will occur in the final package stacking structure connection, and even cause reliability problems for consumer products.

Therefore, how to overcome the various shortcomings of knowledge technology is a technical problem that all walks of life are eager to solve.

In view of the above-mentioned deficiencies in the prior art, the present invention provides a method for manufacturing an electronic package, comprising: providing a first substrate; placing an electronic component on the first substrate, wherein before placing the electronic component on the first substrate, a heating process is first performed on the first substrate to release stress; and bonding a second substrate to the first substrate.

The aforementioned method for manufacturing an electronic package further includes forming a coating layer between the first substrate and the second substrate to cover the electronic component.

The aforementioned method for manufacturing an electronic package further includes providing a plurality of conductive elements on the side of the first substrate that is not connected to the second substrate.

In the aforementioned method for manufacturing electronic packages, one of the first substrate and the second substrate is a substrate without a core layer and undergoes the heating process to release stress.

In the aforementioned method for manufacturing an electronic package, the other of the first substrate and the second substrate is a substrate having a core layer.

In the aforementioned method for manufacturing electronic packages, the first substrate and the second substrate are both core-less substrates and undergo the heating process to release stress.

In the aforementioned method for manufacturing an electronic package, the electronic component is connected to the first substrate via a plurality of conductive bumps.

The aforementioned method for manufacturing the electronic package further includes forming a primer between the electronic component and the first substrate to cover the plurality of conductive bumps.

In the aforementioned method for manufacturing an electronic package, the second substrate is connected to the second substrate through a plurality of conductive components.

In the aforementioned method for manufacturing electronic packages, the coreless substrate includes a dielectric layer and a wiring layer combined with the dielectric layer.

As can be seen from the above, the manufacturing method of the electronic package of the present invention mainly performs a heating process before the electronic components are placed on the first substrate when the first substrate is a substrate without a core layer, or before the second substrate is placed on the first substrate when the second substrate is a substrate without a core layer, to achieve the purpose of stress release. By releasing the stress of the first substrate or the second substrate, the morphology of the final electronic package meets the expected requirements, so as to avoid the morphology of the conventional package stacking structure not matching the morphology of the printed circuit board, resulting in the problem of solder ball non-wetting, which leads to reliability problems of consumer products.

1: Package stack structure

10: First semiconductor chip

11: First packaging substrate

111,121: Circuit layer

12: Second packaging substrate

13: Welding Ball

14: Second semiconductor chip

15: Packaging colloid

16: Base glue

2: Electronic packaging

20: Electronic components

200: Conductive bump

201: Base glue

21: First substrate

21a: First side

21b: Second side

211: Dielectric layer

212: Wiring layer

22: Second substrate

220: Core layer

222: Circuit layer

23: Conductive parts

24: Coating layer

26: Conductive element

S21~S25: Steps

FIG1 is a schematic cross-sectional view of a known package stacking structure 1.

Figure 2 is a schematic diagram of the process of manufacturing the electronic package of the present invention.

Figures 3 to 7 are cross-sectional schematic diagrams of the manufacturing method of the electronic package of the present invention.

The following is a specific and concrete example to illustrate the implementation of the present invention. People familiar with this technology can easily understand other advantages and effects of the present invention from the content disclosed in this manual.

It should be noted that the structures, proportions, sizes, etc. depicted in the drawings attached to this specification are only used to match the contents disclosed in the specification for understanding and reading by people familiar with this technology, and are not used to limit the restrictive conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "above", "first", "second" and "one" used in this specification are only used to facilitate the clarity of the description, and are not used to limit the scope of implementation of the present invention. Changes or adjustments to their relative relationships, without substantially changing the technical content, should also be regarded as the scope of implementation of the present invention.

Please refer to Figure 2, which is a schematic diagram of the process of manufacturing the electronic package of the present invention, and please also refer to Figures 3 to 7, which are cross-sectional schematic diagrams of the manufacturing method of the electronic package of the present invention.

As shown in FIG. 2 and FIG. 3, step S21 is first performed to provide a first substrate 21, and the first substrate 21 is heated to release stress.

The first substrate 21 is, for example, a coreless substrate having a first side 21a and a second side 21b opposite to each other, and includes a dielectric layer 211 and a wiring layer 212 combined with the dielectric layer 211. For example, the material forming the wiring layer 212 is copper, and the material forming the dielectric layer 211 is polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials, and the wiring layer 212 and the dielectric layer 211 can be formed by a redistribution layer (RDL) process.

This step mainly performs a heating process on the first substrate 21 to achieve the purpose of stress release, so as to avoid the accumulation of residual stress caused by external force or thermal process in the subsequent manufacturing process, and even affect the morphology of the final electronic package structure.

As shown in FIG. 2 and FIG. 4 , step S22 is performed to set at least one electronic component 20 on the first substrate 21.

The electronic component 20 is disposed on the first side 21a of the first substrate 21 and electrically connected to the wiring layer 212. The electronic component 20 may be, for example, an active component, a passive component, or a combination thereof. The active component may be, for example, a semiconductor chip, and the passive component may be, for example, a resistor, a capacitor, and an inductor. In this embodiment, the electronic component 20 is a semiconductor chip and is disposed on the first side 21a of the first substrate 21 through a plurality of conductive bumps 200 in a flip chip manner. In other embodiments, the electronic component 20 may also be electrically connected to the wiring layer 212 by wire bonding, direct contact, or other appropriate methods.

In addition, a base glue 201 may be disposed between the electronic element 20 and the first substrate 21 to cover the plurality of conductive bumps 200.

As shown in Figures 2 and 5, step S23 is performed to bond the second substrate 22 to the first substrate 21.

In this embodiment, the second substrate 22 is a core layer substrate having a core layer 220 and a circuit layer 222. The second substrate 22 is connected to the first side 21a of the first substrate 21 through a plurality of conductive elements 23, and the circuit layer 222 is electrically connected to the wiring layer 212. The conductive element 23 is, for example, a copper column or a solder ball.

Since the second substrate 22 has a core layer 220 and has a certain strength, it is not necessary to heat it first to release stress. In another embodiment, if the second substrate 22 is a substrate without a core layer, the second substrate 22 can be heated to release stress before being placed on the first substrate 21, similar to the aforementioned step S21.

In another embodiment, if the first substrate 21 has a core layer and has a certain strength, it is not necessary to heat it first to release the stress, and the electronic component 20 can be directly placed on the first substrate 21; if the second substrate 22 is a substrate without a core layer, the second substrate 22 is first heated to release the stress before being placed on the first substrate 21.

As shown in Figures 2 and 6, step S24 is performed to form a coating layer 24 between the first substrate 21 and the second substrate 22.

In this embodiment, a coating layer 24 is mainly formed between the first substrate 21 and the second substrate 22 to cover the electronic element 20. The coating layer 24 can be an insulating material, such as polyimide (PI), dry film, epoxy packaging colloid or molding compound, but is not limited to the above.

As shown in Figures 2 and 7, step S25 is performed to set a plurality of conductive elements 26 under the first substrate.

In this embodiment, a plurality of conductive elements 26 such as solder bumps or solder balls (whose specifications are C4 type) are mainly combined on the second side 21b of the first substrate 21, and the plurality of conductive elements 26 are electrically connected to the wiring layer 212 to obtain the electronic package 2 of the present invention. Subsequently, the electronic package 2 can be connected to an external device such as a circuit board through the plurality of conductive elements 26.

Therefore, the manufacturing method of the electronic package of the present invention mainly performs a heating process before the electronic components are placed on the first substrate when the first substrate is a substrate without a core layer, or before the second substrate is placed on the first substrate when the second substrate is a substrate without a core layer, to achieve the purpose of stress release. By releasing the stress of the first substrate or the second substrate, the morphology of the final electronic package meets the expected requirements, avoiding the mismatch between the morphology of the known package stacking structure and the morphology of the printed circuit board, and the problem of the solder ball not being wetted, which leads to the reliability problem of consumer products. In addition, the above-mentioned manufacturing method does not need to increase the development of new processes and materials or purchase machines. The existing technical problems in the industry can be solved with existing materials and old processes and machines, so there will be no large amount of additional cost expenditure.

The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Anyone familiar with this technology can modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application described below.

S21~S25: Steps

Claims (10)

A method for manufacturing an electronic package includes: Providing a first substrate; An electronic component is arranged on the first substrate, wherein before the electronic component is arranged on the first substrate, a heating process is first performed on the first substrate to release stress; and Bonding the second substrate to the first substrate. The method for manufacturing an electronic package as described in claim 1 further includes forming a coating layer between the first substrate and the second substrate to cover the electronic component. The method for manufacturing an electronic package as described in claim 1 further includes providing a plurality of conductive elements on the side of the first substrate that is not connected to the second substrate. A method for manufacturing an electronic package as described in claim 1, wherein one of the first substrate and the second substrate is a substrate without a core layer and undergoes the heating process to release stress. A method for manufacturing an electronic package as described in claim 4, wherein the other of the first substrate and the second substrate is a substrate having a core layer. The method for manufacturing an electronic package as described in claim 1, wherein the first substrate and the second substrate are both core-less substrates and undergo the heating process to release stress. A method for manufacturing an electronic package as described in claim 1, wherein the electronic component is connected to the first substrate via a plurality of conductive bumps. The method for manufacturing an electronic package as described in claim 7 further includes forming a primer between the electronic component and the first substrate to cover the plurality of conductive bumps. A method for manufacturing an electronic package as described in claim 1, wherein the second substrate is connected to the first substrate through a plurality of conductive components. A method for manufacturing an electronic package as described in claim 1, wherein one of the first substrate and the second substrate is a coreless substrate, and the coreless substrate includes a dielectric layer and a wiring layer combined with the dielectric layer.

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