TWI874068B - Bias current automatic adjustment circuit, display driver chip, display device and information processing device - Google Patents

Abstract

The present invention discloses a bias current automatic adjustment circuit, which is used to be integrated in a source drive unit to couple a plurality of channel drive units, and mainly includes a logic unit and a bias current adjustment module, wherein the logic unit is configured to output a maximum gear data, a minimum gear data, a sub-gear data, and an input voltage, and the bias current adjustment module is configured to generate a sub-bias current with a gear between the maximum gear and the minimum gear. In this way, when the load change of the display screen is small, the logic unit enables the bias current adjustment module to transmit the sub-bias current to a bias terminal of a buffer amplifier, thereby reducing the circuit power consumption.

Description

Bias current automatic adjustment circuit, display driver chip, display device and information processing device

The present invention relates to the technical field of OLED display, and in particular to a channel driving circuit with a bias current automatic adjustment function integrated in a source driving unit.

As is known, flat panel displays include non-self-luminous flat panel displays and self-luminous flat panel displays, wherein liquid crystal displays are a type of non-self-luminous flat panel displays that have been used for a long time, while organic light-emitting diode (OLED) displays and light-emitting diode (LED) displays are self-luminous flat panel displays that are currently in mainstream applications. FIG1 is a block diagram of a known OLED display device. As shown in FIG1 , the conventional OLED display device 1a mainly includes: an OLED panel 11a, a display controller (Tcon) 120a, a gate driver unit 121a, a source driver unit 122a, and an EM control unit 123a, wherein the OLED panel 11a includes X×Y pixel circuits 111a and X×Y OLED elements 112a, and X and Y are positive integers. Further, FIG2 is a circuit block diagram of the source driver unit shown in FIG1 . As shown in FIG. 2 , the conventional source driving unit 122a includes a shift register 1221a, a data register 1222a, a data latch 1223a, a level shifter 1224a, a logic unit 1225a, and a plurality of channel driving units 1226a.

As shown in FIG. 1 and FIG. 2 , the source driving unit 122a includes a plurality of channels for coupling to a plurality of source lines of the OLED panel 11a, and each of the channel driving units 1226a is used to generate a display data voltage VDATA and drive it to its corresponding channel. Further, FIG. 3 is a circuit diagram of the channel driving unit shown in FIG. 2 . As shown in FIG. 3 , each of the channel driving units 1226a includes: a buffer amplifier 1227a, a selection unit 1228a, and a plurality of current sources 1220a ( ), wherein the logic unit 1225a is configured to generate an input voltage Vin according to a shift display data received from the level shifter 1224a, and to generate a corresponding level data SAP according to the line load size of each source line. Specifically, as shown in the following table (1), each level data SAP has its corresponding description. Table (1) SAP[3:0] Description 0h ×0.3 1h ×0.4 2h ×0.5 3h ×0.6 4h ×0.7 5h ×0.8 6h ×0.9 7h ×1.0 8h ×1.1 9h ×1.2 Ah ×1.3 Bh ×1.4 Ch ×1.5 Dh ×1.6 E ×1.7 F ×1.8

In the above table (1), SAP[3:0] is a 4-bit data (i.e., the aforementioned gear data), which is represented by 0000B to 1111B in binary, and 0H to FH in hexadecimal. In other words, SAP[3:0]=0h~Fh respectively represents the bias current of the 1st to 16th current sources 1220a ( ). In this way, the logic unit 1225a can use the gear data SAP to specify the bias current gear of the buffer amplifier 1227a, for example, setting it to the 7th gear or the 5th gear, thereby adjusting the output voltage (ie, the display data voltage VDATA) of the buffer amplifier 1227a.

In practice, in order to ensure the quality of the display image and optimize the power consumption, the source drive bias current is set to an appropriate level through repeated debugging during the module verification phase according to the actual RC loading conditions of the OLED panel 11a.

As can be seen from the above table (1), the higher the value of the gear data, the greater the bias current of the buffer amplifier 1227a, which is accompanied by high power consumption. Therefore, when the load change of the display screen is relatively small, if the gear of the bias current is still fixed, the source drive unit 122a will continue to generate high power consumption. In view of this, it should be considered to change the circuit design of the channel drive circuit 1226a shown in Figure 3, so that in addition to fixing the gear of the bias current of the buffer amplifier 1227a according to the RC loading of the source line, it can also adaptively adjust the gear of the bias current high or low according to the load change of the display screen.

From the above description, it can be seen that a new type of bias current automatic adjustment circuit is urgently needed in the field.

The main purpose of the present invention is to provide a bias current automatic adjustment circuit, which is used to be integrated in a source drive unit to couple a plurality of channel drive units, and mainly includes a logic unit and a bias current adjustment module, wherein the logic unit is configured to output a maximum gear data, a minimum gear data, a sub-gear data, and an input voltage, and the bias current adjustment module is configured to generate a sub-bias current with a gear between the maximum gear and the minimum gear.

During normal operation, a selection unit of the channel driving unit selects one from a plurality of current sources according to the maximum gear data output by the logic unit, and transmits the bias current of the current source to the bias end of a buffer amplifier of the channel driving unit. Furthermore, when the load change of the display screen is small, the logic unit enables the bias current adjustment module to transmit the sub-bias current to the bias end of the buffer amplifier, thereby reducing circuit power consumption. Designed in this way, the bias current automatic adjustment circuit of the present invention can not only fix the bias current level of the buffer amplifier according to the RC loading of the display panel coupled to the source drive unit, but also adaptively adjust the bias current level high or low according to the load change of the display screen, thereby reducing the overall power consumption of the circuit.

To achieve the above-mentioned purpose, the present invention proposes an embodiment of the bias current automatic adjustment circuit, which is used to be integrated in a source drive unit and includes: A logic unit coupled to a plurality of channel drive units included in the source drive unit, wherein each of the channel drive units includes a buffer amplifier and a selection unit coupled to a plurality of first current sources, and the logic unit is configured to output a maximum gear data and a minimum gear data, generate a sub-gear data according to a current frame display data and a previous frame display data, and generate an input voltage; and A bias current adjustment module is coupled to the logic unit to receive the maximum gear data, the minimum gear data and the sub-gear data, and is also coupled to the selection unit and the buffer amplifier; Wherein, the logic unit transmits the input voltage to a positive input terminal of the buffer amplifier, and transmits the maximum gear data to a control terminal of the selection unit, so that the selection unit selects one from the plurality of first current sources according to the maximum gear data, so that a bias current of the selected first current source is transmitted to the bias current adjustment module; Wherein, the bias current adjustment module is configured to generate a sub-bias current according to the maximum gear data, the minimum gear data and the sub-gear data; The logic unit transmits an enable signal to the bias current adjustment module, and uses the enable signal to control the bias current adjustment module to output the sub-bias current or transmit the bias current to a bias end of the buffer amplifier.

In one embodiment, the bias current adjustment module includes: an interpolation operation unit, coupled to the logic unit to receive the maximum gear data, the minimum gear data and the sub-gear data, and perform an interpolation operation on the maximum gear data, the minimum gear data and the sub-gear data to obtain a current adjustment ratio, thereby generating a current adjustment signal according to the current adjustment ratio; a second current source, having a bias terminal and an output terminal, and the bias terminal is coupled to the interpolation operation unit to receive the current adjustment signal, thereby outputting the sub-bias current under the control of the current adjustment signal; and A switching unit has a first input terminal, a second input terminal, a control terminal, and an output terminal, wherein the first input terminal is coupled to the selection unit to receive the bias current, the second input terminal is coupled to the output terminal of the second current source to receive the sub-bias current, and the control terminal is coupled to the logic unit to receive the enable signal.

In one embodiment, the logic unit executes an operation method to generate the sub-level data, and the operation method includes the following steps: A first display screen corresponding to the current frame display data is divided into N first-row display blocks, and a second display screen corresponding to the previous frame display data is divided into N second-row display blocks, N is a positive integer; A first difference operation is performed on two adjacent first-row display blocks among the N first-row display blocks, thereby obtaining an intra-frame adjacent row difference; A second difference operation is performed on the i-th first-row display block and the i-th second-row display block, thereby obtaining an inter-frame row difference, i∈N; Perform a search operation to obtain the sub-level data LSAP corresponding to both the intra-frame adjacent row difference and the inter-frame row difference from a pre-made search table; and Repeat the first difference operation, the second difference operation and the search operation to obtain a plurality of the intra-frame adjacent row differences, a plurality of the inter-frame row differences and a plurality of the sub-level data LSAP.

In one embodiment, the interpolation operation unit calculates the current adjustment ratio using the following formula (1); …………(1) Wherein, SAP_ratio is the current adjustment ratio, SAP_max is the maximum gear data, SAP_min is the minimum gear data, LSAP is the sub-gear data, and K is used to represent the total number of sub-gears.

In one embodiment, the maximum gear data and the minimum gear data are both 4-bit data, and the sub-gear data is 3-bit data.

Furthermore, the present invention also proposes an embodiment of a display driver chip, which includes a source driver unit; the characteristic is that the source driver unit has a bias current automatic adjustment circuit, and the bias current automatic adjustment circuit includes: A logic unit coupled to a plurality of channel driver units included in the source driver unit, wherein each of the channel driver units includes a buffer amplifier and a selection unit coupled to a plurality of first current sources, and the logic unit is configured to output a maximum gear data and a minimum gear data, generate a sub-gear data according to a current frame display data and a previous frame display data, and generate an input voltage; and A bias current adjustment module is coupled to the logic unit to receive the maximum gear data, the minimum gear data and the sub-gear data, and is also coupled to the selection unit and the buffer amplifier; Wherein, the logic unit transmits the input voltage to a positive input terminal of the buffer amplifier, and transmits the maximum gear data to a control terminal of the selection unit, so that the selection unit selects one from the plurality of first current sources according to the maximum gear data, so that a bias current of the selected first current source is transmitted to the bias current adjustment module; Wherein, the bias current adjustment module is configured to generate a sub-bias current according to the maximum gear data, the minimum gear data and the sub-gear data; The logic unit transmits an enable signal to the bias current adjustment module, and uses the enable signal to control the bias current adjustment module to output the sub-bias current or transmit the bias current to a bias end of the buffer amplifier.

In one embodiment, the bias current adjustment module includes: an interpolation operation unit, coupled to the logic unit to receive the maximum gear data, the minimum gear data and the sub-gear data, and perform an interpolation operation on the maximum gear data, the minimum gear data and the sub-gear data to obtain a current adjustment ratio, thereby generating a current adjustment signal according to the current adjustment ratio; a second current source, having a bias terminal and an output terminal, and the bias terminal is coupled to the interpolation operation unit to receive the current adjustment signal, thereby outputting the sub-bias current under the control of the current adjustment signal; and A switching unit has a first input terminal, a second input terminal, a control terminal, and an output terminal, wherein the first input terminal is coupled to the selection unit to receive the bias current, the second input terminal is coupled to the output terminal of the second current source to receive the sub-bias current, and the control terminal is coupled to the logic unit to receive the enable signal.

In one embodiment, the logic unit executes an operation method to generate the sub-level data, and the operation method includes the following steps: A first display screen corresponding to the current frame display data is divided into N first-row display blocks, and a second display screen corresponding to the previous frame display data is divided into N second-row display blocks, N is a positive integer; A first difference operation is performed on two adjacent first-row display blocks among the N first-row display blocks, thereby obtaining an intra-frame adjacent row difference; A second difference operation is performed on the i-th first-row display block and the i-th second-row display block, thereby obtaining an inter-frame row difference, i∈N; Perform a search operation to obtain the sub-level data LSAP corresponding to both the intra-frame adjacent row difference and the inter-frame row difference from a pre-made search table; and Repeat the first difference operation, the second difference operation and the search operation to obtain a plurality of the intra-frame adjacent row differences, a plurality of the inter-frame row differences and a plurality of the sub-level data LSAP.

In one embodiment, the interpolation operation unit calculates the current adjustment ratio using the following formula (1); …………(1) Wherein, SAP_ratio is the current adjustment ratio, SAP_max is the maximum gear data, SAP_min is the minimum gear data, LSAP is the sub-gear data, and K is used to represent the total number of sub-gears.

In one embodiment, the maximum gear data and the minimum gear data are both 4-bit data, and the sub-gear data is 3-bit data.

Furthermore, the present invention also provides a display device, which is characterized in that it includes a display panel and at least one display driver chip of the present invention as described above.

In addition, the present invention also provides an information processing device having at least one display device; the display device includes a display panel and at least one display driver chip of the present invention as described above. In a feasible embodiment, the information processing device is an electronic device selected from the group consisting of a head-mounted display device, a smart TV, a smart phone, a smart watch, a tablet computer, an all-in-one computer, a notebook computer, a car entertainment device, a digital camera, and a video door phone.

In order to enable the Review Committee to further understand the structure, features, purpose, and advantages of the present invention, the following are attached with drawings and detailed descriptions of preferred specific embodiments.

FIG4 is a block diagram of a display device including a bias current automatic adjustment circuit of the present invention. As shown in FIG4, the display device 1 mainly includes: a display panel 11, a display controller (Tcon) 10, a gate drive unit 13, a source drive unit 12, and a light-emitting control unit 14. Further, FIG5 is a circuit block diagram of the source drive unit shown in FIG4. As shown in FIG5, the source drive unit 12 includes: a shift register 121, a data register 122, a data latch 123, a level shifter 124, the bias current automatic adjustment circuit 125 of the present invention, and a plurality of channel drive units 126. As shown in FIG. 4 and FIG. 5 , the source driving unit 12 includes a plurality of channels for coupling to a plurality of source lines of the display panel 11 , and each of the channel driving units 126 is used to generate a display data voltage VDATA and drive it to its corresponding channel.

FIG6 is a circuit diagram of the bias current automatic adjustment circuit shown in FIG5. As shown in FIG6, each of the channel driving units 126 includes: a buffer amplifier 1261, a selection unit 1262 and a plurality of first current sources 1263, wherein the selection unit 1262 has a plurality of input terminals respectively coupled to the plurality of first current sources 1263, a control terminal and an output terminal. In addition, the buffer amplifier 1261 has a positive input terminal, a negative input terminal, a bias terminal, and an output terminal, and the negative input terminal is coupled to the output terminal. According to the present invention, the bias current automatic adjustment circuit 125 mainly includes a logic unit 1251 and a bias current adjustment module 1252, wherein the logic unit 1251 is coupled to the control end of the logic unit 1251 and the positive input end of the buffer amplifier 1261, and is configured to: output a maximum gear data (SAP_max) and a minimum gear data (SAP_min), generate a sub-gear data according to a current frame display data and a previous frame display data, and generate an input voltage Vin. According to FIG. 6 , the logic unit 1251 transmits the input voltage Vin to the positive input terminal of the buffer amplifier 1261, and transmits the maximum gear data to the control terminal of the selection unit 1262, so that the selection unit 1262 selects one from the plurality of first current sources 1263 according to the maximum gear data, thereby causing a bias current of the selected first current source 1263 to be transmitted to the bias current adjustment module 1252.

To explain in more detail, when the display device 1 is working normally, the logic unit 1251 generates an input voltage Vin according to a shifted display data received from the level shifter 124, and generates a corresponding optimal gear data according to the line load (RC loading) of each source line. In practice, after performing an RC loading test on each source line of the display panel 11, a gear table as shown in the following table (2) can be generated according to the line load size of each source line. Table (2) SAP[3:0] Description 0h ×0.3 1h ×0.4 2h ×0.5 3h ×0.6 4h ×0.7 5h ×0.8 6h ×0.9 7h ×1.0 8h ×1.1 9h ×1.2 Ah ×1.3 Bh ×1.4 Ch ×1.5 Dh ×1.6 E ×1.7 F ×1.8

It should be understood that the gear data SAP[3:0] is a 4-bit data, which is represented by 0000B to 1111B in binary, and 0H to FH in hexadecimal. In other words, SAP[3:0]=0h~Fh respectively represents the bias current of the 1st to 16th first current source 1263 ( ).

As shown in FIG6 , the bias current adjustment module 1252 is coupled to the logic unit 1251 to receive the maximum gear data, the minimum gear data and the sub-gear data, and is also coupled to the output end of the selection unit 1262 and the bias end of the buffer amplifier 1261. Specifically, the bias current adjustment module 1252 includes: an interpolation operation unit 1253, a second current source 1254 and a switching unit 1255, wherein the interpolation operation unit 1253 is configured to perform an interpolation operation on the maximum gear data, the minimum gear data and the sub-gear data LSAP using the following formula (1) to obtain a current adjustment ratio, thereby generating a current adjustment signal LSAP_Bias according to the current adjustment ratio: …………(1)

In the above formula (1), SAP_ratio is the current adjustment ratio, SAP_max is the maximum gear data, SAP_min is the minimum gear data, LSAP is the sub-gear data, and K is used to represent the total number of sub-gears. It is particularly noted that the present invention uses the best gear data as the maximum gear data, and, as shown in the following table (3), stores the maximum gear data in hexadecimal or binary in the register of the logic unit 1251. At the same time, the present invention selects a gear data lower than the maximum gear data as the minimum gear data, and, as shown in the following table (3), stores the minimum gear data in the register. Table (3) SAP_max[3:0] 5h ×0.8 SAP_min[3:0] 3h ×0.6

On the other hand, the second current source 1254 has a bias terminal and an output terminal, and the bias terminal is coupled to the interpolation operation unit 1253 to receive the current adjustment signal LSAP_Bias, thereby outputting a sub-bias current with a gear between the maximum gear and the minimum gear under the control of the current adjustment signal LSAP_Bias. In more detail, the switching unit 1255 has a first input terminal, a second input terminal, a control terminal, and an output terminal, wherein the first input terminal is coupled to the selection unit 1262 to receive the bias current, the second input terminal is coupled to the output terminal of the second current source 1254 to receive the sub-bias current, and the control terminal is coupled to the logic unit 1251 to receive the enable signal LSAP_EN.

According to the design of the present invention, as shown in FIG6 , the logic unit 1251 transmits an enable signal LSAP_EN to the switching unit 1255 of the bias current adjustment module 1252, thereby utilizing the enable signal LSAP_EN to control the switching unit 1255 to output the sub-bias current or transmit the bias current to a bias end of the buffer amplifier 1261. Designed in this way, the bias current automatic adjustment circuit 125 of the present invention can not only fix the bias current level of the buffer amplifier 1261 according to the RC loading of the display panel 11 coupled to the source drive unit 12 (i.e., fixed at 0h~Fh as shown in the above table (2)), but also adaptively adjust the sub-level (LSAP) of the sub-bias current according to the load changes of the display screen, so as to reduce the overall power consumption of the circuit.

When adjusting the sub-level of the sub-bias current, specifically, the present invention first calculates an intra-frame line difference (Intra-frame line difference, Intra_Ldiff) and an inter-frame line difference (Inter-frame line difference, Inter_Ldiff), and when the intra-frame line difference falls within a first predetermined difference range and the inter-frame line difference falls within a second predetermined difference range, it is determined that the current load change of the display screen is small, so the circuit power consumption can be reduced by adjusting the sub-bias current.

FIG7 shows a diagram of a first display screen corresponding to the current frame display data and a second display screen corresponding to the previous frame display data. As shown in FIG6 and FIG7, the logic unit 1251 divides a first display screen Cf corresponding to the current frame display data into N first row display blocks Cf1, and divides a second display screen Pf corresponding to the previous frame display data into N second row display blocks Pf2, where N is a positive integer. It is worth noting that the display technology is based on row scanning column drive, where a row (line) refers to the horizontal direction rather than the vertical direction, and a column (column) is the vertical direction. Next, the logic unit 1251 performs a first difference operation on two adjacent first-row display blocks Cf1 among the N first-row display blocks Cf1 to obtain an intra-frame adjacent-row difference, and performs a second difference operation on the i-th first-row display block Cf1 and the i-th second-row display block Pf2 to obtain an inter-frame row difference, i∈N. Then, the logic unit 1251 performs a search operation to obtain a sub-level data LSAP corresponding to both the intra-frame adjacent-row difference and the inter-frame row difference from a pre-made search table (as shown in FIG. 8 ).

In a feasible embodiment, when performing the first difference operation, the average value of the row pixels of the j+1th first row display block Cf1 is subtracted from the average value of the row pixels of the jth first row display block Cf1, where j is a positive integer. Similarly, when performing the second difference operation, the average value of the row pixels of the i-th second row display block Cf2 is subtracted from the average value of the row pixels of the i-th first row display block Cf1, where i is a positive integer. In another feasible embodiment, when performing the first difference operation, the maximum pixel value in the j+1th first row display block Cf1 is subtracted from the maximum pixel value in the j-th first row display block Cf1, where j is a positive integer. Similarly, when performing the second difference operation, the maximum pixel value in the i-th second row display block Pf2 is subtracted from the maximum pixel value in the i-th first row display block Cf1, where i is a positive integer.

It is worth noting that, in the lookup table shown in FIG8 , Inter_Ldiff=31, 64, 96, 128, 160, 192, 224, 255 are the 8 pre-set first binding points, and Intra_Ldiff=31, 64, 96, 128, 160, 192, 224, 255 are the 8 pre-set second binding points. Further, 64 sub-levels corresponding to the 8 first binding points and the 8 second binding points are filled in the lookup table. Thus, as shown in FIG8 , after calculating Inter_Ldiff and Intra_Ldiff, the correct sub-level data (LSAP) can be obtained by looking up the lookup table and performing interpolation operations on the matching values. Finally, the logic unit 1251 repeats the first difference operation, the second difference operation and the search operation, thereby obtaining a plurality of the intra-frame adjacent row differences, a plurality of the inter-frame row differences and a plurality of the sub-level data.

It is particularly noted that, as shown in Figure 8 and the following table (4), 0, 1, 2, 3, 4, 5, 6, and 7 are used to represent the gears of the sub-gear data, and 0.625~0.8 are used to represent the current adjustment parameters of the sub-gear data. Table (4) LSAP[2:0] Description 0 ×0.625 1 ×0.650 2 ×0.675 3 ×0.7 4 ×0.725 5 ×0.750 6 ×0.775 7 ×0.8

Therefore, after obtaining the sub-level data (LSAP) from the lookup table in FIG8 , the interpolation operation unit 1253 can know that the corresponding current adjustment parameter is 0.625~0.8 according to LASP=0~7. Afterwards, the interpolation operation unit 1253 calculates a current adjustment ratio SAP_ratio using the above formula (1), and generates a current adjustment signal LSAP_Bias (as shown in FIG6 ) according to the current adjustment ratio. Finally, as shown in FIG6 , the second current source 1254 outputs a sub-bias current with a level between the maximum level and the minimum level according to this current adjustment signal.

Thus, the above description has completely and clearly explained the bias current automatic adjustment circuit of the present invention; and, from the above description, it can be known that the present invention has the following advantages:

(1) The present invention discloses a bias current automatic adjustment circuit 125, which is used to be integrated in a source driver unit 12 to couple a plurality of channel driver units 126, and mainly includes a logic unit 1251 and a bias current adjustment module 1252, wherein the logic unit 1251 is configured to output a maximum gear data SAP_max, a minimum gear data SAP_min, a sub-gear data LSAP, and an input voltage Vin, and the bias current adjustment module 1252 is configured to generate a sub-bias current with a gear between the maximum gear and the minimum gear. Thus, during normal operation, a selection unit 1262 of the channel driving unit 126 selects one from a plurality of current sources according to the maximum gear data output by the logic unit 1251, and transmits the bias current of the current source to the bias end of a buffer amplifier 1261 of the channel driving unit 126. Furthermore, when the load change of the display screen is small, the logic unit 1251 enables the bias current adjustment module 1252 to transmit the sub-bias current to the bias end of the buffer amplifier 1261, thereby reducing circuit power consumption.

(2) The bias current automatic adjustment circuit 125 of the present invention can not only fix the bias current level of the buffer amplifier 1261 according to the RC loading of the display panel 11 coupled to the source driver unit 12, but also adaptively adjust the level of the sub-bias current to high or low according to the load change of the display screen, thereby reducing the overall power consumption of the circuit.

(3) The present invention also discloses a display driver chip, which includes a source driver unit 12; its characteristic is that the source driver unit 12 has the bias current automatic adjustment circuit 125 of the present invention as described above.

(4) Furthermore, the present invention also provides a display device, which is characterized in that it includes a display panel and at least one display driver chip of the present invention as described above.

(5) Furthermore, the present invention also provides an information processing device having at least one display device; the display device includes a display panel and at least one display driver chip of the present invention as described above. In a feasible embodiment, the information processing device is an electronic device selected from the group consisting of a head-mounted display device, a smart TV, a smart phone, a smart watch, a tablet computer, an all-in-one computer, a laptop computer, a car entertainment device, a digital camera, and a video door phone.

It must be emphasized that what is disclosed in the above-mentioned case is a preferred embodiment. Any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by people familiar with the art do not deviate from the scope of the patent rights of this case.

In summary, this case shows that its purpose, means and effects are all different from the known technology, and it is the first invention that is practical and indeed meets the patent requirements for invention. We sincerely request the review committee to examine this carefully and grant a patent as soon as possible to benefit the society. This is our utmost prayer.

1a: OLED display device 11a: OLED panel 111a: pixel circuit 112a: OLED element 120a: display controller 121a: gate driver unit 122a: source driver unit 1221a: shift register 1222a: data register 1223a: data latch 1224a: level shifter 1225a: logic unit 1226a: channel driver unit 1227a: buffer amplifier 1228a: selection unit 1220a: current source 1: display device 10: display controller 11: display panel 12: source driver unit 121: shift register 122: data register 123: data latch 124: level shifter 125: bias current automatic adjustment circuit 1251: logic unit 1252: bias current adjustment module 1253: interpolation operation unit 1254: second current source 1255: switching unit 126: channel drive unit 1261: buffer amplifier 1262: selection unit 1263: first current source 13: gate drive unit 14: light control unit Cf: first display screen Cf1: first row display block Pf: second display screen Pf2: The second row shows the block

FIG. 1 is a block diagram of a known OLED display device; FIG. 2 is a circuit block diagram of a source drive unit shown in FIG. 1; FIG. 3 is a circuit diagram of a channel drive unit shown in FIG. 2; FIG. 4 is a block diagram of a display device including a bias current automatic adjustment circuit of the present invention; FIG. 5 is a circuit block diagram of a source drive unit shown in FIG. 4; FIG. 6 is a circuit diagram of a bias current automatic adjustment circuit shown in FIG. 5; FIG. 7 is a diagram of a first display screen corresponding to the current frame display data and a second display screen corresponding to the previous frame display data; and FIG. 8 is a diagram of a lookup table.

125: Bias current automatic adjustment circuit

1251:Logic unit

1252: Bias current adjustment module

1253: Interpolation operation unit

1254: Second current source

1255: Switching unit

1261: Buffer amplifier

1262:Select unit

1263: First current source

Claims (12)

A bias current automatic adjustment circuit is used to be integrated in a source drive unit, and includes: a logic unit, coupled to a plurality of channel drive units included in the source drive unit, wherein each of the channel drive units includes a buffer amplifier and a selection unit coupled to a plurality of first current sources, and the logic unit is configured to output a maximum gear data and a minimum gear data, generate a sub-gear data according to a current frame display data and a previous frame display data, and generate an input voltage; and A bias current adjustment module is coupled to the logic unit to receive the maximum gear data, the minimum gear data and the sub-gear data, and is also coupled to the selection unit and the buffer amplifier; Wherein, the logic unit transmits the input voltage to a positive input terminal of the buffer amplifier, and transmits the maximum gear data to a control terminal of the selection unit, so that the selection unit selects one from the plurality of first current sources according to the maximum gear data, so that a bias current of the selected first current source is transmitted to the bias current adjustment module; Wherein, the bias current adjustment module is configured to generate a sub-bias current according to the maximum gear data, the minimum gear data and the sub-gear data; The logic unit transmits an enable signal to the bias current adjustment module, and uses the enable signal to control the bias current adjustment module to output the sub-bias current or transmit the bias current to a bias end of the buffer amplifier. The bias current automatic adjustment circuit as described in claim 1, wherein the bias current adjustment module includes: an interpolation operation unit, coupled to the logic unit to receive the maximum gear data, the minimum gear data and the sub-gear data, and perform an interpolation operation on the maximum gear data, the minimum gear data and the sub-gear data to obtain a current adjustment ratio, thereby generating a current adjustment signal according to the current adjustment ratio; a second current source, having a bias terminal and an output terminal, and the bias terminal is coupled to the interpolation operation unit to receive the current adjustment signal, thereby outputting the sub-bias current under the control of the current adjustment signal; and A switching unit has a first input terminal, a second input terminal, a control terminal, and an output terminal, wherein the first input terminal is coupled to the selection unit to receive the bias current, the second input terminal is coupled to the output terminal of the second current source to receive the sub-bias current, and the control terminal is coupled to the logic unit to receive the enable signal. The bias current automatic adjustment circuit as described in claim 1, wherein the logic unit executes an operation method to generate the sub-level data, and the operation method includes the following steps: Divide a first display screen corresponding to the current frame display data into N first-row display blocks, and divide a second display screen corresponding to the previous frame display data into N second-row display blocks, where N is a positive integer; Perform a first difference operation on two adjacent first-row display blocks among the N first-row display blocks, thereby obtaining adjacent row differences within a frame; Perform a second difference operation on the i-th first row display block and the i-th second row display block to obtain an inter-frame row difference, i∈N; Perform a search operation to obtain the sub-level data corresponding to both the intra-frame adjacent row difference and the inter-frame row difference from a pre-made search table; and Repeat the first difference operation, the second difference operation and the search operation to obtain a plurality of intra-frame adjacent row differences, a plurality of inter-frame row differences and a plurality of sub-level data. The bias current automatic adjustment circuit as described in claim 2, wherein the interpolation operation unit calculates the current adjustment ratio using the following formula (1); …………(1); wherein SAP_ratio is the current adjustment ratio, SAP_max is the maximum gear data, SAP_min is the minimum gear data, LSAP is the sub-gear data, and K is used to represent the total number of sub-gears. A bias current automatic adjustment circuit as described in claim 2, wherein the maximum gear data and the minimum gear data are both 4-bit data, and the sub-grade data is 3-bit data. A display driver chip includes a source driver unit; the characteristic is that the source driver unit has a bias current automatic adjustment circuit, and the bias current automatic adjustment circuit includes: A logic unit coupled to a plurality of channel driver units included in the source driver unit, wherein each of the channel driver units includes a buffer amplifier and a selection unit coupled to a plurality of first current sources, and the logic unit is configured to output a maximum gear data and a minimum gear data, generate a sub-gear data according to a current frame display data and a previous frame display data, and generate an input voltage; and A bias current adjustment module is coupled to the logic unit to receive the maximum gear data, the minimum gear data and the sub-gear data, and is also coupled to the selection unit and the buffer amplifier; Wherein, the logic unit transmits the input voltage to a positive input terminal of the buffer amplifier, and transmits the maximum gear data to a control terminal of the selection unit, so that the selection unit selects one from the plurality of first current sources according to the maximum gear data, so that a bias current of the selected first current source is transmitted to the bias current adjustment module; Wherein, the bias current adjustment module is configured to generate a sub-bias current according to the maximum gear data, the minimum gear data and the sub-gear data; The logic unit transmits an enable signal to the bias current adjustment module, and uses the enable signal to control the bias current adjustment module to output the sub-bias current or transmit the bias current to a bias end of the buffer amplifier. The display driver chip as described in claim 6, wherein the bias current adjustment module includes: an interpolation operation unit, coupled to the logic unit to receive the maximum gear data, the minimum gear data and the sub-gear data, and perform an interpolation operation on the maximum gear data, the minimum gear data and the sub-gear data to obtain a current adjustment ratio, thereby generating a current adjustment signal according to the current adjustment ratio; a second current source, having a bias terminal and an output terminal, and the bias terminal is coupled to the interpolation operation unit to receive the current adjustment signal, thereby outputting the sub-bias current under the control of the current adjustment signal; and A switching unit has a first input terminal, a second input terminal, a control terminal, and an output terminal, wherein the first input terminal is coupled to the selection unit to receive the bias current, the second input terminal is coupled to the output terminal of the second current source to receive the sub-bias current, and the control terminal is coupled to the logic unit to receive the enable signal. A display driver chip as described in claim 6, wherein the logic unit executes an operation method to generate the sub-level data, and the operation method includes the following steps: Divide a first display screen corresponding to the current frame display data into N first-row display blocks, and divide a second display screen corresponding to the previous frame display data into N second-row display blocks, N is a positive integer; Perform a first difference operation on two adjacent first-row display blocks among the N first-row display blocks, thereby obtaining an intra-frame adjacent row difference; Perform a second difference operation on the i-th first-row display block and the i-th second-row display block, thereby obtaining an inter-frame row difference, i∈N; Perform a search operation to obtain the sub-level data corresponding to both the intra-frame adjacent row difference and the inter-frame row difference from a pre-made search table; and Repeat the first difference operation, the second difference operation and the search operation to obtain a plurality of the intra-frame adjacent row differences, a plurality of the inter-frame row differences and a plurality of the sub-level data. The display driver chip as claimed in claim 7, wherein the interpolation operation unit calculates the current adjustment ratio using the following formula (1); …………(1); wherein SAP_ratio is the current adjustment ratio, SAP_max is the maximum gear data, SAP_min is the minimum gear data, LSAP is the sub-gear data, and K is used to represent the total number of sub-gears. A display driver chip as described in claim 7, wherein the maximum gear data and the minimum gear data are both 4-bit data, and the sub-grade data is 3-bit data. A display device is characterized by comprising a display panel and at least one display driver chip as described in any one of claim 6 to claim 10. An information processing device has at least one display device, characterized in that the display device includes a display panel and at least one display driver chip as described in any one of claim 6 to claim 10.

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