TWI872995B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

This disclosure provides a semiconductor structure and its manufacturing method including conformally depositing a gate dielectric layer and a first gate metal layer in a first gate trench to define a second gate trench, depositing a planarization material to fill the second gate trench, performing a planarization process to the planarization material to form a planarization layer with a top surface coplanar with that of a side portion of the first gate metal layer, removing the planarization layer and the side portion to form an opening exposing a bottom portion of the first gate metal layer with a top surface lower than a top surface of the gate dielectric layer, and depositing a second metal gate layer in the opening to cover the top surface of the bottom portion. A top surface of the second metal layer is coplanar with that of the gate dielectric layer, and the second metal layer has hardness higher than that of the first metal gate layer.

Description

Semiconductor device and method for manufacturing the same

The present disclosure relates to semiconductor devices and methods for manufacturing the same.

The manufacture of semiconductor devices generally includes sequentially depositing and patterning dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate to form circuit components, such as gate structures and gate contacts. After forming the gate structure, the gate structure may be subjected to, for example, a heat treatment process to reduce damage to the gate structure during the manufacture of the gate contacts. However, the heat treatment process may cause excessive thermal budget and degrade components of the semiconductor device.

According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes conformally depositing a gate dielectric layer and a first gate metal layer in a first gate trench to define a second gate trench on the first gate metal layer, depositing a planarizing material on the first gate metal layer to fill the second gate trench, and performing a planarizing process on the planarizing material to form a planarizing layer, wherein a top surface of the planarizing layer is flush with a top surface of a side portion of the first gate metal layer. The planar layer and the side of the first gate metal layer are removed to form an opening exposing the bottom of the first gate metal layer, wherein the top surface of the bottom of the first gate metal layer is lower than the top surface of the gate dielectric layer. A second gate metal layer is deposited in the opening to cover the top surface of the bottom of the first gate metal layer, wherein the top surface of the second gate metal layer is flush with the top surface of the gate dielectric layer, and the hardness of the second gate metal layer is greater than the hardness of the first gate metal layer.

According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes sequentially forming a gate dielectric layer, a first work function metal layer, and a first gate metal layer in a first gate trench to define a second gate trench on the first gate metal layer. A planar layer is formed in the second gate trench, wherein a top surface of the planar layer is flush with a top surface of a side portion of the first gate metal layer, a top surface of a side portion of the first work function metal layer, and a top surface of a side portion of the gate dielectric layer. An etching process is performed on the planar layer, the side of the first gate metal layer and the side of the first work function metal layer. After the etching process, the top surface of the bottom of the first gate metal layer is flush with the top surface of the side of the first work function metal layer and is lower than the top surface of the side of the gate dielectric layer. A second gate metal layer is formed on the top surface of the bottom of the first gate metal layer and the top surface of the side of the first work function metal layer, the top surface of the second gate metal layer is flush with the top surface of the side of the gate dielectric layer, and the hardness of the second gate metal layer is greater than the hardness of the first gate metal layer.

According to some embodiments of the present disclosure, a semiconductor device includes a gate dielectric layer, a first work function metal layer located above the gate dielectric layer, and a first gate metal layer located on the first work function metal layer, wherein a top surface of the first gate metal layer is flush with a top surface of a side of the first work function metal layer and lower than a top surface of the side of the gate dielectric layer. The semiconductor device includes a second gate metal layer covering the top surface of the first gate metal layer and the top surface of the side portion of the first work function metal layer, wherein the top surface of the second gate metal layer is flush with the top surface of the side portion of the gate dielectric layer, and the hardness of the second gate metal layer is greater than the hardness of the first gate metal layer.

According to one embodiment of the present disclosure, FIG. 1 shows a cross-sectional view of a semiconductor device 100. The semiconductor device 100 includes a substrate 110, a source/drain region 120 located in the substrate 110, a gate structure 130 located above the substrate 110, a gate spacer 140 covering a sidewall of the gate structure 130, an interlayer dielectric layer 150 covering the source/drain region 120 and the gate structure 130, and a gate contact 160 located in the interlayer dielectric layer 150 and electrically connected to the gate structure 130.

Specifically, the substrate 110 may include an elemental semiconductor, a compound semiconductor, or a base material suitable for the semiconductor device 100, such as silicon, silicon carbide, silicon germanium, or the like. The substrate 110 may be formed of an undoped or doped semiconductor material, such as doped with nitrogen, phosphorus, arsenic, or other n-type dopants, or doped with boron, gallium, or other p-type dopants. The source/drain region 120 may include the same base material as the substrate 110, but with a higher doping concentration than the substrate 110. For example, the source/drain region 120 may include a silicide layer 122, a first doped region 124 located below the silicide layer 122 and having a first conductivity type, and a second doped region 126 located between the first doped region 124 and the gate structure 130 and having a second conductivity type, but the present disclosure is not limited thereto. For example, the source/drain region 120 in FIG. 2 may further include a third doped region 128 located between the second doped region 126 and the gate structure 130.

The gate structure 130 is located between the plurality of source/drain regions 120 and above the channel region 112 of the substrate 110. The gate structure 130 may include an interfacial layer (IL) 131 on the channel region 112, a gate dielectric layer 132 on the interfacial layer 131, a capping layer 133 on the gate dielectric layer 132, a work function metal (WFM) layer 134 on the capping layer 133, a first gate metal layer 135 on the work function metal layer 134, and a second gate metal layer 136 on the first gate metal layer 135.

The interface layer 131 is located between the gate dielectric layer 132 and the channel region 112, and is used as a buffer layer between the gate structure 130 and the substrate 110. The top surface and the bottom surface of the interface layer 131 can directly contact the gate dielectric layer 132 and the substrate 110, and the sidewall of the interface layer 131 can directly contact the gate spacer 140. The interface layer 131 can be formed of an oxide such as silicon oxide, silicon oxide, etc. In an embodiment in which the gate structure 130 does not include the optional interface layer 131, the bottom surface of the gate dielectric layer 132 can directly contact the channel region 112.

The gate dielectric layer 132 is located between the work function metal layer 134 and the substrate 110. The gate dielectric layer 132 may include a bottom portion 132b above the channel region 112 and a side portion 132s extending along the gate spacer 140, wherein a top surface of the side portion 132s is higher than a top surface of the bottom portion 132b and is flush with a top surface of the gate spacer 140. The bottom surface of the bottom portion 132b may directly contact the interface layer 131, and a sidewall of the side portion 132s may directly contact the gate spacer 140. The gate dielectric layer 132 may be formed of a high-k dielectric material having a dielectric constant greater than that of silicon dioxide, such as a metal oxide having a dielectric constant greater than 4.0.

The capping layer 133 is located between the work function metal layer 134 and the gate dielectric layer 132, and is used as a barrier layer to protect the gate dielectric layer 132. The capping layer 133 may include a bottom 133b above the bottom 132b of the gate dielectric layer 132 and a side 133s extending along the side 132s of the gate dielectric layer 132, wherein a top surface of the side 133s is higher than a top surface of the bottom 133b and lower than a top surface of the side 132s. The top surface and the bottom surface of the bottom portion 133b can directly contact the work function metal layer 134 and the gate dielectric layer 132, respectively, and the sidewall of the side portion 133s can directly contact the gate dielectric layer 132. The cap layer 133 can be formed of, for example, titanium nitride, silicon nitride, or a similar nitride. In an embodiment in which the gate structure 130 does not include the optional cap layer 133, the bottom surface of the work function metal layer 134 can directly contact the gate dielectric layer 132.

The work function metal layer 134 is located between the first gate metal layer 135 and the gate dielectric layer 132. The work function metal layer 134 may include a bottom 134b above the bottom 132b of the gate dielectric layer 132 and a side 134s extending along the side 132s of the gate dielectric layer 132, wherein the top surface of the side 134s is higher than the top surface of the bottom 134b and lower than the top surface of the side 132s. The bottom surface of the bottom 134b may directly contact the capping layer 133, and the sidewall of the side 134s may directly contact the gate dielectric layer 132. The work function metal layer 134 can be formed of an n-type work function metal or a p-type work function metal, such as titanium aluminide, iron aluminide, etc., so that the gate electrode formed by the work function metal layer 134, the first gate metal layer 135 and the second gate metal layer 136 can match the gate dielectric layer 132 with a high dielectric constant.

The first gate metal layer 135 is located between the work function metal layer 134 and the second gate metal layer 136. The bottom surface of the first gate metal layer 135 may directly contact the bottom 134b of the work function metal layer 134, and the sidewall of the first gate metal layer 135 may directly contact the side 134s of the work function metal layer 134. The top surface of the first gate metal layer 135 may be flush with the top surface of the side 134s of the work function metal layer 134 and the top surface of the side 133s of the capping layer 133, and lower than the top surface of the side 132s of the gate dielectric layer 132. The first gate metal layer 135 may be formed of a low-resistivity metal such as aluminum.

The second gate metal layer 136 covers the top surface of the first gate metal layer 135 , thereby serving as a metal capping layer for protecting the first gate metal layer 135 . The bottom surface of the second gate metal layer 136 can directly contact the top surface of the first gate metal layer 135 and the top surface of the side 134s of the work function metal layer 134, so in the direction parallel to the top surface of the substrate 110, the width W2 of the bottom surface of the second gate metal layer 136 is greater than the width W1 of the top surface of the first gate metal layer 135, so that the top surface of the first gate metal layer 135 is completely covered by the bottom surface of the second gate metal layer 136. The top surface of the second gate metal layer 136 can be flush with the top surface of the side 132s of the gate dielectric layer 132, and the side wall of the second gate metal layer 136 can directly contact the side 132s of the gate dielectric layer 132, so that the second gate metal layer 136 and the gate dielectric layer 132 jointly form the top surface of the gate structure 130.

The hardness of the second gate metal layer 136 is greater than that of the first gate metal layer 135 . Therefore, the second gate metal layer 136 can protect the first gate metal layer 135 during the manufacturing process of the semiconductor device 100 , thereby improving the performance of the gate structure 130 . For example, when forming the gate contact 160 directly contacting the gate structure 130, the second gate metal layer 136 may make the bottom surface of the gate contact 160 higher than the bottom surface of the second gate metal layer 136, so as to prevent the gate contact 160 from unexpectedly extending to the first gate metal layer 135 and affecting the performance of the gate structure 130. In some embodiments, when the first gate metal layer 135 is formed of metal aluminum, the second gate metal layer 136 may be formed of metal tungsten.

In some embodiments, in a direction perpendicular to the top surface of the substrate 110, the thickness T1 of the first gate metal layer 135 may be greater than the thickness T2 of the second gate metal layer 136, so that the first gate metal layer 135 with a lower resistivity serves as the main layer of the gate electrode to reduce the total resistivity of the gate structure 130. For example, with respect to the sum of the thickness T1 of the first gate metal layer 135 and the thickness T2 of the second gate metal layer 136, the ratio of the thickness T2 of the second gate metal layer 136 may be less than or equal to 40%.

In an embodiment where the semiconductor device 100 is an N-type metal oxide semiconductor (NMOS) device, the work function metal layer 134 may be a single layer of n-type work function metal material as shown in FIG. 1. In an embodiment where the semiconductor device is a P-type metal oxide semiconductor (PMOS) device, the work function metal layer 134 may be formed of multiple layers of material, such as the cross-sectional view of a semiconductor device 200 shown in FIG. 2. The semiconductor device 200 is similar to the semiconductor device 100 of FIG. 1, but the gate structure 130 of the semiconductor device 200 includes a first work function metal layer 134-1 formed of an n-type work function metal and a second work function metal layer 134-2 formed of a p-type work function metal.

The first work function metal layer 134-1 includes a bottom 134b-1 directly contacting the bottom surface of the first gate metal layer 135 and a side 134s-1 directly contacting the side wall of the first gate metal layer 135, wherein the top surface of the side 134s-1 is flush with the top surface of the first gate metal layer 135 and the top surface of the side 133s of the covering layer 133, and the top surface of the side 134s-1 is lower than the top surface of the side 132s of the gate dielectric layer 132. The second work function metal layer 134-2 is located below the first work function metal layer 134-1 and between the first work function metal layer 134-1 and the capping layer 133. The second work function metal layer 134-2 includes a top surface directly contacting the bottom 134b-1 of the first work function metal layer 134-1 and a bottom surface directly contacting the bottom 133b of the capping layer 133, so that the second work function metal layer 134-2 separates the bottom 134b-1 and the bottom 133b. In some embodiments, the second work function metal layer 134 - 2 may not extend on the side 134 s - 1 of the first work function metal layer 134 - 1 , such that the side 134 s - 1 directly contacts the side 133 s of the capping layer 133 .

According to some embodiments of the present disclosure, FIGS. 3A to 3E illustrate cross-sectional views of multiple intermediate stages of a semiconductor device manufacturing process to exemplify a method for manufacturing a gate structure. To facilitate the description of the steps illustrated in FIGS. 3A to 3E, the semiconductor device 100 of FIG. 1 is used as an example, but those skilled in the art should understand that the method illustrated in FIGS. 3A to 3E can be used to form other semiconductor devices including a gate structure of a metal cap within the scope of the present disclosure, such as the semiconductor device 200 of FIG. 2.

3A , the manufacturing method of the gate structure may start with forming a first gate metal material 305 in a first gate trench 300. Specifically, a dummy gate (not shown), a gate spacer 140, and an interlayer dielectric layer 150 may be formed on a substrate 110, and the dummy gate between the gate spacers 140 may be removed to form the first gate trench 300 exposing the substrate 110. An interface layer 131 (if present), a gate dielectric layer 132, a capping layer 133 (if present), and a work function metal layer 134 are sequentially formed in the first gate trench 300 by a deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), and these material layers do not fill the first gate trench 300.

Next, a first gate metal material 305 is formed in the first gate trench 300 to cover the work function metal layer 134. The first gate metal material 305 may be conformally deposited using a deposition process such as chemical vapor deposition or physical vapor deposition to define a second gate trench 302 on the first gate metal material 305. The first gate metal material 305 may also be deposited on the interlayer dielectric layer 150 so that the first gate metal material 305 covers the gate spacer 140 and the interlayer dielectric layer 150.

Referring to FIG. 3B , a planar material 310 is formed on the first gate metal material 305. Specifically, the planar material 310 may be deposited or coated on the first gate metal material 305 to fill the second gate trench 302 on the first gate metal material 305. The planar material 310 may further extend above the interlayer dielectric layer 150, so that the planar material 310 has a flat top surface. The planar material 310 may include, for example, a photoresist material or a spin-on glass, but is not limited thereto, so that the planar material 310 may have a hardness that can withstand a subsequent planarization process after a curing step.

3C , a planarization process such as chemical mechanical polishing (CMP) is performed on the planar material 310 and the first gate metal material 305, or an etch back is performed followed by a planarization process to form a planar layer 315 and the first gate metal layer 135. The planarization process may stop at the top surface of the interlayer dielectric layer 150, so that the top surface of the planar layer 315 is flush with the top surface of the side portion 135s of the first gate metal layer 135, the top surface of the side portion 134s of the work function metal layer 134, and the top surface of the side portion 132s of the gate dielectric layer 132.

Compared to the method of directly filling the gate trench with metal material, the steps of Figures 3A to 3C are to first conformally deposit the first gate metal material 305 in the first gate trench 300, and then form a planar material 310 to fill the second gate trench 302. Therefore, the gaps remaining in the first gate trench 300 and the second gate trench 302 after forming the first gate metal layer 135 and the planar layer 315 can be reduced, thereby improving the performance of the gate structure. In addition, the deposition process or spin coating process for forming the first gate metal material 305 and the planar material 310 does not require high temperature treatment of the material layer on the substrate 110, thereby reducing heat accumulation in the gate dielectric layer 132 and the work function metal layer 134.

3D , the planarization layer 315 and the side portion 135s of the first gate metal layer 135 are removed to form an opening 320 exposing the bottom 135b of the first gate metal layer 135. Specifically, an etching process may be performed on the planarization layer 315, the side portion 135s, the side portion 134s of the work function metal layer 134, and the side portion 133s of the capping layer 133, wherein the etching process may stop at the interface between the planarization layer 315 and the first gate metal layer 135 to completely remove the planarization layer 315. After the etching process, the top surface of the bottom 135b is flush with the top surfaces of the side 134s and the side 133s, and the top surface of the bottom 135b is lower than the top surface of the side 132s of the gate dielectric layer 132 by a distance T3, so that the width W3 of the opening 320 in a direction parallel to the top surface of the substrate 110 can be greater than the width W1 of the bottom 135b.

3E , a second gate metal layer 136 is formed on the first gate metal layer 135. Specifically, a material of the second gate metal layer 136 may be deposited in the opening 320 and on the interlayer dielectric layer 150 using, for example, a chemical vapor deposition process, and a planarization process may be performed to make the top surface of the second gate metal layer 136 flush with the top surface of the side portion 132s of the gate dielectric layer 132. The second gate metal layer 136 fills the opening 320, so that the width of the second gate metal layer 136 is correspondingly greater than the width of the first gate metal layer 135, so that the bottom surface of the second gate metal layer 136 is sufficient to completely cover the top surface of the first gate metal layer 135. The second gate metal layer 136 can further cover the side 134s of the work function metal layer 134 and the side 133s of the covering layer 133, so that the sidewall of the second gate metal layer 136 contacts the side 132s of the gate dielectric layer 132. In some embodiments, an adhesion layer may be formed between the first gate metal layer 135 and the second gate metal layer 136 to enhance the bonding strength between the second gate metal layer 136 and the first gate metal layer 135 .

Since the second gate metal layer 136 is directly deposited on the first gate metal layer 135 by a deposition process instead of post-treating the first gate metal layer 135 by plasma, for example, to form the second gate metal layer 136 , the risk of damage to the first gate metal layer 135 can be reduced, thereby improving the performance of the gate structure 130 . In addition, the deposition process of the second gate metal layer 136 does not require high temperature treatment of the materials on the substrate 110 , thereby reducing heat accumulation in the gate dielectric layer 132 , the work function metal layer 134 , and the first gate metal layer 135 , thereby avoiding excessive heat accumulation in the gate structure 130 .

After the gate structure 130 of FIG. 3E is completed, a back end of line (BEOL) process may be performed to complete the semiconductor device. For example, a dielectric material may be deposited over the gate structure 130 to thicken the interlayer dielectric layer 150, and an opening for accommodating the conductive material may be etched in the interlayer dielectric layer 150 to form a gate contact 160 on the gate structure 130. Since the hardness of the second gate metal layer 136 is greater than that of the first gate metal layer 135, the second gate metal layer 136 can protect the first gate metal layer 135 during etching of the opening of the gate contact 160, thereby improving the performance of the first gate metal layer 135 as a gate electrode main layer. For example, if a shallower opening for the gate contact 160 and a deeper opening for the source/drain contact (not shown) are simultaneously etched in the interlayer dielectric layer 150, the second gate metal layer 136 can prevent the etchant from damaging the first gate metal layer 135 during etching.

After the gate contact 160 is formed, the gate contact 160 can be electrically connected to the first gate metal layer 135 through the second gate metal layer 136. Since the width of the second gate metal layer 136 is greater than the width of the first gate metal layer 135, the top view area of the second gate metal layer 136 can be correspondingly greater than the top view area of the first gate metal layer 135, so the second gate metal layer 136 can expand the process window of the gate contact 160, thereby improving the flexibility of manufacturing semiconductor devices.

According to the above-mentioned implementation, the manufacturing method of the semiconductor device disclosed in the present invention includes first conformally depositing a first gate metal layer in the gate trench and then filling a flat layer, thereby reducing the voids that may remain in the gate trench and improving the performance of the gate structure. Forming the second gate metal layer by a non-high temperature deposition process can avoid excessive heat accumulation in the gate structure and reduce the risk of damage to the first gate metal layer. The second gate metal layer has a greater hardness and width than the first gate metal layer, so the second gate metal layer can protect the first gate metal layer and expand the process window of the gate contact.

100,200: semiconductor device 110: substrate 112: channel region 120: source/drain region 122: silicide layer 124,126,128: doping region 130: gate structure 131: interface layer 132: gate dielectric layer 133: cap layer 132b,133b,134b,134b-1,135b: bottom 132s,133s,134s,134s-1,135s: side 134: work function metal layer 134-1: first work function metal layer 134-2: Second work function metal layer 135: First gate metal layer 136: Second gate metal layer 140: Gate spacer 150: Interlayer dielectric layer 160: Gate contact 300: First gate trench 302: Second gate trench 305: First gate metal material 310: Flat material 315: Flat layer 320: Opening T1, T2: Thickness T3: Distance W1, W2, W3: Width

FIG. 1 and FIG. 2 illustrate cross-sectional views of a semiconductor device according to some embodiments of the present disclosure. FIG. 3A to FIG. 3E illustrate cross-sectional views of multiple intermediate stages of a semiconductor device manufacturing process according to some embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100:Semiconductor devices

110: Substrate

112: Channel area

120: Source/drain region

122: Silicide layer

124,126: mixed area

130: Gate structure

131: Interface layer

132: Gate dielectric layer

133: Covering layer

132b,133b,134b: bottom

132s,133s,134s: Side

134: Work function metal layer

135: First gate metal layer

136: Second gate metal layer

140: Gate spacer

150: Interlayer dielectric layer

160: Gate contact

T1, T2: thickness

W1,W2: Width

Claims (10)

A method for manufacturing a semiconductor device, comprising: Conformally depositing a gate dielectric layer and a first gate metal layer in a first gate trench to define a second gate trench on the first gate metal layer; Depositing a planar material on the first gate metal layer to fill the second gate trench; Performing a planarization process on the planar material to form a planar layer, wherein a top surface of the planar layer is flush with a top surface of a side portion of the first gate metal layer; Removing the planar layer and the side of the first gate metal layer to form an opening exposing a bottom of the first gate metal layer, wherein a top surface of the bottom of the first gate metal layer is lower than a top surface of the gate dielectric layer; and Depositing a second gate metal layer in the opening to cover the top surface of the bottom of the first gate metal layer, wherein a top surface of the second gate metal layer is flush with the top surface of the gate dielectric layer, and a hardness of the second gate metal layer is greater than a hardness of the first gate metal layer. The manufacturing method as described in claim 1, wherein a width of the opening is greater than a width of the bottom of the first gate metal layer. A method for manufacturing a semiconductor device, comprising: Sequentially forming a gate dielectric layer, a first work function metal layer and a first gate metal layer in a first gate trench to define a second gate trench on the first gate metal layer; Forming a flat layer in the second gate trench, wherein a top surface of the flat layer is flush with a top surface of a side portion of the first gate metal layer, a top surface of a side portion of the first work function metal layer and a top surface of a side portion of the gate dielectric layer; An etching process is performed on the planar layer, the side of the first gate metal layer and the side of the first work function metal layer, wherein after the etching process, a top surface of a bottom of the first gate metal layer is flush with the top surface of the side of the first work function metal layer and lower than the top surface of the side of the gate dielectric layer; and A second gate metal layer is formed on the top surface of the bottom of the first gate metal layer and the top surface of the side of the first work function metal layer, wherein a top surface of the second gate metal layer is flush with the top surface of the side of the gate dielectric layer, and a hardness of the second gate metal layer is greater than a hardness of the first gate metal layer. The manufacturing method as described in claim 3 further comprises: Forming a second work function metal layer between the gate dielectric layer and the first work function metal layer in the first gate trench, wherein a top surface of the second work function metal layer directly contacts the bottom of the first gate metal layer. A semiconductor device, comprising: a gate dielectric layer; a first work function metal layer located above the gate dielectric layer; a first gate metal layer located on the first work function metal layer, wherein a top surface of the first gate metal layer is flush with a top surface of a side portion of the first work function metal layer and is lower than a top surface of a side portion of the gate dielectric layer; and A second gate metal layer covers the top surface of the first gate metal layer and the top surface of the side portion of the first work function metal layer, wherein a top surface of the second gate metal layer is flush with the top surface of the side portion of the gate dielectric layer, and a hardness of the second gate metal layer is greater than a hardness of the first gate metal layer. The semiconductor device as described in claim 5 further comprises: A gate contact directly contacting the second gate metal layer, wherein a bottom surface of the gate contact is higher than a bottom surface of the second gate metal layer. A semiconductor device as described in claim 5, wherein a width of a bottom surface of the second gate metal layer is greater than a width of the top surface of the first gate metal layer, and a side wall of the second gate metal layer directly contacts the side of the gate dielectric layer. The semiconductor device as described in claim 5 further comprises: A second work function metal layer located between the first work function metal layer and the gate dielectric layer, wherein a top surface of the second work function metal layer directly contacts the first work function metal layer. The semiconductor device as described in claim 5 further comprises: A capping layer located between the first work function metal layer and the gate dielectric layer, wherein a top surface of one side of the capping layer is flush with the top surface of the side of the first work function metal layer. A semiconductor device as described in claim 5, wherein a thickness of the first gate metal layer is greater than a thickness of the second gate metal layer.

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