TWI872866B - Data processing circuits, electronic chips, and information processing devices - Google Patents

Abstract

The present invention discloses a data processing circuit, which is used to be integrated in a display driver chip and is configured to receive an input display data from an application processor of an electronic device. The data processing circuit of the present invention is configured to perform at least one data processing on the input display data to generate an output display data, and transmit the output display data to a driver circuit inside the display driver chip. At the same time, the data processing circuit of the present invention caches the output display data in a frame buffer. Thereafter, when the electronic device operates in a low refresh application scenario, the data processing circuit of the present invention can repeatedly read the output display data from the frame buffer and transmit it to the driver circuit, and no longer generates output display data for transmission to the driver circuit by processing the input display data. This can significantly reduce the power consumption of the display driver chip.

Description

Data processing circuits, electronic chips, and information processing devices

The present invention relates to the field of display driver chip (DDIC), and in particular to a data processing circuit integrated into a display driver chip.

It is known that flat panel displays include non-self-luminous flat panel displays and self-luminous flat panel displays, wherein liquid crystal displays are a type of non-self-luminous flat panel displays that have been used for a long time, while organic light-emitting diode (OLED) displays and light-emitting diode (LED) displays are self-luminous flat panel displays that are currently in mainstream applications.

FIG1 is a block diagram of a known OLED display. As shown in FIG1 , the structure of the OLED display 1a mainly includes: an OLED panel 11a and at least one display driver IC (DDIC) 12a, wherein the OLED panel 11a includes M×N OLED pixel units, each of which is composed of a pixel circuit and an OLED element, and each of which includes a driving TFT element, a storage capacitor, and a plurality of switching TFT elements. Electronic engineers who are familiar with the design and manufacture of OLED displays 1a should know that the power consumption of the OLED panel 11a includes refresh power consumption and lighting power consumption, wherein the refresh power consumption is positively correlated with the refresh rate, storage capacitance and the ΔVth of the multiple switching TFT elements, while the lighting power consumption is positively correlated with the luminous efficiency of the OLED element and the Vth of the driving TFT element. Electronic engineers also know that the larger the switching ratio, the lower the leakage current of the switching TFT element in the closed state, which can not only extend the lighting time of the OLED element, but also reduce the lighting power consumption. On the other hand, the higher the carrier mobility of the driving TFT element, the lower its driving voltage, thereby reducing the refresh power consumption.

In recent years, indium gallium zinc oxide (IGZO) thin film transistor (TFT) and low temperature polysilicon (LTPS) thin film transistor are widely used to form the pixel circuit. Among them, LTPS TFT elements have advantages such as high carrier mobility (∼100 cm ² /V.s) and high stability, so they are most suitable for high refresh rate, high PPI OLED display 1a. As shown in FIG1, when the OLED display 1a is integrated into an electronic device such as a smart phone, the display driver chip 12a drives the OLED panel 11a according to an output display data transmitted by an application processor (AP) 2a of the smart phone. At the same time, since LTPS TFT elements usually have a high cut-off current, if the OLED panel 11a includes a pixel circuit composed of LTPS TFT elements, the application processor 2a will transmit display data to the display driver chip 12a at a higher frame rate.

Electronic engineers familiar with the design and manufacture of DDIC must know that the display driver chip 12a has a data processing circuit 121a inside, which is used to perform at least one data processing on the output display data to generate an output display data, so that a driver circuit 122a inside the display driver chip 12a drives the OLED panel 11a for display according to the output display data. FIG. 2 is a circuit block diagram of the data processing circuit shown in FIG. 1. As shown in FIG. 2, usually, the data processing circuit 121a is configured to include: a frame buffer 1211a, a decompression unit 1212a, a data processing unit 1213a, and a data transmission unit (Tcon_Data_Tx) 1214a. In this configuration, after receiving a compressed display data from the application processor 2a via a MIPI interface, the frame buffer 1211a buffers the compressed display data. Then, the decompression unit 1212a reads the compressed display data from the frame buffer 1211a and decompresses the compressed display data into an input display data. It is worth noting that the data processing unit 1213a includes multiple data processing algorithms such as sub-pixel pattern detection (Pattern detection), color management (Color Engine, CE), gamma correction (Gamma correction), frame rate conversion (Frame rate conversion, FRC), etc. Therefore, the data processing unit 1213a performs at least one data processing on the input display data to obtain an output display data, and finally the data transmission unit 1214a transmits the output display data to the driving circuit 122a.

The problem with the prior art is that, since LTPS TFT elements generally have a high cutoff current, if the OLED panel 11a includes a pixel circuit composed of LTPS TFT elements, the application processor 2a will transmit display data to the display driver chip 12a at a higher frame rate to keep the OLED panel 11a at a high refresh rate. However, if the smartphone is operating in a low refresh application scenario (such as reading novels or e-books), the application processor 2a still transmits display data to the display driver chip 12a at a higher frame rate, which will cause the decompression unit 1212a, the data processing unit 1213a, and the data transmission unit 1214a of the data processing circuit 121a to continue to work. In other words, even if the smart phone operates in a low refresh application scenario, the power consumption of the display driver chip 12a cannot be reduced accordingly because the internal data processing circuit 121a is constantly working.

In summary, the existing display driver chip 12a has an obvious defect that the power consumption cannot be reduced accordingly when the electronic device (such as a smart phone) in which it is applied operates in a low refresh application scenario. Therefore, it should be considered to change the design or improve the data processing circuit 121a inside the existing display driver chip 12a to solve the above-mentioned defects of the existing display driver chip 12a.

From the above description, it can be seen that a new data processing circuit is urgently needed in this field.

The main purpose of the present invention is to provide a data processing circuit, which is used to be integrated in a display driver chip and is configured to receive an input display data from an application processor of an electronic device. The data processing circuit of the present invention is configured to perform at least one data processing on the input display data to generate an output display data, and transmit the output display data to a driver circuit inside the display driver chip. At the same time, the data processing circuit of the present invention caches the output display data in a frame buffer. Thereafter, when the electronic device operates in a low refresh application scenario, the data processing circuit of the present invention can repeatedly read the output display data from the frame buffer and transmit it to the driver circuit, and no longer generates output display data for transmission to the driver circuit by processing the input display data. This can significantly reduce the power consumption of the display driver chip.

To achieve the above-mentioned purpose, the present invention proposes an embodiment of the data processing circuit, which is used to be integrated into an electronic chip and includes: A frame buffer for caching a compressed display data; A decompression unit, coupled to the frame buffer, for reading the compressed display data from the frame buffer and decompressing the compressed display data into an input display data; A data processing unit, coupled to the decompression unit, for performing a data processing operation, thereby processing the input display data into an output display data; A first data transmission unit, coupled between the data processing unit and the frame buffer; a second data transmission unit coupled to the frame buffer; a switching unit coupled to the first data transmission unit and the second data transmission unit; and a data output unit coupled to the switching unit; wherein, after the data processing unit completes the data processing operation, the switching unit transmits the output display data to the data output unit, and the first data transmission unit returns the output display data to the frame buffer for caching; wherein, when the data processing unit is configured to stop the data processing operation, the second data transmission unit reads the output display data from the frame buffer, and transmits the output display data to the data output unit through the switching unit.

In one embodiment, the first data transmission unit includes a coder, and the coder is configured to encode the output display data into a coded output display data, and then transmit the coded output display data to the frame buffer for buffering.

In one embodiment, the second data transmission unit includes: a decoder configured to read the encoded output display data from the frame buffer and decode the encoded output display data to obtain the output display data; and a row buffer coupled to the decoder and configured to perform a row buffer processing on the output display data.

In one embodiment, the second data transmission unit includes: a row buffer configured to read the encoded output display data from the frame buffer and perform a row buffer processing on the encoded output display data; and a decoder coupled to the row buffer and configured to read the encoded output display data from the row buffer and decode the encoded output display data to obtain the output display data.

In one embodiment, the electronic chip is any one selected from the group consisting of a display driver chip and a touch and display driver integration (TDDI) chip.

Furthermore, the present invention also proposes an embodiment of an electronic chip, which is used to form a flat panel display together with a display panel, and is characterized in that it contains a data processing circuit, and the data processing circuit includes: A frame buffer, which is used to cache a compressed display data; A decompression unit, coupled to the frame buffer, is used to read the compressed display data from the frame buffer and decompress the compressed display data into an input display data; A data processing unit, coupled to the decompression unit, is used to perform a data processing operation, thereby processing the input display data into an output display data; A first data transmission unit coupled between the data processing unit and the frame buffer; A second data transmission unit coupled to the frame buffer; A switching unit coupled to the first data transmission unit and the second data transmission unit; and A data output unit coupled to the switching unit; wherein, after the data processing unit completes the data processing operation, the switching unit transmits the output display data to the data output unit, and the first data transmission unit returns the output display data to the frame buffer for caching; Wherein, when the data processing unit is configured to stop the data processing operation, the second data transmission unit reads the output display data from the frame buffer, and transmits the output display data to the data output unit through the switching unit.

In one embodiment, the electronic chip is any one selected from the group consisting of a display driver chip and a touch and display driver integration (TDDI) chip.

In one embodiment, the first data transmission unit includes a coder, and the coder is configured to encode the output display data into a coded output display data, and then transmit the coded output display data to the frame buffer for buffering.

In one embodiment, the second data transmission unit includes: a decoder configured to read the encoded output display data from the frame buffer and decode the encoded output display data to obtain the output display data; and a row buffer coupled to the decoder and configured to perform a row buffer processing on the output display data.

In one embodiment, the second data transmission unit includes: a row buffer configured to read the encoded output display data from the frame buffer and perform a row buffer processing on the encoded output display data; and a decoder coupled to the row buffer and configured to read the encoded output display data from the row buffer and decode the encoded output display data to obtain the output display data.

Furthermore, the present invention also provides an embodiment of an information processing device, which is characterized in that it has at least one flat panel display, and the flat panel display includes a display panel and at least one electronic chip of the present invention as described above.

In a feasible embodiment, the information processing device is an electronic device selected from the group consisting of a flat panel display device, a multimedia information display device (KIOSK), a head-mounted display device, a smart TV, a smart phone, a smart watch, a tablet computer, an all-in-one computer, a laptop computer, an in-vehicle entertainment device, a digital camera, and a video door machine.

In order to enable the Review Committee to further understand the structure, features, purpose, and advantages of the present invention, the following are attached with drawings and detailed descriptions of preferred specific embodiments.

FIG. 3 is a block diagram of a flat panel display including a data processing circuit of the present invention. As shown in FIG. 3 , the flat panel display 1 is, for example, an OLED display or a Micro-LED display, and is integrated into an information processing device. In a feasible embodiment, the information processing device may be, but is not limited to, an electronic device from the group consisting of a flat display device, a multimedia information display device (KIOSK), a head-mounted display device, a smart TV, a smart phone, a smart watch, a tablet computer, an all-in-one computer, a notebook computer, an in-vehicle entertainment device, a digital camera, and a video door phone. Moreover, as shown in FIG. 3 , the flat panel display 1 mainly includes: a display panel 11 and at least one electronic chip 12, wherein the electronic chip 12 may be a display driver IC (DDIC) or a touch and display driver integration (TDDI) chip.

As shown in FIG3 , the electronic chip 12 includes a data processing circuit 3 of the present invention. Further, FIG4 is a first circuit block diagram of the data processing circuit shown in FIG3 . As shown in FIG4 , the data processing circuit 3 of the present invention includes: a frame buffer 30, a decompression unit 31, a data processing unit 32, a first data transmission unit including a codec 33, a second data transmission unit including a decoder 34 and a line buffer 35, a switching unit 36, and a data output unit 37 (i.e., Tcon_Data_Tx). According to the design of the present invention, the decompression unit 31 is coupled to the frame buffer 30, the data processing unit 32 is coupled to the decompression unit 31, and the encoder 33 is coupled between the data processing unit 32 and the frame buffer 30. In addition, the decoder 34 and the row buffer 35 (i.e., the second data transmission unit) are coupled to the frame buffer 30, the switching unit 36 (e.g., a multiplexer MUX) is coupled to the first data transmission unit 33 and the second data transmission unit, and the data output unit 37 is coupled to the switching unit 36.

According to this design, after the electronic chip 12 receives a compressed display data from an application processor (AP) 2 of the information processing device through a MIPI interface, the compressed display data is first buffered in the frame buffer 30. As shown in FIG4 , the decompression unit 31 is configured to read the compressed display data from the frame buffer 30 and decompress the compressed display data into an input display data. Furthermore, the data processing unit 32 is configured to perform a data processing operation, thereby processing the input display data into an output display data. In one embodiment, the data processing unit 32 includes multiple data processing algorithms such as sub-pixel pattern detection (Pattern detection), color management (Color Engine, CE), gamma correction (Gamma correction), frame rate conversion (Frame rate conversion, FRC), etc. Therefore, it can be understood that the data processing operation includes performing at least one data processing on the input display data to obtain an output display data, and then transmitting the output display data to the data output unit 37 through the switching unit 36.

To explain in more detail, the data processing circuit 3 of the present invention includes three data transmission paths, wherein the frame buffer 30, the decompression unit 31, the data processing unit 32 and the switching unit 36 constitute a first data transmission path, the data processing unit 32, the encoder 33 and the frame buffer 30 constitute a second data transmission path, and the frame buffer 30, the decoder 34, the row buffer 35, and the switching unit 36 constitute a third data transmission path.

When the application processor 2 has a low refresh rate and the display panel 11 maintains a high refresh rate, the first data transmission path and the second data transmission path are enabled when the application processor 2 sends a new picture (i.e., compressed display data of updated content). In this way, after the data processing unit 32 completes the data processing operation, the switching unit 36 transmits the output display data to the data output unit 37, and the data output unit 37 transmits the output display data to a driving circuit 122 inside the electronic chip 12. At the same time, in the second data transmission path, the encoder 33 encodes the output display data into a coded output display data, and then transmits the coded output display data to the frame buffer 30 for buffering. Afterwards, the first data transmission path is closed and the third data transmission path is enabled. In the third data transmission path, the decoder 34 is configured to read the coded output display data from the frame buffer 30 and decode the coded output display data to obtain the output display data. Next, the row buffer 35 coupled to the decoder 34 is configured to perform a row buffering process on the output display data. Finally, the switching unit 36 reads the output display data from the row buffer 35 and transmits the output display data to the driving circuit 122 through the data output unit 37.

Simply put, when the information processing device operates in a low refresh application scenario (such as reading novels or e-books) but the display panel 11 is controlled at a high refresh rate, the first data transmission path and the second data transmission path are only enabled when the application processor 2 transmits a new picture, and the third data transmission path is enabled when the data processing unit 32 is configured to stop the data processing operation (i.e., the first data transmission path is disabled), thereby repeatedly reading the output display data from the frame buffer 30, and transmitting the output display data to the drive circuit 122 through the switching unit 36 and the data output unit 37. In this way, when the application processor 2 sends the input display data at a higher frame rate when the information processing device operates in a low refresh application scenario, the power consumption of the electronic chip 12 can be significantly reduced.

On the other hand, when the application processor 2 is refreshed at a high rate and the display panel 11 maintains a high refresh rate, since the application processor 2 continuously sends new pictures, the second data transmission path and the third data transmission path remain closed, while the first data transmission path remains enabled.

Furthermore, FIG5 is a second circuit block diagram of the data processing circuit shown in FIG3. Comparing FIG5 with FIG4, it can be seen that in the second data transmission unit, the row buffer 35 is configured to read the encoded output display data from the frame buffer 30, and perform a row buffer processing on the encoded output display data. In addition, the decoder 34 is coupled to the row buffer 35, and is configured to read the encoded output display data from the row buffer 35, and decode the encoded output display data to obtain the output display data. In other words, the circuit positions of the decoder 34 and the row buffer 35 are swapped with each other.

Thus, the above description has completely and clearly described a data processing circuit of the present invention; and, from the above description, it can be known that the present invention has the following advantages:

(1) The present invention discloses a data processing circuit, which is used to be integrated into a display driver chip and is configured to receive an input display data from an application processor of an electronic device. The data processing circuit of the present invention is configured to perform at least one data processing on the input display data to generate an output display data, and transmit the output display data to a driver circuit inside the display driver chip. At the same time, the data processing circuit of the present invention caches the output display data in a frame buffer. Thereafter, when the electronic device operates in a low refresh application scenario, the data processing circuit of the present invention can repeatedly read the output display data from the frame buffer and transmit it to the driver circuit, and no longer generates output display data for transmission to the driver circuit by processing the input display data. This can significantly reduce the power consumption of the display driver chip.

(2) The present invention also discloses an electronic chip, which is a DDIC or a TDDI, used together with a display panel to form a flat panel display; and, its characteristic is that it contains the data processing circuit of the present invention as described above.

(3) Furthermore, the present invention also discloses an information processing device, which is characterized in that it has at least one flat panel display, and the flat panel display includes a display panel and at least one electronic chip of the present invention as described above.

It must be emphasized that what is disclosed in the above-mentioned case is a preferred embodiment. Any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by people familiar with the art do not deviate from the scope of the patent rights of this case.

In summary, this case shows that its purpose, means and effects are very different from the known technology, and it is the first invention that is practical and indeed meets the patent requirements for invention. We sincerely request the review committee to examine this carefully and grant a patent as soon as possible to benefit the society. This is our utmost prayer.

1a: OLED display 11a: OLED panel 12a: display driver chip 121a: data processing circuit 1211a: frame buffer 1212a: decompression unit 1213a: data processing unit 1214a: data transmission unit 122a: driver circuit 2a: application processor 1: flat panel display 11: display panel 12: electronic chip 122: driver circuit 2: application processor 3: data processing circuit 30: frame buffer 31: decompression unit 32: data processing unit 33: encoder 34: decoder 35: Row Buffer 36: Switching Unit 37: Data Output Unit

FIG. 1 is a block diagram of a known OLED display; FIG. 2 is a circuit block diagram of the data processing circuit shown in FIG. 1; FIG. 3 is a block diagram of a flat panel display including a data processing circuit of the present invention; FIG. 4 is a first circuit block diagram of the data processing circuit shown in FIG. 3; and FIG. 5 is a second circuit block diagram of the data processing circuit shown in FIG. 3.

122:Drive circuit

2: Application processor

3: Data processing circuit

30: Frame buffer

31: Decompression unit

32: Data processing unit

33: Encoder

34:Decoder

35: Line Buffer

36: Switching unit

37: Data output unit

Claims (5)

A data processing circuit is used for integration in an electronic chip, and includes: A frame buffer for buffering a compressed display data from an application processor at a first refresh rate; A decompression unit coupled to the frame buffer for reading the compressed display data from the frame buffer and decompressing the compressed display data into an input display data; A data processing unit coupled to the decompression unit for performing a data processing operation to process the input display data into an output display data; A coder coupled between the data processing unit and the frame buffer, used to encode the output display data into a coded output display data, and return the coded output display data to the frame buffer for caching; A data transmission unit coupled to the frame buffer and comprising a decoder and a row buffer in cascade, the decoder is used to decode the coded output display data to obtain the output display data, and the row buffer is used to perform a row buffer processing on the output display data or the coded output display data; A switching unit coupled to the data processing unit and the data transmission unit; and A data output unit is coupled to the switching unit and is used to provide the output display data to a display panel at a second refresh rate; Wherein, when the first refresh rate is lower than the second refresh rate, the data processing unit is configured to stop the data processing operation, and the data transmission unit transmits the output display data to the data output unit through the switching unit. A data processing circuit as described in claim 1, wherein the electronic chip is any one selected from the group consisting of a display driver chip and a touch and display driver integration (TDDI) chip. An electronic chip, which is used to form a flat panel display together with a display panel, is characterized in that it contains a data processing circuit, and the data processing circuit includes: A frame buffer, which is used to cache a compressed display data from an application processor according to a first refresh rate; A decompression unit, coupled to the frame buffer, is used to read the compressed display data from the frame buffer and decompress the compressed display data into an input display data; A data processing unit, coupled to the decompression unit, is used to perform a data processing operation, thereby processing the input display data into an output display data; A coder coupled between the data processing unit and the frame buffer, used to encode the output display data into a coded output display data, and return the coded output display data to the frame buffer for caching; A data transmission unit coupled to the frame buffer and comprising a decoder and a row buffer in cascade, the decoder is used to decode the coded output display data to obtain the output display data, and the row buffer is used to perform a row buffer processing on the output display data or the coded output display data; A switching unit coupled to the data processing unit and the data transmission unit; and A data output unit is coupled to the switching unit and is used to provide the output display data to the display panel at a second refresh rate; Wherein, when the first refresh rate is lower than the second refresh rate, the data processing unit is configured to stop the data processing operation, and the data transmission unit transmits the output display data to the data output unit through the switching unit. An electronic chip as described in claim 3, wherein the electronic chip is any one selected from the group consisting of a display driver chip and a touch and display driver integration (TDDI) chip. An information processing device is characterized in that it has at least one flat panel display, and the flat panel display includes a display panel and at least one electronic chip as described in any one of claim 3 to claim 4.

Images