TWI872761B - Sequential transmission method for i2c with low pin count and i2c transmission system using the same - Google Patents

Abstract

The present invention relates to a sequential transmission method for I2C with low pin count and an I2C transmission system using the same. The method includes: providing a plurality of I2C slave devices and a I2C master device, wherein the plurality of I2C slave devices and the I2C master device is electrically connected to a I2C serial bus; interrupt request (IRQ) pins of the I2C slave devices are coupled to an interrupt input pin of the I2C master device; when a specific I2C slave device of the I2C slave devices asks an IRQ, an IRQ pin of the specific I2C slave device output a voltage level corresponding to the regulation of the specific I2C slave device; determining which one of the plurality of I2C slave devices asks IRQ according to an voltage level of the interrupt input pin of the I2C master device.

Description

Low-pin I2C serial transmission method and low-pin I2C transmission system using the same

The present invention relates to an I2C transmission technology, and in particular to a low-pin I2C serial transmission method and a low-pin I2C transmission system using the same.

I2C (Inter-Integrated Circuit) is a serial communication protocol used to connect different digital electronic components, such as microcontrollers, sensors, displays, etc., to achieve data exchange. The I2C protocol was developed by Philips (now NXP) in 1982. Its main feature is that it uses two lines (a data line SDA and a clock line SCL) for communication and supports multiple slave devices connected to the same set of lines.

FIG1 is a schematic diagram of an I2C transmission method of the prior art. Please refer to FIG1 , in which an I2C serial transmission master controller 101 and a plurality of I2C serial transmission slave devices 102 are shown. The basic operation mode of the I2C communication protocol is that the I2C serial transmission master controller 101 initiates communication and selects the I2C serial transmission slave device 102 to be transmitted with it. The I2C serial transmission master controller 101 generates a clock signal to control the rhythm of data transmission. The data transmission is carried out in the form of a bit string. The I2C serial transmission slave device 102 reads or transmits data under the triggering of the clock. The end of communication is indicated by the master controller generating a stop condition to indicate the end of transmission.

When the I2C serial transmission slave device 102 wants to send an interrupt to the I2C serial transmission master controller 101, it needs to use a specific pin, usually called an "interrupt input pin", to notify the I2C serial transmission master controller 101. However, such a design has the following disadvantages:

1. Additional hardware pin requirements: The I2C serial transmission master controller 101 requires additional hardware pin support, which may cause inconvenience for some applications with limited pins.

2. Interrupt conflicts: When multiple slave devices need to send interrupts, interrupt conflicts may occur, and additional logical processing is required to manage the priority of these interrupts.

The present invention provides a low-pin I2C serial transmission method and a low-pin I2C transmission system using the method, which are used to change the interrupt design between an I2C serial transmission master device and an I2C serial transmission slave device, so that the I2C serial transmission master device only needs one interrupt input pin to connect multiple I2C serial transmission slave devices.

The embodiment of the present invention provides a low-pin I2C transmission system, which includes an I2C serial transmission data cable, a plurality of I2C serial transmission slave devices and an I2C serial transmission master device. The I2C serial transmission data cable includes an I2C serial transmission data line and an I2C serial transmission clock line. Each of the I2C serial transmission slave devices includes an I2C serial transmission data pin, an I2C serial transmission clock pin, and an interrupt request pin, wherein the I2C serial transmission data pin of each of the I2C serial transmission slave devices is coupled to the I2C serial transmission data line of the I2C serial transmission data cable, and the I2C serial transmission clock pin of each of the I2C serial transmission slave devices is coupled to the I2C serial transmission clock line of the I2C serial transmission data cable. An I2C serial transmission master device includes an I2C serial transmission data pin, an I2C serial transmission clock pin, and an interrupt input pin, wherein the I2C serial transmission data pin of the I2C serial transmission master device is coupled to the I2C serial transmission data line of the I2C serial transmission data cable, and the I2C serial transmission clock pin of the I2C serial transmission master device is coupled to the I2C serial transmission clock line of the I2C serial transmission data cable, wherein each The interrupt request pins of the I2C sequence transmission slave devices are coupled to the interrupt input pins of the I2C sequence transmission master device, wherein the interrupt request pins of each of the I2C sequence transmission slave devices respectively output different voltages when making an interrupt request, wherein the I2C sequence transmission master device determines whether each of the I2C sequence transmission slave devices makes an interrupt request according to the voltage size received by the interrupt input pins of the I2C sequence transmission master device.

According to the preferred embodiment of the present invention, the low-pin I2C transmission system further includes a first pull-up resistor, the first end of the first pull-up resistor is coupled to a power voltage, and the second end of the first pull-up resistor is coupled to the I2C sequence transmission data line of the I2C sequence transmission data line. In another preferred embodiment, the low-pin I2C transmission system further includes a second pull-up resistor, the first end of the second pull-up resistor is coupled to a power voltage, and the second end of the second pull-up resistor is coupled to the I2C sequence transmission clock line of the I2C sequence transmission data line. In another preferred embodiment, when each of the I2C sequence transmission slave devices does not make an interrupt request, the interrupt request pin of each of the I2C sequence transmission slave devices is in a high impedance state. In another preferred embodiment, the interrupt input pin of the I2C serial transmission master device is an analog-to-digital conversion input channel pin.

The embodiment of the present invention provides a method for low-pin I2C serial transmission, which includes: providing a plurality of I2C serial transmission slave devices; providing an I2C serial transmission master device, wherein the I2C serial transmission slave devices and the I2C serial transmission master device are electrically connected to an I2C serial transmission cable; coupling the interrupt request pin of each of the I2C serial transmission slave devices to the I2C serial transmission master device; An interrupt input pin of the transmission master device; when a specific I2C serial transmission slave device among each of the I2C serial transmission slave devices makes an interrupt request, the interrupt request pin of the specific I2C serial transmission slave device outputs a voltage corresponding to the specification of the specific I2C serial transmission slave device; according to the voltage size of the interrupt input pin of the I2C serial transmission master device, it is judged whether each of the I2C serial transmission slave devices makes an interrupt request.

In summary, the embodiment of the present invention allows the interrupt request pins of multiple I2C serial transmission slave devices to be coupled to the same interrupt input pin of the I2C serial transmission master device, and each interrupt request pin of the I2C serial transmission slave device outputs a different voltage when requesting an interrupt. Therefore, the I2C serial transmission master device can determine which I2C serial transmission slave device has issued an interrupt request based on the voltage received by the interrupt input pin. Furthermore, in another preferred embodiment, if multiple devices send interrupt requests at the same time, the I2C serial transmission master device will first process the interrupt of the I2C serial transmission slave device with a lower interrupt request voltage.

In order to further understand the technology, means and effects of the present invention, reference may be made to the following detailed description and accompanying drawings, so that the purpose, features and concepts of the present invention can be thoroughly and specifically understood. However, the following detailed description and accompanying drawings are only used for reference and explanation of the implementation of the present invention, and are not used to limit the present invention.

Reference will now be made in detail to exemplary embodiments of the present invention, which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and the specification to refer to the same or similar components. In addition, the exemplary embodiments are only one of the implementation methods of the design concept of the present invention, and the following examples are not intended to limit the present invention.

FIG2 is a system block diagram of a low-pin I2C transmission system of a preferred embodiment of the present invention. Referring to FIG2 , the low-pin I2C transmission system includes an I2C serial transmission master device 201, a plurality of I2C serial transmission slave devices 202, and an I2C serial transmission data cable, wherein the I2C serial transmission data cable includes an I2C serial transmission data line SDA and an I2C serial transmission clock line SCK. The I2C serial transmission data pin of each I2C serial transmission slave device 202 and the I2C serial transmission master device 201 is coupled to the I2C serial transmission data line SDA, and the I2C serial transmission clock pin of each I2C serial transmission slave device 202 and the I2C serial transmission master device 201 is coupled to the I2C serial transmission clock line SCK. In addition, in this embodiment, each I2C serial transmission slave device 202 has an interrupt request pin IRQ. More specifically, the interrupt request pin IRQ of each I2C serial transmission slave device 202 is coupled to the same interrupt input pin IRI of the I2C serial transmission master device 201. In addition, in this embodiment, the I2C serial transmission data line SDA and the I2C serial transmission timing pulse line SCK are respectively coupled to the first resistor R1 and the second resistor R2 as pull-up resistors for pulling the I2C serial transmission data line SDA and the I2C serial transmission timing pulse line SCK to the power voltage VDD.

When performing general transmission, the transmission is initiated by the I2C serial transmission master device 201, and according to the I2C format, the specified I2C serial transmission slave device 202 outputs or requests data. In addition, in this embodiment, the interrupt request pin IRQ of each I2C serial transmission slave device 202 is coupled to the same interrupt input pin IRI of the I2C serial transmission master device 201. In the prior art, the interrupt request pin IRQ of each I2C serial transmission slave device 202 is coupled to a different pin of the I2C serial transmission master device 201, which is generally a general-purpose input/output (GPIO) pin. The reason is that in the prior art, the interrupt requests sent from the I2C serial transmission slave device 202 are all logically low voltage. If the interrupt request pins IRQ of multiple I2C serial transmission slave devices 202 are coupled to the same pin of the I2C serial transmission master device 201, it is impossible to determine which I2C serial transmission slave device 202 issued the interrupt request, so an interrupt conflict will occur.

However, in this embodiment, the interrupt request pin IRQ of each I2C serial transmission slave device 202 is coupled to the same interrupt input pin IRI of the I2C serial transmission master device 201. And the interrupt request pin IRQ of each I2C serial transmission slave device 202 will output a different voltage when making an interrupt request. The interrupt input pin IRI of the I2C serial transmission master device 201 has a circuit that can distinguish voltage, such as an analog-to-digital converter (ADC).

Most microprocessors (MCUs) in the I2C serial transmission master device 201 have built-in analog-to-digital converters to convert the analog voltage on the analog-to-digital converter input channel pin (ADC input channel pin) into digital values, such as 12-bit SAR-ADC, which usually has an accuracy of about 10 bits. In order to avoid misjudgment, this 10-bit accuracy is further divided into 2^7 = 128 intervals. For example, the reference voltage of the analog-to-digital converter is 3.3V, which is divided into 128 intervals, and the range of each interval is approximately equal to 3.3V/128 = 25.78mV. Assuming that the input ADC voltage can be made to fall approximately in the middle of each interval, the microprocessor in the I2C serial transmission master device 201 can easily identify the conversion values of the ADCs in different intervals.

Furthermore, it is assumed that each I2C serial transmission slave device 202 has a pin that can enable or disable the output voltage control and can output a fixed and unique voltage (the output voltage value of each I2C serial transmission slave device 202 is different, but all fall roughly in the middle of each range described in the previous paragraph, for example: 25.78mV/2 * (2N+1), N = 0, 1, 2, …, 127, that is, 12.89mV, 38.67mV, 64.45mV, …, 3.287V). In general, if the I2C serial transmission slave device 202 does not detect any changes (such as touch, direction axis or acceleration/deceleration changes) and needs the I2C serial transmission master device 201 to read data, the interrupt request pin IRQ outputs a floating voltage (floating, or high impedance). On the contrary, if the I2C serial transmission slave device 202 detects any abnormality, the interrupt request pin IRQ can output a fixed and unique voltage corresponding to the I2C serial transmission slave device 202 as a specific interrupt request to the I2C serial transmission master device 201, so as to notify the I2C serial transmission master device 201 to access the I2C serial transmission slave device 202.

Therefore, as shown in FIG. 2 , it is only necessary to utilize an analog-to-digital conversion input channel pin (ADC input channel pin) of the microprocessor in the I2C serial transmission master device 201 to couple the output voltage pins of each I2C serial transmission slave device 202 to the same interrupt input pin IRI of the I2C serial transmission master device 201. When the I2C serial transmission master device 201 finds that the analog-to-digital conversion value corresponds to a fixed voltage value output by a certain I2C serial transmission slave device 202, the I2C serial transmission master device 201 can send I2C signals (SCL and SDA) to read data from the I2C serial transmission slave device 202. After the data of the I2C serial transmission slave device 202 is read, the I2C serial transmission slave device 202 disables the voltage output on the interrupt request pin IRQ and restores it to a normal floating voltage output state.

In another preferred embodiment, if multiple I2C serial transmission slave devices 202 send voltages from the interrupt request pin IRQ during the same period, at this time, since the low voltage interrupt will be pulled up by the high voltage interrupt voltage, the interrupt input pin IRI of the I2C serial transmission master device 201 will receive the voltage of the I2C serial transmission slave device 202 that outputs the highest voltage. Therefore, the I2C serial transmission master device 201 will first perform the interrupt access processing corresponding to the I2C serial transmission slave device 202 with the highest voltage, and then perform the interrupt access processing of the I2C serial transmission slave device 202 in order from high to low voltage. Thereby, the interruption conflict in the previous technology is also solved.

From the above-mentioned embodiments, it can be seen that, through the interrupt operation mechanism of the above-mentioned embodiments, the I2C serial transmission master device 201 does not need to have multiple general-purpose input/output (GPIO) pins or interrupt input pins to receive the interrupt requirements sent by each I2C serial transmission slave device 202, so as to save the number of general-purpose input/output (GPIO) pins or interrupt input pins (pin counts) of the I2C serial transmission master device 201.

According to the above-mentioned preferred embodiment of the low-pin I2C transmission system, a method of low-pin I2C serial transmission can be summarized. FIG3 is a flow chart of the method of low-pin I2C serial transmission of a preferred embodiment of the present invention. Referring to FIG3, the method of low-pin I2C serial transmission includes the following steps:

Step S301: Start.

Step S302: Provide a plurality of I2C serial transmission slave devices.

Step S303: Provide an I2C serial transmission master device, wherein the I2C serial transmission slave device and the I2C serial transmission master device are electrically connected to an I2C serial transmission cable, and each of the I2C serial transmission slave devices has an interrupt request pin coupled to an interrupt input pin of the I2C serial transmission master device.

Step S304: Determine the voltage of the IRI pin of the I2C serial transmission master device. In this way, determine whether the above-mentioned multiple I2C serial transmission slave devices have issued an interrupt request, and determine which of the above-mentioned multiple I2C serial transmission slave devices has issued an interrupt request based on the voltage. Since each I2C serial transmission slave device 202 has a corresponding set of fixed voltages, when the interrupt request pin IRQ of one of the specific I2C serial transmission slave devices 202 makes an interrupt request, the interrupt request pin IRQ of the above-mentioned specific I2C serial transmission slave device 202 outputs a voltage corresponding to the specification of the above-mentioned specific I2C serial transmission slave device 202.

Step S305: Determine whether each of the I2C serial transmission slave devices has made an interrupt request according to the voltage level of the interrupt input pin of the I2C serial transmission master device.

In summary, the embodiment of the present invention allows the interrupt request pins of multiple I2C serial transmission slave devices to be coupled to the same interrupt input pin of the I2C serial transmission master device, and each interrupt request pin of the I2C serial transmission slave device outputs a different voltage when requesting an interrupt. Therefore, the I2C serial transmission master device can determine which I2C serial transmission slave device has issued an interrupt request based on the voltage received by the interrupt input pin. Furthermore, in another preferred embodiment, if multiple devices send interrupt requests at the same time, the I2C serial transmission master device first processes the interrupt of the I2C serial transmission slave device with a higher interrupt request voltage.

It should be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes thereto will be suggested to those skilled in the art and are to be included within the spirit and scope of the present application and the scope of the appended claims.

101: I2C serial transmission master controller 102: I2C serial transmission slave device 201: I2C serial transmission master device 202: I2C serial transmission slave device SDA: I2C serial transmission data line SCK: I2C serial transmission clock line SCK: Each I2C serial transmission slave device 202 and I2C serial transmission master device IRQ: I2C serial transmission slave device 202 interrupt request pin IRI: I2C serial transmission master device 201 interrupt input pin R1: first resistor R2: second resistor VDD: power supply voltage S301~S305: process steps of the low-pin I2C serial transmission method of a preferred embodiment of the present invention

The accompanying drawings are provided to enable a person with ordinary knowledge in the art to which the present invention belongs to further understand the present invention, and are incorporated into and constitute a part of the specification of the present invention. The accompanying drawings show exemplary embodiments of the present invention, and are used together with the specification of the present invention to explain the principles of the present invention.

FIG. 1 is a schematic diagram of an I2C transmission method in the prior art.

FIG. 2 is a system block diagram of a low-pin I2C transmission system according to a preferred embodiment of the present invention.

FIG. 3 is a flow chart showing a method for low pin I2C serial transmission according to a preferred embodiment of the present invention.

S301~S305: Process steps of the method of low-pin I2C serial transmission of a preferred embodiment of the present invention

Claims (8)

A low-pin I2C transmission system, comprising: an I2C serial transmission data cable, including an I2C serial transmission data line and an I2C serial transmission clock line; a plurality of I2C serial transmission slave devices, wherein each of the I2C serial transmission slave devices comprises an I2C serial transmission data pin, an I2C serial transmission clock pin and an interrupt request pin, wherein the I2C serial transmission data pin of each of the I2C serial transmission slave devices is coupled to the I2C serial transmission data line of the I2C serial transmission data cable, and the I2C serial transmission clock pin of each of the I2C serial transmission slave devices is coupled to the I2C serial transmission clock line of the I2C serial transmission data cable; and An I2C serial transmission master device includes an I2C serial transmission data pin, an I2C serial transmission clock pin, and an interrupt input pin, wherein the I2C serial transmission data pin of the I2C serial transmission master device is coupled to the I2C serial transmission data line of the I2C serial transmission data cable, and the I2C serial transmission clock pin of the I2C serial transmission master device is coupled to the I2C serial transmission clock line of the I2C serial transmission data cable, wherein the interrupt request pin of each of the I2C serial transmission slave devices is coupled to the interrupt input pin of the I2C serial transmission master device, Wherein, the interrupt request pins of each of the I2C serial transmission slave devices output different voltages when making an interrupt request, Wherein, the I2C serial transmission master device determines whether each of the I2C serial transmission slave devices makes an interrupt request based on the voltage size received by the interrupt input pin of the I2C serial transmission master device. The low-pin I2C transmission system according to claim 1 further includes: A first pull-up resistor including a first end and a second end, wherein the first end of the first pull-up resistor is coupled to a power voltage, and the second end of the first pull-up resistor is coupled to the I2C serial transmission data line of the I2C serial transmission data cable. The low-pin I2C transmission system according to claim 1 further includes: A second pull-up resistor, including a first end and a second end, wherein the first end of the second pull-up resistor is coupled to a power voltage, and the second end of the second pull-up resistor is coupled to the I2C serial transmission clock line of the I2C serial transmission data cable. According to the low-pin I2C transmission system described in claim 1, when each of the I2C serial transmission slave devices does not make an interrupt request, the interrupt request pin of each of the I2C serial transmission slave devices is in a high-impedance state. According to the low-pin I2C transmission system described in claim 1, the interrupt input pin of the I2C serial transmission master device is an analog-to-digital conversion input channel pin. A method for low-pin I2C serial transmission, comprising: Providing a plurality of I2C serial transmission slave devices; Providing an I2C serial transmission master device, wherein the I2C serial transmission slave devices and the I2C serial transmission master device are electrically connected to an I2C serial transmission cable; Coupling an interrupt request pin of each of the I2C serial transmission slave devices to an interrupt input pin of the I2C serial transmission master device; When a specific I2C serial transmission slave device among each of the I2C serial transmission slave devices makes an interrupt request, the interrupt request pin of the specific I2C serial transmission slave device outputs a voltage corresponding to the specification of the specific I2C serial transmission slave device; According to the voltage level of the interrupt input pin of the I2C serial transmission master device, it is determined whether each of the I2C serial transmission slave devices has made an interrupt request. According to the method of low-pin I2C serial transmission described in claim 6, when each of the I2C serial transmission slave devices does not make an interrupt request, the interrupt request pin of each of the I2C serial transmission slave devices is in a high impedance state. According to the method of low-pin I2C serial transmission described in claim 6, the interrupt input pin of the I2C serial transmission master device is an analog-to-digital conversion input channel pin.

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