TWI871815B - Method of controlling display panel and related control circuit - Google Patents

Abstract

A method used for a control circuit for controlling a display panel includes steps of: determining whether there is an input video data received at a predetermined time; outputting an output video data and a clock signal having a first frequency to the display panel when determining that there is an input video data received at the predetermined time; and stopping outputting the output video data but outputting the clock signal having a second frequency to the display panel when determining that there is no input video data received at the predetermined time. Wherein, the second frequency is higher than the first frequency.

Description

Method for controlling display panel and control circuit thereof

The present invention refers to a method for controlling a display panel and a related control circuit, in particular, a method for receiving input video data through a display port (DP) interface or an embedded display port (eDP) interface to control a light-emitting diode (LED) panel, and a related control circuit.

Different from the mainstream Mobile Industry Processor Interface (MIPI), there is no vertical synchronization signal in the protocol of the embedded Display Port (eDP) interface or Display Port (DP) interface (hereinafter referred to as eDP/DP interface). Therefore, after the data of the previous frame is completely transmitted, the video provider unit can start transmitting the data of the next frame to the display driver circuit at any time. Therefore, based on the reception of video data, the display driver circuit should be synchronized with the video provider unit at any time.

In a conventional liquid crystal display (LCD) panel, since the backlight is continuously turned on, when the video data arriving through the eDP/DP interface is irregular, the display driver circuit can delay the video data accordingly, and then refresh the panel with the video data at a predetermined time point, so that the video data can be well synchronized and not affected by the irregular transmission on the eDP/DP interface.

For an OLED panel, light is generated by the OLED in the pixel instead of the backlight module, where the OLED's light emission is controlled by a light pulse signal, and the brightness is determined by the duty cycle of the light pulse signal. However, when the eDP/DP interface is used to transmit video data, the display driver circuit should be equipped with sufficient column buffers or frame buffers (such as static random access memory (SRAM)) to temporarily store video data to maintain an accurate light duty cycle when the video data refreshes the panel.

Therefore, when an OLED panel uses an eDP/DP interface to transmit video data, it needs to have sufficient column buffers or frame buffers to meet the above control requirements. The required column/frame buffers often occupy a large area, thus increasing circuit costs.

Therefore, the main purpose of the present invention is to propose a method for controlling a light-emitting diode (LED) panel to solve the above problems.

An embodiment of the present invention discloses a method for a control circuit for controlling a display panel. The method comprises the following steps: determining whether an input video data is received within a predetermined time; when determining that an input video data is received within the predetermined time, outputting an output video data and a clock signal having a first frequency to the display panel; and when determining that no input video data is received within the predetermined time, stopping outputting the output video data and outputting the clock signal having a second frequency to the display panel. The second frequency is higher than the first frequency.

Another embodiment of the present invention discloses a control circuit for controlling a display panel. The control circuit includes a detection circuit, a data output driver and a light control circuit. The detection circuit is used to determine whether an input video data is received within a predetermined time. The data output driver is coupled to the detection circuit and is used to output an output video data to the display panel when the detection circuit determines that an input video data is received within the predetermined time, and stop outputting the output video data when the detection circuit determines that no input video data is received within the predetermined time. The light control circuit is coupled to the detection circuit, and is used to output a clock signal with a first frequency to the display panel when the detection circuit determines that an input video data is received within the predetermined time, and output the clock signal with a second frequency to the display panel when the detection circuit determines that no input video data is received within the predetermined time. The second frequency is higher than the first frequency.

Another embodiment of the present invention discloses a method for a control circuit for controlling a display panel. The method comprises the following steps: receiving a first frame of video data; outputting the first frame of video data and a light pulse signal having a first duty cycle to the display panel; after the first frame of video data is completely received, determining whether a second frame of video data is received within a predetermined time; and when determining that the second frame of video data is not received within the predetermined time, outputting the light pulse signal having the first duty cycle to the display panel without outputting any video data.

Another embodiment of the present invention discloses a control circuit for controlling a display panel. The control circuit includes a detection circuit, a data output driver, and a light control circuit. The detection circuit is used to receive a first frame of video data, and after the first frame of video data is completely received, determine whether a second frame of video data is received within a predetermined time. The data output driver is coupled to the detection circuit and is used to output the first frame of video data to the display panel. The light control circuit is coupled to the detection circuit and is used to output a light pulse signal having a first duty cycle to the display panel. When the detection circuit determines that the second frame of video data is not received within the predetermined time, the light control circuit is used to output the light pulse signal with the first duty cycle, and the data output driver does not output any video data.

BS: Blank start signal

BE: Blank end signal

20: Display system

200:Host

202: Display driver circuit

204: Display panel

212: Detection circuit

214: Luminescence control circuit

216: Data output driver

218: Gate control circuit

220: Timing controller

230: column buffer

F1,F2,F3,F4: Frame

Vsync: vertical synchronization signal

Hsync: horizontal synchronization signal

GOA: Gate control signal

MUX1~MUX3: multiplexing control signal

VOUT: Output video data

EM_CLK: luminescence control clock

EM_STV: Luminous pulse signal

60: Process

600~608: Steps

Figure 1 is a schematic diagram of the typical packet format of the eDP/DP interface.

Figure 2 is a schematic diagram of the display system of the first embodiment of the present invention.

Figures 3A and 3B are timing diagrams showing the operation of the driver circuit.

Figures 4A and 4B are timing diagrams showing the operation of the drive circuit according to an embodiment of the present invention.

Figures 5A and 5B are waveform diagrams showing the detailed implementation of the drive circuit in the normal scanning mode and the fast scanning mode according to the embodiment of the present invention.

Figure 6 is a flow chart of the process of the first embodiment of the present invention.

Figures 7A and 7B are timing diagrams showing the operation of the drive circuit according to an embodiment of the present invention.

FIG1 is a schematic diagram of a typical packet format of an embedded Display Port (eDB) interface or Display Port (DP) interface (eDP/DP interface). As shown in FIG1, the timing of the eDP/DP packet is defined by a Blanking Start (BS) signal and a Blanking End (BE) signal. Each Blanking Start signal is used to indicate a row of time, and part of the row of time in front is a blank row, which can be left unused or used to send commands. These row times can be defined as a porch. During the porch period, only the Blanking Start signal and part of the commands are transmitted, but the Blanking End signal is not transmitted. The video data is transmitted after the porch period ends. During the data transmission period, each row of time is started by a Blanking Start signal, followed by a Blanking End signal, and then a row of video data is transmitted. When a frame of video data is transmitted, it means the entire transmission period is over.

In the Mobile Industry Processor Interface (MIPI), the timing is defined by the transmission of the vertical synchronization signal and the horizontal synchronization signal, so the display driver circuit can easily know the start and end of each frame of data. In contrast, in the eDP/DP packet, the timing is only defined by the blank start signal and the blank end signal, and the display driver circuit may not know when the corridor ends and when the video data starts to be transmitted. Therefore, when the display driver circuit is configured to drive a light-emitting diode (LED) panel (such as an organic LED (OLED) panel), if the frame rate is variable, the corridor period length in the eDP/DP packet is also variable. Therefore, the display driver circuit needs to handle data transmission and lighting control well when video data arrives irregularly.

FIG. 2 is a schematic diagram of a display system 20 of an embodiment of the present invention. The display system 20 includes a host 200, a display driver circuit 202, and a display panel 204. The host 200 can be used as a video providing unit to generate video/image content and output video data to the display driver circuit 202. The host 200 can be a system on chip (SoC) or any other type of main processing circuit, which is provided with an operating system (such as Android) for installing various applications, but is not limited thereto. The display panel 204 can be an organic light-emitting diode panel, a mini-LED panel, a micro-LED panel, and the like, which utilizes the light-emitting elements contained in the pixels to emit light.

The display driver circuit 202 includes a detection circuit 212, a light control circuit 214, a data output driver 216, a gate control circuit 218, a timing controller 220, and one or more row buffers 230. The detection circuit 212 is used to detect and determine whether any video data is received within a predetermined time. In one embodiment, the detection circuit 212 may include a receiver or be implemented by a receiver, and the receiver may be an eDP/DP receiver, which is used to receive input video data from the host 200 and transmitted through the eDP/DP interface. The light control circuit 214 is used to output light control signals, such as light pulse signals and light control clocks, which can be transmitted to a gate-on-array (GOA) circuit (not shown) on the display panel 204 to achieve light control. The gate control circuit 218 is used to output gate control signals, such as gate pulse signals and gate control clocks, which can also be transmitted to the gate drive array circuit. The data output driver 216 is also called a source driver and can be used to output video data voltages to target pixels on the display panel 204. The timing controller 220 is used to control the output timing of the light/gate control signal and the data voltage according to the reception of the input video data. The column buffer 230 can be used to store the received video data before the video data is output. The display driver circuit 202 can be implemented in an integrated circuit (IC) in a chip, also known as a display driver integrated circuit (DDIC).

Figures 3A and 3B are timing diagrams of the operation of the display driver circuit 202, which illustrate the input video data, a vertical synchronization signal Vsync, and the output timing of the video data. The display driver circuit 202 can receive a series of frames (F1, F2, F3, etc.) of video data from the host 200, and output the video data to refresh the display panel 204. The received video data frame must comply with the packet format of the eDP/DP interface, such as the eDP/DP packet shown in Figure 1.

The vertical synchronization signal Vsync includes a plurality of pulses, each of which indicates the start of an output frame period, which is a period for outputting a frame of video data. It should be noted that the eDP/DP interface does not carry a synchronization signal, and the vertical synchronization signal Vsync here is an internal signal generated by the display driver circuit 202 according to the input video data. In one embodiment, the timing controller 220 is configured to generate the vertical synchronization signal Vsync to define the internal timing to control the light/gate control signal and the data voltage to be output at the appropriate time. The output frame period is composed of a vertical back porch (Vertical Back Porch, VBP), a data output period, and a vertical front porch (Vertical Front Porch, VFP), wherein the display driver circuit 202 outputs video data during the data output period to refresh the display panel 204.

There are 100 blank rows without video data in frame F1, followed by a frame of video data. The display driver circuit 202 can detect whether these blank rows carry any instructions. Then, when the display driver circuit 202 detects a blank start signal and its corresponding blank end signal, it can be known that video data is about to arrive and starts to receive video data. At this time, the timing controller 220 can generate a pulse of the vertical synchronization signal Vsync to indicate the start of a frame period. The operation of the light control circuit 214, the data output driver 216 and the gate control circuit 218 must follow the interval timing defined by the vertical synchronization signal Vsync. It should be noted that the display driver circuit 202 needs to spend some processing time to generate the vertical synchronization signal Vsync and configure the vertical back porch. Therefore, part of the video data received before the vertical synchronization signal Vsync can be first stored in the column buffer 230. Next, the display driver circuit 202 can start refreshing the display panel 204 at the time point when the data output period starts.

In this example, it is assumed that each frame contains 2000 rows of video data. During data output, the display driver circuit 202 can output video data from the row buffer 230 and write newly received video data into the row buffer 230 according to the first-in-first-out principle.

After the 2000 rows of video data of frame F1 are completely received, the display driver circuit 202 can start receiving the second frame F2, which includes 90 blank rows and 2000 data rows. At this time, the output frame period enters the vertical front corridor after the video data of frame F1 is output. However, until the display driver circuit 202 receives the blank end signal indicating the arrival of video data, the display driver circuit 202 cannot know the total number of blank rows in the second frame F2. The lighting control should be based on the current video frame. More specifically, the output frame period used to output the frame data of F1 can be determined to be equal to 2100 row times, which is the sum of 100 blank rows and 2000 data rows in frame F1. Assuming a 20% luminance duty cycle, the luminance pulse width during the output frame period for frame F1 is equal to 420 column times, as shown in Figure 3A.

Since there are 90 blank rows in the second frame F2, which is less than the 100 blank rows in the first frame F1, after starting to receive the video data of frame F2, the output frame period for the second frame F2 (as indicated by the pulse of the vertical synchronization signal Vsync) needs to be delayed by 10 row times to cope with the reduced number of blank rows. In this case, there are 10 more rows of data stored in the row buffer 230 than the number of row data temporarily stored in the row buffer 230 in the previous frame (i.e., F1).

Similarly, the output frame period length for frame F2 is determined by the sum of the blank rows and data rows of frame F2, which is equal to 2090 row times. In order to maintain constant brightness, the luminous duty cycle is still 20%, and the luminous pulse width of this output frame period will be equal to 418 row times.

Next, the display driver circuit 202 starts receiving the third frame F3, which includes 110 blank rows, which is more than the 90 blank rows of the second frame F2. Therefore, after starting to receive the video data of frame F3, the output frame period for the third frame F3 (as indicated by the pulse of the vertical synchronization signal Vsync) starts with a smaller delay corresponding to the arrival of the video data of frame F3. In this case, there are fewer rows of data stored in the row buffer 230 (20 rows of data less than the number of rows of data temporarily stored in the row buffer 230 in the previous frame (i.e., F2)).

Similarly, the output frame period length for frame F3 is determined by the sum of the blank rows and data rows of frame F3, which is equal to 2110 row times. In order to maintain constant brightness, the luminous duty cycle is still 20%, and the luminous pulse width of this output frame period will be equal to 422 row times.

Based on the above control method, under variable frame rate, the display driver circuit 202 can handle the refresh of the display panel 204 and well control the constant light-emitting duty cycle. It is necessary to use part of the column buffer 230 to temporarily store the input video data before transmitting it to the display panel 204. However, due to the non-fixed frame rate, the arrival time of the next frame of video data is usually difficult to predict. If the variation of the delay time exceeds an allowable value, so that the video data cannot arrive in time to smoothly generate the output video data, the display driver circuit 202 cannot store the new video data into the column buffer 230, and therefore needs to refresh the display panel 204 through the old video data or other available data, resulting in abnormal display screen. To solve this problem, the conventional approach is to use a larger row buffer or even a frame buffer that can store more row data, but a larger memory space is often accompanied by a larger area and higher cost. From another perspective, the memory space of the row/frame buffer is limited. Unless the allocated memory space reaches a very large capacity, the arrival time with a large variation range is still difficult to be well processed by the row/frame buffer.

The present invention proposes a novel control method that does not require a large amount of memory space. It can well control the light-emitting duty cycle to reduce the side effects on the displayed image when the arrival time of the input video varies greatly. In one embodiment, after the video data of the previous frame is completely received, the detection circuit 212 of the display driver circuit 202 can determine whether the next frame of video data is received within a predetermined time. If the next frame of video data is received at or before the predetermined time point, that is, the delay time of this frame of data can be processed by the existing column buffer 230, which means that the timing scheme in Figures 3A and 3B is feasible. On the contrary, if the next frame of video data cannot be received within the scheduled time, it means that the delay time of the video data is too large, so that the display driver circuit 202 cannot output the newly received video data in time to refresh the display panel 204.

Figures 4A and 4B are timing diagrams showing the operation of the driver circuit 202 according to an embodiment of the present invention. Similar to Figures 3A and 3B, Figures 4A and 4B also show a series of input frames, vertical synchronization signals Vsync, and output timings of video data configured according to the eDP/DP data format. In this example, the number of blank rows in frame F1 is 100, and the storage capacity of the row buffer 230 included in the display driver circuit 202 allows the reception of a maximum of, for example, 130 blank rows. Then, the video data in frame F1 is successfully received and then output during the corresponding output frame period. After the last row of video data of frame F1 is received, the detection circuit 212 can calculate the row time until the next frame of input video data (i.e., F2) is received. More specifically, the detection circuit 212 can calculate the row time to determine whether the input video data is received at a predetermined time point corresponding to 130 blank rows.

In this example, a blank start signal is sent at the beginning of each column time, so the detection circuit 212 can count the number of blank start signals after receiving the last column of video data.

In one embodiment, if the display driver circuit 202 operates normally, according to the first-in-first-out principle, the input video data is written into the column buffer 230 in time, and the output video data is output from the column buffer 230, the display driver circuit 202 can be regarded as operating in a normal scanning mode. In the normal scanning mode, the vertical synchronization signal Vsync can be used to define an output frame period for outputting a frame of video data. If the detection circuit 212 determines that when the calculated column time exceeds a critical value (such as 130) but no input video data is received, the display driver circuit 202 can enter a fast scanning mode. In the fast scan mode, the data output driver 216 can stop outputting video data, that is, stop refreshing the display panel 204. Correspondingly, the gate control circuit 218 can stop outputting the gate control signal to the display panel 204.

In the fast scan mode, in order to maintain constant brightness, the light control circuit 214 can still output a light pulse signal with the same duty cycle as the previous normal scan mode. Although the data output driver 216 stops outputting video data, the data voltage can still be retained in the storage capacitor of the corresponding pixel for a frame period, with only leakage within the allowable range. Therefore, the impact of delayed refresh on the screen display can be minimized.

For example, as shown in FIGS. 4A and 4B, after the video data of frame F1 is completely received, when the detection circuit 212 determines that the calculated number of blank rows exceeds a critical value and no video data is received, the display driver circuit 202 can enter the fast scan mode after the output frame period for frame F1 ends. In the fast scan mode, each pulse of the vertical synchronization signal Vsync generated by the timing controller 220 can define a fast scan period, and the length of the fast scan period is shorter than the length of the output frame period. The length of the fast scan period can be predetermined, and its suitable value can be determined according to the operating speed of the display panel 204. For example, the length of the fast scanning period can be determined to be equal to 1/10, 1/25 or 1/100 of the length of the output frame period. Based on the fast scanning period, the luminescence control clock can have a higher frequency (compared to the normal scanning mode), and the duty cycle of the luminescence pulse signal is the same as its duty cycle in the last output frame period in the normal scanning mode.

If blank rows are continuously received, the display driver circuit 202 is in the fast scan mode until the next frame of video data arrives. In this example, after the display driver circuit 202 receives a blank end signal indicating the arrival of the video data of frame F2, it is ready to enter the normal scan mode and restart the refresh of the display panel 204. More specifically, when the detection circuit 212 detects the arrival of new video data, the display driver circuit 202 completes the last fast scan period, or allocates an additional fast scan period to ensure that the row buffer 230 stores enough video data, and then enters the normal scan mode. In normal scanning mode, the vertical synchronization signal Vsync restarts to follow the frame period corresponding to the input video data. The luminous pulse signal can maintain the same duty cycle, and the luminous control clock is output at a lower frequency (compared to the fast scanning period). The display driver circuit 202 restarts to refresh the display panel 204 using the newly received video data, and outputs the corresponding gate control signal at the same time.

Figures 5A and 5B are waveform diagrams showing the detailed implementation of the driver circuit 202 in the normal scanning mode and the fast scanning mode according to the embodiment of the present invention. Figures 5A and 5B show the waveforms of a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a gate control signal GOA, multiplexing control signals MUX1~MUX3, output video data VOUT, a light control clock EM_CLK, and a light pulse signal EM_STV. The vertical synchronization signal Vsync and the horizontal synchronization signal Hsync are used to define the timing of the normal scanning mode and the fast scanning mode. In the normal scanning mode, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync follow the input frame data and are used to define an output frame period and a column time respectively. In the fast scan mode, the vertical synchronization signal Vsync can define a fast scan period, which is shorter than the output frame period, and the period length of the horizontal synchronization signal Hsync is also proportionally shortened. In this case, each period defined by the pulse of the vertical synchronization signal Vsync has a fixed number of horizontal synchronization signal Hsync pulses. The signal output from the display driver circuit 202 to the display panel 204 will follow the timing defined by the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync.

In the normal scanning mode, the display driver circuit 202 can refresh the display panel 204 normally. Specifically, the output of the gate control signal GOA is enabled, and a frame of output video data VOUT (for red (R), green (G), and blue (B)) is output row by row, and the corresponding multiplexers on the display panel 204 are sequentially turned on through the multiplexing control signals MUX1~MUX3, so that the output video data VOUT is sequentially transmitted to the target data row. The multiplexing control signals MUX1~MUX3 are only used to illustrate an exemplary implementation of the multiplexer control. In fact, there may be 6, 8 or any number of multiplexers on the display panel 204 to couple to hundreds or thousands of data rows on the panel. The luminous control clock EM_CLK is toggled according to the timing defined by the horizontal synchronization signal Hsync. It should be noted that the luminous control clock EM_CLK can be output at any and suitable frequency, and its implementation is not limited to the cases shown in Figures 5A and 5B. The luminous pulse signal EM_STV has a predetermined duty cycle to determine the overall brightness. In this example, the duty cycle is defined as a lighting ratio equal to 4/N, wherein the luminous pulse signal EM_STV has a pulse whose width is equal to 4 column times (among the N column times of this frame).

As shown in FIG. 5B, after the corridor of the output frame period is the fast scanning period, at which time the display driver circuit 202 enters the fast scanning mode. In the fast scanning mode, each pulse of the horizontal synchronization signal Hsync defines a shortened column time. In order to maintain constant brightness, the luminous pulse signal EM_STV also has a pulse, and the width of this pulse is equal to 4 shortened column times to achieve the same lighting ratio 4/N, which is equivalent to the same duty cycle.

FIG. 6 is a flow chart of process 60 of the first embodiment of the present invention. Process 60 can be implemented in a display driver circuit for controlling a light-emitting diode panel, such as the display driver circuit 202 in FIG. 2. As shown in FIG. 6, process 60 includes the following steps: Step 600: The display driver circuit 202 receives a frame of video data and outputs the frame of video data in a normal scanning mode.

Step 602: The detection circuit 212 determines whether the next frame of video data is received in time. If yes, execute step 600; if no, execute step 604.

Step 604: After the last output frame period ends, the display driver circuit 202 enters the fast scanning mode.

Step 606: In the fast scanning mode, the light-emitting control circuit 214 outputs a light-emitting pulse signal with the same duty cycle and outputs a light-emitting control clock with a higher frequency, and the data output driver 216 and the gate control circuit 218 stop outputting.

Step 608: The detection circuit 212 determines whether the next frame of video data has arrived. If yes, execute step 600; if no, execute step 606.

For the detailed operation and variations of process 60, please refer to the description in the previous paragraph and will not be elaborated here.

It is worth noting that the purpose of the present invention is to propose a new method for receiving input video data through the eDP/DP interface to control the LED panel. Those skilled in the art can make modifications or changes accordingly, but are not limited to this. For example, in the above embodiment, the host 200 continuously outputs a blank start signal in the blanking interval, and the blank start signal can be used as a reference for the display driver circuit 202 to calculate the column time. In another embodiment, the blank start signal is not transmitted in the blanking interval, and the display driver circuit 202 should judge the arrival of the next frame of data by itself.

FIG. 7A and FIG. 7B are timing diagrams of the operation of the display driver circuit 202 according to an embodiment of the present invention. In the timing diagrams of FIG. 7A and FIG. 7B, no blank start signal is received in the blank interval between frames F1 and F2, so the display driver circuit 202 cannot determine the row time by counting the number of blank start signals. However, based on the previous frame F1 video data received by the display driver circuit 202 and its associated blank end/blank start signals, the row time length is known information, so that the display driver circuit 202 can calculate the row time through an internal clock (such as the horizontal synchronization signal generated by the timing controller 220). If the calculated row time quantity exceeds a critical value (which exceeds the allowable value range based on the storage capacity of the row buffer 230), the display driver circuit 202 can still enter the fast scanning mode.

In summary, the present invention proposes a method for receiving input video data through an eDP/DP interface to control a light-emitting diode panel, and its related control circuit (such as a display driver circuit). When the input video data is received normally, the display driver circuit can operate in a normal scanning mode, wherein the input video data is sequentially written into the column buffer, and then the output video data is output from the column buffer to the display panel. Under a variable frame rate, the arrival time of each frame of video data has a different delay. If the next frame of data is not received within a predetermined time, the display driver circuit can enter a fast scan mode, in which the light control clock has a higher frequency (compared to the normal scan mode), and the light pulse signal maintains the same duty cycle to keep the brightness constant. In one embodiment, the vertical and horizontal synchronization signals in the fast scan mode can be triggered by a higher frequency (compared to the normal scan mode) to control the output timing of the light control signal. At the same time, the video data and its related gate control signal stop outputting, so the data voltage stored in the pixel can be used to maintain the picture display. Therefore, the display driver circuit only needs a small number of column buffers to well control the light emission and brightness of the LED panel in variable frame rate applications without affecting the picture quality.

The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

60: Process

600~608: Steps

Claims (36)

A method for a control circuit for controlling a display panel, the method comprising: determining whether an input video data is received within a predetermined time; when determining that an input video data is received within the predetermined time, outputting an output video data and a clock signal having a first frequency to the display panel; and when determining that no input video data is received within the predetermined time, stopping outputting the output video data and outputting the clock signal having a second frequency to the display panel; wherein the second frequency is higher than the first frequency. The method as described in claim 1 further comprises: outputting a light pulse signal having a first duty cycle to the display panel during an output frame period for outputting a frame of video data; and when it is determined that no input video data is received within the predetermined time, outputting the light pulse signal having a second duty cycle to the display panel during a time period after the output frame period; wherein the second duty cycle is substantially equal to the first duty cycle. The method as described in claim 1 further includes: when it is determined that an input video data is received within the predetermined time, outputting a gate control signal to the display panel; and when it is determined that no input video data is received within the predetermined time, stopping outputting the gate control signal to the display panel. As described in claim 1, the step of determining whether an input video data is received within the predetermined time includes: calculating a time column after receiving the last input video data to determine whether an input video data is received within the predetermined time. The method as described in claim 4, wherein the step of calculating the row time after receiving the last input video data includes: calculating the number of blank start signals received after receiving the last input video data. The method as described in claim 4, wherein the step of calculating the row time after receiving the last input video data to determine whether an input video data is received within the predetermined time includes: when the calculated row time exceeds a critical value but no input video data is received, it is determined that no input video data is received within the predetermined time, and the critical value is determined according to a row buffer. The method as described in claim 1, wherein when it is determined that an input video data is received within the predetermined time, the control circuit is in a normal scanning mode, and when it is determined that no input video data is received within the predetermined time, the control circuit is in a fast scanning mode, and the method further includes: when the control circuit is in the normal scanning mode, a vertical synchronization signal is generated according to the input video data to define an output frame period; and when the control circuit is in the fast scanning mode, the vertical synchronization signal is generated to define a fast scanning period; Wherein, the length of the fast scanning period is shorter than the length of the output frame period. The method as described in claim 1, wherein the control circuit is in a fast scanning mode, and the method further comprises: after receiving a blank end signal, entering a normal scanning mode and restarting to output the output video data, the blank end signal indicating the arrival of the input video data. The method as described in claim 1 further includes: receiving the input video data through a display port (DP) interface or an embedded display port (eDP) interface. A control circuit for controlling a display panel comprises: a detection circuit for determining whether an input video data is received within a predetermined time; a data output driver coupled to the detection circuit for outputting an output video data to the display panel when the detection circuit determines that the input video data is received within the predetermined time, and outputting an output video data to the display panel when the detection circuit determines that no input video data is received within the predetermined time. Stop outputting the output video data; and a light control circuit coupled to the detection circuit, used to output a clock signal with a first frequency to the display panel when the detection circuit determines that an input video data is received within the predetermined time, and output the clock signal with a second frequency to the display panel when the detection circuit determines that no input video data is received within the predetermined time; wherein the second frequency is higher than the first frequency. The control circuit as described in claim 10, wherein the light control circuit is further used to: output a light pulse signal having a first duty cycle to the display panel during an output frame period for outputting a frame of video data; and when the detection circuit determines that no input video data is received within the predetermined time, output the light pulse signal having a second duty cycle to the display panel within a time interval after the output frame period; wherein the second duty cycle is substantially equal to the first duty cycle. The control circuit as described in claim 10 further includes a gate control circuit, which is used to: output a gate control signal to the display panel when the detection circuit determines that an input video data is received within the predetermined time; and stop outputting the gate control signal to the display panel when the detection circuit determines that no input video data is received within the predetermined time. The control circuit as described in claim 10, wherein the detection circuit is further used to calculate a time after receiving the last input video data to determine whether an input video data is received within the predetermined time. A control circuit as described in claim 13, wherein the detection circuit is further used to calculate the number of blank start signals received after receiving the last input video data to calculate the row time. The control circuit as described in claim 13 further includes a row of buffers, wherein when the calculated row time exceeds a critical value but no input video data is received, the detection circuit further determines that no input video data is received within the predetermined time, and the critical value is determined according to the row of buffers. The control circuit as claimed in claim 10, wherein when the detection circuit determines that an input video data is received within the predetermined time, the control circuit is in a normal scanning mode, and when the detection circuit determines that no input video data is received within the predetermined time, the control circuit is in a fast scanning mode, and the control circuit further comprises: a timing controller, which is used to: when the control circuit is in the normal scanning mode, generate a vertical synchronization signal according to the input video data to define an output frame period; and when the control circuit is in the fast scanning mode, generate the vertical synchronization signal to define a fast scanning period; wherein the length of the fast scanning period is shorter than the length of the output frame period. A control circuit as described in claim 10, wherein the control circuit is in a fast scanning mode, and after the control circuit receives a blank end signal, the control circuit enters a normal scanning mode and the data output driver restarts outputting the output video data, and the blank end signal indicates the arrival of the input video data. The control circuit as described in claim 10 is also used to receive the input video data through a display port (DP) interface or an embedded display port (eDP) interface. A method for a control circuit for controlling a display panel, the method comprising: receiving a first frame of video data; outputting the first frame of video data and a light pulse signal having a first duty cycle to the display panel; after the first frame of video data is completely received, determining whether a second frame of video data is received within a predetermined time; and when determining that the second frame of video data is not received within the predetermined time, outputting the light pulse signal having the first duty cycle to the display panel without outputting any video data. The method as described in claim 19 further includes: outputting a light control clock having a first frequency to the display panel for the first frame of video data; and when it is determined that the second frame of video data is not received within the predetermined time, outputting the light control clock having a second frequency to the display panel; wherein the second frequency is higher than the first frequency. The method as described in claim 19 further includes: when it is determined that the second frame of video data is received within the predetermined time, outputting a gate control signal to the display panel; and when it is determined that the second frame of video data is not received within the predetermined time, stopping outputting the gate control signal to the display panel. The method as described in claim 19, wherein the step of determining whether the second frame of video data is received within the predetermined time includes: calculating a series of time after the first frame of video data is received to determine whether the second frame of video data is received within the predetermined time. The method as described in claim 22, wherein the step of calculating the column time after receiving the first frame of video data includes: calculating the number of blank start signals received after receiving the first frame of video data. The method as described in claim 22, wherein the step of calculating the column time after receiving the first frame of video data to determine whether the second frame of video data is received within the predetermined time includes: when the calculated column time exceeds a critical value but no video data is received, it is determined that the second frame of video data is not received within the predetermined time, and the critical value is determined based on a column buffer. The method as described in claim 19, wherein when it is determined that the second frame of video data is received within the predetermined time, the control circuit is in a normal scanning mode, and when it is determined that the second frame of video data is not received within the predetermined time, the control circuit is in a fast scanning mode, and the method further includes: when the control circuit is in the normal scanning mode, a vertical synchronization signal is generated according to the second frame of video data to define an output frame period; and when the control circuit is in the fast scanning mode, the vertical synchronization signal is generated to define a fast scanning period; wherein the length of the fast scanning period is shorter than the length of the output frame period. The method as described in claim 19, wherein the control circuit is in a fast scanning mode, and the method further comprises: after receiving a blank end signal, entering a normal scanning mode and restarting to output an output video data, the blank end signal indicating the arrival of a third frame of video data. The method as described in claim 19 further includes: receiving the first frame of video data via a display port (DP) interface or an embedded DP (eDP) interface. A control circuit is used to control a display panel, the control circuit comprising: a detection circuit, used to receive a first frame of video data, and after the first frame of video data is completely received, determine whether a second frame of video data is received within a predetermined time; a data output driver, coupled to the detection circuit, used to output the first frame of video data to the display panel; and A light control circuit is coupled to the detection circuit and is used to output a light pulse signal having a first duty cycle to the display panel; wherein, when the detection circuit determines that the second frame of video data is not received within the predetermined time, the light control circuit is used to output the light pulse signal having the first duty cycle, and the data output driver does not output any video data. The control circuit as described in claim 28, wherein the light control circuit is further used to: output a light control clock having a first frequency to the display panel for the first frame of video data; and when the detection circuit determines that the second frame of video data is not received within the predetermined time, output the light control clock having a second frequency to the display panel; wherein, the second frequency is higher than the first frequency. The control circuit as described in claim 28 further includes a gate control circuit, which is used to: output a gate control signal to the display panel when the detection circuit determines that the second frame of video data is received within the predetermined time; and stop outputting the gate control signal to the display panel when the detection circuit determines that the second frame of video data is not received within the predetermined time. The control circuit as described in claim 28, wherein the detection circuit is further used to calculate a time after the first frame of video data is received to determine whether the second frame of video data is received within the predetermined time. The control circuit as described in claim 31, wherein the detection circuit is further used to calculate the number of blank start signals received after receiving the first frame of video data to calculate the row time. The control circuit as described in claim 31 further includes a row buffer, wherein when the calculated row time exceeds a critical value but no video data is received, the detection circuit further determines that the second frame of video data is not received within the predetermined time, and the critical value is determined according to the row buffer. A control circuit as described in claim 28, wherein when the detection circuit determines that the second frame of video data is received within the predetermined time, the control circuit is in a normal scanning mode, and when the detection circuit determines that the second frame of video data is not received within the predetermined time, the control circuit is in a fast scanning mode, and the control circuit further includes: a timing controller, which is used to: when the control circuit is in the normal scanning mode, generate a vertical synchronization signal according to the second frame of video data to define an output frame period; and when the control circuit is in the fast scanning mode, generate the vertical synchronization signal to define a fast scanning period; wherein the length of the fast scanning period is shorter than the length of the output frame period. A control circuit as described in claim 28, wherein the control circuit is in a fast scanning mode, and after the control circuit receives a blank end signal, the control circuit enters a normal scanning mode and the data output driver restarts outputting an output video data, and the blank end signal indicates the arrival of a third frame of video data. The control circuit as described in claim 28 is also used to receive the first frame of video data through a display port (DP) interface or an embedded display port (eDP) interface.

Images