TWI871735B - Method of programming memory - Google Patents

Abstract

A method of programming a memory includes performing a plurality of programming shots is provided. Each programming shot includes a pre-charge stage and a programming stage and includes the following steps. Applying a common source line voltage to a common source line or applying a bit line voltage to a bit line in the pre-charge stage, wherein the common source line voltage or the bit line voltage is applied by using incremental-step-pulse programming (ISPP) in the plurality of pre-charge stages. Applying a programming voltage to a selected word line in the programming stage, wherein the programming voltage is applied by using ISPP in the plurality of programming stages.

Description

How to write to memory

The present invention relates to an operating method of a semiconductor device, and in particular to a memory writing method.

When performing a write operation including multiple write shots on a memory, a specific common source line voltage may be applied to the common source line in the precharge stage of the write shot to increase the channel potential of the unselected memory cells so that they can be at a sufficiently large voltage level to avoid the unselected memory cells from generating the Fowler-Nordheim Tunneling Effect. However, an excessively large common source line voltage is likely to generate a relatively large horizontal electric field on a specific word line (e.g., a selected word line) and induce hot carrier interference, causing the critical voltage of the unselected memory cells to rise and increasing the possibility of generating read interference during a subsequent read operation.

If the common source line voltage applied to the common source line during the pre-charge stage is reduced to improve the above problem, the ability of the unselected memory cells to prevent write interference will be reduced due to the decrease in channel potential, which increases the possibility of the unselected memory cells being subject to write interference.

The present invention provides a memory writing method, which can avoid inducing hot carrier interference and reduce the possibility of memory generating writing interference.

The memory writing method of the present invention includes performing multiple writing shots, wherein each of the multiple writing shots includes a precharge phase and a writing phase, and includes the following steps. First, in the precharge phase, a common source line voltage is applied to the common source line, wherein the common source line voltage is applied in an incremental step pulse writing manner in multiple precharge phases. Next, in the writing phase, a writing voltage is applied to a selected word line, wherein the writing voltage is applied in an incremental step pulse writing manner in multiple writing phases.

The memory writing method of the present invention includes performing multiple write shots, wherein each of the multiple write shots includes a precharge phase and a write phase, and includes the following steps. First, in the precharge phase, a bit line voltage is applied to the bit line, wherein the bit line voltage is applied in an incremental step pulse writing manner in multiple precharge phases. Next, in the write phase, a write voltage is applied to the selected word line, wherein the write voltage is applied in an incremental step pulse writing manner in multiple write phases.

Based on the above, the memory writing method of the present invention applies the common source line voltage applied to the common source line or the bit line voltage applied to the bit line in a plurality of pre-charge stages in an incremental step pulse writing manner, which can avoid generating a relatively large horizontal electric field on a specific word line (e.g., a selected word line) to induce hot carrier interference. Furthermore, the memory writing method of the present invention applies the common source line voltage applied to the common source line or the bit line voltage applied to the bit line in a plurality of pre-charge stages in an incremental step pulse writing manner, thereby reducing the possibility of the memory of the present invention generating write interference.

FIG. 1A is a partial three-dimensional schematic diagram of a memory according to an embodiment of the present invention, and FIG. 1B is a partial three-dimensional schematic diagram of a memory cell string according to an embodiment of the memory in FIG. 1A .

1A and 1B , the memory 10 of the present embodiment includes a substrate SB, a common source line CSL, a word line stack WL, a dummy word line stack DWL, a series selection line SSL, a ground selection line GSL, a plurality of vertical channel structures VC, a plurality of bit lines BL, and a global bit line GBL. The memory 10 may be, for example, a three-dimensional memory, such as a three-dimensional NAND flash memory, but the present invention is not limited thereto.

The substrate SB may be, for example, a semiconductor substrate. In some embodiments, the material of the substrate SB may include silicon, doped silicon, germanium, silicon germanium, semiconductor compounds, other suitable semiconductor materials, or a combination thereof. For example, the substrate SB may be a silicon substrate, but the present invention is not limited thereto. In some embodiments, a plurality of doped regions may be formed in the substrate SB according to design requirements. For example, a plurality of doped regions including a P-type well region (not shown) and an N-type deep well region (not shown) may be formed in the substrate SB, but the present invention is not limited thereto. In other embodiments, a buried oxide layer (not shown) may be further formed on the substrate SB.

The common source line CSL is, for example, disposed on the substrate SB, and may be, for example, a conductive layer or a plurality of conductive lines disposed on the substrate SB, but the present invention is not limited thereto. In the present embodiment, the common source line CSL further extends in the normal direction d3 of the substrate SB to define a memory block 10B of the memory 10. Specifically, the memory 10 of the present embodiment may further include a plurality of memory blocks and a plurality of common source lines not shown in FIG. 1A , and the memory blocks are defined by two common source lines adjacent to each other.

A plurality of vertical channel structures VC are, for example, disposed on the substrate SB and electrically connected to the common source line CSL, wherein each of the plurality of vertical channel structures VC extends, for example, in the normal direction d3 of the substrate SB. In some embodiments, the plurality of vertical channel structures VC are disposed in a memory block 10B defined by two adjacent common source lines. In other words, the plurality of vertical channel structures VC can be disposed between adjacent common source lines.

One of the plurality of vertical channel structures VC includes a memory cell string 10S, as shown in FIG. 1B , but the present invention is not limited thereto. In the present embodiment, each of the plurality of vertical channel structures VC may include an insulating column DC, a channel layer CH, and a charge trapping layer CTL, but the present invention is not limited thereto.

The insulating column DC is, for example, an internal structure of the vertical channel structure VC. In some embodiments, the material of the insulating column DC may include a suitable dielectric material. For example, the material of the insulating column DC may include silicon oxide, but the present invention is not limited thereto.

The channel layer CH is, for example, disposed around the insulating column DC. In some embodiments, the channel layer CH may include a suitable semiconductor material. For example, the material of the channel layer CH may include polysilicon, but the present invention is not limited thereto.

The charge trapping layer CTL is, for example, disposed around the channel layer CH, and may be, for example, an external structure of the vertical channel structure VC. In some embodiments, the charge trapping layer CTL may include a composite structure. In the present embodiment, the charge trapping layer CTL may include three dielectric layers sequentially stacked on the side surface of the channel layer CH. For example, the charge trapping layer CTL may include a composite layer of oxide-nitride-oxide (ONO), but the present invention is not limited thereto. In other embodiments, the charge trapping layer CTL may include a composite layer of oxide-nitride-oxide-nitride-oxide (ONONO) or a composite layer including other structures.

The word line stack WL is, for example, disposed on a substrate SB. In some embodiments, the word line stack WL may include a plurality of word lines stacked in sequence in a normal direction d3 of the substrate SB, wherein the plurality of word lines may each extend on a plane defined by a first direction d1 and a second direction d2, and the first direction d1 and the second direction d2 are orthogonal to the normal direction d3 of the substrate SB. Specifically, the plurality of word lines included in the word line stack WL may each be regarded as a layer of memory cell pages, wherein the memory block 10B includes a plurality of layers of memory cell pages. In this embodiment, the word line stack WL includes 96 word lines _WL0 - _WL95 , wherein each memory cell in a memory cell string 10S is electrically connected to a corresponding word line, but the present invention is not limited thereto. In some embodiments, the material of the word line stack WL may include a suitable conductive material. For example, the material of the word line stack WL may include tungsten, but the present invention is not limited thereto.

The dummy word line stack DWL is, for example, disposed on the substrate SB, and may include, for example, a lower dummy word line stack DBWL and an upper dummy word line stack DTWL. In some embodiments, the lower dummy word line stack DBWL may include a plurality of lower dummy word lines sequentially stacked in the normal direction d3 of the substrate SB, and the upper dummy word line stack DTWL may also include a plurality of upper dummy word lines sequentially stacked in the normal direction d3 of the substrate SB, wherein the plurality of lower dummy word lines and the plurality of upper dummy word lines may also extend on planes defined by the first direction d1 and the second direction d2, respectively. In this embodiment, the lower dummy word line stack DBWL includes three lower dummy word lines _DBWL0 - _DBWL2 , and the upper dummy word line stack DTWL also includes three upper dummy word lines DTWL0 _{- DTWL2} , but the invention is not limited thereto. In some embodiments, the material of the dummy word line stack DWL may be the same or similar to the material of the word line stack WL.

In this embodiment, the plurality of dummy word lines DBWL0 _{- DBWL2} are disposed between the substrate SB and the plurality of word lines _WL0 - _WL95 in the normal direction d3 of the substrate SB. From another perspective, the plurality of word lines _WL0 - _WL95 are disposed between the plurality of dummy word lines DBWL0 _- DBWL2 and the plurality of dummy word lines DTWL0 _{- DTWL2} in the normal direction _d3 of the substrate SB.

The serial selection line SSL is, for example, disposed on the substrate SB. In some embodiments, the serial selection line SSL may be disposed on a plurality of dummy word lines _{DTWL0- DTWL2} in the normal direction d3 of the substrate SB. In some embodiments, the material of the serial selection line SSL may be the same as or similar to the material of the word line stack WL. It is worth noting that, although FIG. 1A shows that the number of serial selection lines SSL included in the memory 10 is 1, the present invention is not limited thereto.

The ground selection line GSL is, for example, disposed on the substrate SB. In some embodiments, the ground selection line GSL may be disposed between the plurality of dummy word lines _DBWL0 - _DBWL2 and the substrate SB in the normal direction d3 of the substrate SB. In some embodiments, the material of the ground selection line GSL may be the same as or similar to the material of the word line stack WL.

A plurality of bit lines BL are, for example, disposed on a substrate SB, wherein the plurality of bit lines BL may, for example, each extend in a second direction d2. In some embodiments, the plurality of bit lines BL are disposed on a vertical channel structure VC in a normal direction d3 of the substrate SB. It is worth noting that, although FIG. 1A shows that the plurality of bit lines BL in the memory 10 include four bit lines BL ₀ -BL ₃ , the present invention is not limited thereto. In addition, in the present embodiment, the corresponding bit lines (e.g., bit lines BL ₀ -BL ₃ ) may be electrically connected to a channel layer CH in the corresponding vertical channel structure VC through a conductive structure such as a plug (not shown). Based on this, each memory cell string 10S in the memory block 10B may be electrically connected between a common source line CSL and a corresponding bit line (e.g., bit lines BL ₀ -BL ₃ ). In some embodiments, the material of the plurality of bit lines BL may be the same as or similar to the material of the word line stack WL.

The global bit line GBL is, for example, disposed on the substrate SB. In some embodiments, the global bit line GBL may be electrically connected to a plurality of bit lines BL. In this embodiment, the global bit line GBL may be electrically connected to bit lines BL ₀ -BL _3. In some embodiments, the material of the global bit line GBL may be the same as or similar to the material of the word line stack WL.

2A and 2B illustrate voltage waveforms of a memory during a write operation according to an embodiment of the present invention, and FIG. 3 illustrates a flow chart of a memory write method according to an embodiment of the present invention, wherein the memory described in FIG. 3 takes the above-mentioned memory 10 as an example, but it should be noted that the present invention is not limited thereto.

Please refer to FIG. 2A and FIG. 3 at the same time. First, the memory 10 of the present embodiment performs a writing operation with multiple programming shots, wherein a writing operation of 15 programming shots is taken as an example, but the present invention is not limited thereto. In addition, although not shown in FIG. 3 , writing verification can be performed between two writing shots.

It is worth noting that, although the present embodiment takes the writing operation from the top of the memory 10 to the bottom of the memory 10 (in the order from the word line WL ₉₅ to the word line WL ₀ ) as an example, the present invention is not limited thereto. That is, in other embodiments, the writing operation may be performed from the bottom of the memory 10 to the top of the memory 10 (in the order from the word line WL ₀ to the word line WL ₉₅ ).

In step S10, during the pre-charge phase Tpre, a common source line voltage VCSL_pre is applied to the common source line CSL, wherein the common source line voltage VCSL_pre is applied in the pre-charge phase Tpre of multiple write shots in an incremental step pulse programming (ISPP) manner. For example, as shown in FIG2A, during the pre-charge phase Tpre1 of the first write shot S1, a common source line voltage VCSL_pre1 is applied to the common source line CSL, during the pre-charge phase Tpre2 of the second write shot S2, a common source line voltage VCSL_pre2 is applied to the common source line CSL, and during the pre-charge phase Tpre3 of the third write shot S3, a common source line voltage VCSL_pre2 is applied to the common source line CSL. , a common source line voltage VCSL_pre3 is applied to the common source line CSL, wherein the common source line voltage VCSL_pre1 is less than or equal to the common source line voltage VCSL_pre2, and the common source line voltage VCSL_pre2 is less than or equal to the common source line voltage VCSL_pre3 (VCSL_pre1≦VCSL_pre2≦VCSL_pre3).

In this embodiment, the common source line voltage VCSL_pre applied in each pre-charge phase Tpre in 15 write shots may be as shown in the following Table 1 and will be described in detail below, but the present invention is not limited thereto.

[Table 1] Common source line voltage applied during pre-charge phase Write Shooting Embodiment 1 Embodiment 2 Embodiment 3 Embodiment 4 Embodiment 5 first 1V 1V 1V 1V 1V Second time 1.1V 1V 1V 1V 1V The third time 1.2V 1V 1V 1V 1V Fourth 1.3V 1V 1V 1.2V 1V Fifth 1.4V 1V 1V 1.2V 1V Sixth 1.5V 1V 1V 1.2V 1V Seventh 1.6V 1V 1V 1.4V 1V Eighth 1.7V 1V 1V 1.4V 1V Ninth 1.8V 1V 1V 1.4V 1V The tenth time 1.9V 1V 1V 1.6V 1V Eleventh 2.0V 1.1V 1.3V 1.6V 2.4V Twelfth 2.1V 1.2V 1.6V 1.6V 2.4V Thirteenth 2.2V 1.3V 1.9V 1.8V 2.4V Fourteenth 2.3V 1.4V 2.2V 1.8V 2.4V The fifteenth 2.4V 1.5V 2.5V 1.8V 2.4V

In Embodiment 1, the common source line voltage applied in the precharge phase increases between a write shot and a subsequent write shot, and the common source line voltage increases by the same value between each write shot and a subsequent write shot. Specifically, the common source line voltage applied in the precharge phase of the first write shot (S1) is 1V, and the common source line voltage applied in the precharge phase of the second write shot (S2) is 1.1V. The common source line voltage applied during the pre-charge phase of the third write shot (S3) is 1.2V, the common source line voltage applied during the pre-charge phase of the fourth write shot (S4) is 1.3V, the common source line voltage applied during the pre-charge phase of the fifth write shot (S5) is 1.4V, the common source line voltage applied during the pre-charge phase of the sixth write shot (S6) is 1.5V, the common source line voltage applied during the pre-charge phase of the seventh write shot (S7) is 1.6V, the common source line voltage applied during the pre-charge phase of the eighth write shot (S8) is 1.7V, and the common source line voltage applied during the pre-charge phase of the ninth write shot (S9) is 1.8V. The source line voltage is 1.8V, the common source line voltage applied in the pre-charge stage of the tenth write shot (S10) is 1.9V, the common source line voltage applied in the pre-charge stage of the eleventh write shot (S11) is 2.0V, the common source line voltage applied in the pre-charge stage of the twelfth write shot (S12) is 2.1V, the common source line voltage applied in the pre-charge stage of the thirteenth write shot (S13) is 2.2V, the common source line voltage applied in the pre-charge stage of the fourteenth write shot (S14) is 2.3V, and the common source line voltage applied in the pre-charge stage of the fifteenth write shot (S15) is 2.4V. In addition, the value of each increase in the common source line voltage between one write shot and the subsequent write shot is 0.1V.

In Embodiment 2, the multiple write shots include a first period and a second period, the common source line voltage applied in the precharge phase does not change between a write shot in the first period and a subsequent write shot, and the common source line voltage applied in the precharge phase increases between a write shot in the second period and a subsequent write shot. Specifically, the first period of the multiple write shots is from the first write shot to the tenth write shot (S1-S10), wherein the common source line voltage applied in the precharge phase maintains a precharge voltage of 1.0V. The second period of the multiple write shots is from the tenth write shot to the fifteenth write shot (S10-S15), wherein the common source line voltage applied in the precharge stage increases between one write shot and a subsequent write shot, and the value of each increase in the common source line voltage between one write shot and a subsequent write shot is 0.1V.

In Embodiment 3, the multiple write shots include a first period and a second period, the common source line voltage applied in the precharge phase does not change between a write shot in the first period and a subsequent write shot, and the common source line voltage applied in the precharge phase increases between a write shot in the second period and a subsequent write shot. Specifically, the first period of the multiple write shots is from the first write shot to the tenth write shot (S1-S10), wherein the common source line voltage applied in the precharge phase maintains a precharge voltage of 1.0V. The second period of the multiple write shots is from the tenth write shot to the fifteenth write shot (S10-S15), wherein the common source line voltage applied in the precharge stage increases between one write shot and a subsequent write shot, and the value of each increase in the common source line voltage between one write shot and a subsequent write shot is 0.3V.

In Embodiment 4, the multiple write shots include multiple first periods and multiple second periods, and one of the multiple second periods is arranged between two of the adjacent multiple first periods. Specifically, the multiple write shots include five first periods, which are respectively the first write shot to the third write shot (S1-S3), the fourth write shot to the sixth write shot (S4-S6), the seventh write shot to the ninth write shot (S7-S9), the tenth write shot to the twelfth write shot (S10-S12), and the thirteenth write shot to the fifteenth write shot (S13-S15), wherein the common source line voltage applied in the pre-charge stage maintains the pre-charge voltage of 1.0V, 1.2V, 1.4V, 1.6V, and 1.8V, respectively. In addition, the multiple write shots include 4 second periods, which are the third write shot to the fourth write shot (S3-S4), the sixth write shot to the seventh write shot (S6-S7), the ninth write shot to the tenth write shot (S9-S10), and the twelfth write shot to the thirteenth write shot (S12-S13), wherein the common source line voltage applied in the pre-charge stage increases between one write shot and the subsequent write shot, and the value of each increase in the common source line voltage between one write shot and the subsequent write shot is 0.2V.

In Embodiment 5, the multiple write shots include two first periods and one second period arranged in sequence, and one second period is arranged between the two first periods. Specifically, the write shots in the two first periods are respectively the first write shot to the tenth write shot (S1-S10) and the eleventh write shot to the fifteenth write shot (S11-S15), wherein the common source line voltage applied in the pre-charge stage maintains the pre-charge voltage of 1.0V and 2.4V respectively. In addition, the write shot of the second period is from the tenth write shot to the eleventh write shot (S10-S11), wherein the common source line voltage applied in the precharge stage increases between the tenth write shot and the eleventh write shot, and the value of the common source line voltage increased between the tenth write shot and the eleventh write shot is 1.4V.

In this embodiment, by applying the common source line voltage VCSL_pre by using an incremental step pulse write in each precharge phase Tpre of multiple write shots, the common source line voltage VCSL_pre having a relatively high voltage level can be applied to the common source line CSL of the last phase of the multiple write shots (e.g., the last five write shots S11 to S15). Based on this, it can be ensured that the channel potential of the unselected memory cell is at a sufficiently large voltage level to avoid the unselected memory cell from generating the FN tunneling effect, thereby reducing the possibility of the memory 10 generating write interference.

In addition, referring to FIG. 2A , a ground voltage VSS is applied to the selected word line (in this embodiment, the word line WL ₂₄ ) of each memory cell string in the precharge phase Tpre. In some embodiments, the ground voltage VSS has the same voltage level in each precharge phase Tpre of multiple write shots (e.g., precharge phase Tpre1, precharge phase Tpre2, and precharge phase Tpre3 in FIG. 2A ). In this embodiment, the ground voltage VSS is 0V.

Please refer to FIG. 2A and FIG. 3 simultaneously. In step S20, during the write phase Tpgm, a write voltage Vpgm is applied to the selected word line, wherein the write voltage Vpgm is applied in an incremental step pulse write manner during the write phase Tpgm of multiple write shots. For example, as shown in Figure 2A, during the write phase Tpgm1 of the first write shot S1, a write voltage Vpgm1 is applied to the selected word line (which is the word line WL ₂₄ in this embodiment), during the write phase Tpgm2 of the second write shot S2, a write voltage Vpgm2 is applied to the selected word line, and during the write phase Tpgm3 of the third write shot S3, a write voltage Vpgm3 is applied to the selected word line, wherein the write voltage Vpgm1 is less than or equal to the write voltage Vpgm2, and the write voltage Vpgm2 is less than or equal to the write voltage Vpgm3 (Vpgm1≦Vpgm2≦Vpgm3).

The present embodiment is not limited to the manner of applying the write voltage Vpgm in an incremental step pulse in the write phase Tpgm of multiple write shots. For example, the write voltage Vpgm applied in the write phase may increase between one write shot and the subsequent write shot, and the write voltage Vpgm may increase by the same value between each write shot and the subsequent write shot.

In the present embodiment, by applying the write voltage Vpgm using incremental step pulse writing in each write phase Tpgm of multiple write shots, the write voltage Vpgm can have a relatively low voltage level during the initial period of the multiple write shots (for example, the initial five write shots S1 to S5), so that during the initial period of the multiple write shots in step S10 (for example, the initial five write shots S1 to S5), a common source line voltage VCSL_pre with a relatively low voltage level can be applied to the common source line CSL, which can avoid generating a relatively large horizontal electric field on a specific word line (for example, word line WL ₂₄ ) to induce hot carrier interference.

2A , the common source line voltage VCSL_pre applied to the common source line CSL in the write phase Tpgm may be increased to the power voltage VDD. For example, the common source line voltage VCSL_pre1 applied to the common source line CSL may be increased to the power voltage VDD in the write phase Tpgm1 of the first write shot S1. In some embodiments, the power voltage VDD has the same voltage level in each write phase Tpgm of multiple write shots.

The following describes the voltage waveforms of the dummy word line DBWL, the ground selection line GSL, the string selection line SSL, and the bit line BL when performing the write operation of the embodiment of the present invention.

2B , in each pre-charge stage (including pre-charge stage Tpre1, pre-charge stage Tpre2, and pre-charge stage Tpre3), the pre-charge voltage VPASS_pre is applied to the down-dummy word line DBWL. Specifically, in each pre-charge stage, the voltage level of the down-dummy word line DBWL may increase from the ground voltage VSS to the pre-charge voltage VPASS_pre, and then decrease from the pre-charge voltage VPASS_pre to the ground voltage VSS. Thereafter, in each write phase (including the write phase Tpgm1, the write phase Tpgm2, and the write phase Tpgm3), the voltage level of the dummy word line DBWL may increase from the ground voltage VSS to the pass voltage VDBWL, and then decrease from the pass voltage VDBWL to the ground voltage VSS.

Referring to FIG. 2B , in each pre-charge phase (including pre-charge phase Tpre1, pre-charge phase Tpre2, and pre-charge phase Tpre3), the pre-charge voltage VPASS_pre is applied to the ground selection line GSL. Specifically, in each pre-charge phase, the voltage level of the ground selection line GSL may increase from the ground voltage VSS to the pre-charge voltage VPASS_pre, and then decrease from the pre-charge voltage VPASS_pre to the ground voltage VSS. Thereafter, in each write phase (including write phase Tpgm1, write phase Tpgm2, and write phase Tpgm3), the voltage level of the ground selection line GSL is maintained at the ground voltage VSS.

2B , in each pre-charge phase (including pre-charge phase Tpre1, pre-charge phase Tpre2, and pre-charge phase Tpre3), the ground voltage VSS is applied to the serial selection line SSL. Thereafter, in each write phase (including write phase Tpgm1, write phase Tpgm2, and write phase Tpgm3), the serial selection line voltage VSSL is applied to the serial selection line SSL. In detail, the voltage level of the serial selection line SSL may increase from the ground voltage VSS to the serial selection line voltage VSSL, and then decrease from the serial selection line voltage VSSL to the ground voltage VSS. In this embodiment, the series selection line voltage VSSL is 3.6V, but the present invention is not limited thereto.

Referring to FIG. 2B , in each precharge phase (including precharge phase Tpre1, precharge phase Tpre2, and precharge phase Tpre3), the ground voltage VSS is applied to the write bit line (BL ₀ in this embodiment). Thereafter, in each write phase (including write phase Tpgm1, write phase Tpgm2, and write phase Tpgm3), the bit line voltage VBL_pgm used to write to the selected memory cell is applied to the write bit line. In this embodiment, the bit line voltage VBL_pgm used to write to the selected memory cell is 0 V, but the present invention is not limited thereto.

2B , in each precharge phase (including precharge phase Tpre1, precharge phase Tpre2, and precharge phase Tpre3), a bit line voltage VBL_inhibit for inhibiting unselected memory cells from being written is applied to the inhibit bit line (BL ₁ in this embodiment). Specifically, in each precharge phase, the voltage level of the inhibit bit line may increase from the ground voltage VSS to the bit line voltage VBL_inhibit for inhibiting unselected memory cells from being written, and the bit line voltage VBL_inhibit is maintained. Thereafter, in each write phase (including write phase Tpgm1, write phase Tpgm2, and write phase Tpgm3), the voltage level of the inhibiting bit line is reduced from the bit line voltage VBL_inhibit to the ground voltage VSS. In the present embodiment, the bit line voltage VBL_inhibit for inhibiting the unselected memory cells from being written is the power supply voltage VDD, but the present invention is not limited thereto.

2B , in each precharge phase (including precharge phase Tpre1, precharge phase Tpre2, and precharge phase Tpre3), the ground voltage VSS is applied to the quick pass write (QPW) bit line (BL ₂ in this embodiment). Thereafter, in each write phase (including write phase Tpgm1, write phase Tpgm2, and write phase Tpgm3), the bit line voltage VBL_QPW for quick pass write to the memory cell is applied to the quick pass write bit line. Specifically, the voltage level of the write bit line can be increased from the ground voltage VSS to the bit line voltage VBL_QPW, and then decreased from the bit line voltage VBL_QPW to the ground voltage VSS.

FIG. 4A is a schematic diagram showing voltages applied to a ground selection line GSL, a plurality of dummy word lines DBWL ₀ -DBWL ₂ , a common source line CSL, and a string selection line SSL during a precharge phase of a write shot according to an embodiment of the present invention.

4A , for the ground selection line GSL and the plurality of lower dummy word lines DBWL ₀ -DBWL ₂ , a precharge voltage VPASS_pre is applied to the ground selection line GSL and the plurality of lower dummy word lines DBWL ₀ -DBWL ₂ in the precharge phase, so that a ground selection gate (not shown) coupled to the ground selection line GSL and a dummy gate (not shown) coupled to the lower dummy word lines DBWL ₀ -DBWL ₂ can be turned on. For the common source line CSL, a common source line voltage VCSL_pre is applied to the common source line CSL in the precharge phase by using an incremental step pulse write. Since the ground selection gate is turned on, the voltage level of the channel layer CH can be increased by applying the common source line voltage VCSL_pre. For the serial selection line SSL, the ground voltage VSS is applied to the serial selection line SSL in the pre-charge stage, so that the serial selection gate (not shown) coupled to the serial selection line SSL can be turned off and is in a closed state.

4B, 4C and 4D are schematic diagrams showing voltages applied to the ground select line GSL, the serial select line SSL, the common source line CSL, the selected word line, the unselected word line and the bit lines _BL0 - _BL2 during the write phase of a write shot according to an embodiment of the present invention, wherein the bit line BL0 in FIG. 4B is a write bit line, the bit line _BL1 in FIG _. 4C is an inhibit bit line, and the bit line _BL2 in FIG. 4D is a fast-pass write bit line.

4B , for the ground selection line GSL, the ground voltage VSS is applied to the ground selection line GSL in the write phase, so that the ground selection gate coupled to the ground selection line GSL can be closed and in a closed state. For the serial selection line SSL, the serial selection line voltage VSSL is applied to the serial selection line SSL in the write phase, so that the serial selection gate coupled to the serial selection line SSL can be opened. For the common source line CSL, the power supply voltage VDD is applied to the common source line CSL in the write phase. For the selected word line (the word line _WL24 in the present embodiment) and the unselected word lines (including the dummy word lines _DBWL0 - _DBWL2 ), the write voltage Vpgm is applied to the selected word line by using an incremental step pulse write in the write phase, and the voltage VDBWL is applied to the unselected word lines in the write phase. For the write bit line (the bit line _BL0 in the present embodiment), the bit line voltage VBL_pgm is applied to the write bit line in the write phase to perform a write operation. Specifically, when a write voltage Vpgm is applied to a selected word line, electrons are tunneled from the channel layer CH to the charge trapping layer CTL (shown in FIG. 1B ) due to a relatively high voltage difference between the write voltage Vpgm and the bit line voltage VBL_pgm and are trapped therein.

4C , for the ground selection line GSL, the ground voltage VSS is applied to the ground selection line GSL in the write phase. For the string selection line SSL, the string selection line voltage VSSL is applied to the string selection line SSL in the write phase. For the common source line CSL, the power supply voltage VDD is applied to the common source line CSL in the write phase. For the selected word line (the word line _WL24 in the present embodiment) and the unselected word lines (including the dummy word lines _DBWL0 - _DBWL2 ), the write voltage Vpgm is applied to the selected word line by using an incremental step pulse write in the write phase, and the voltage VDBWL is applied to the unselected word lines in the write phase. For the inhibited bit line (the bit line _BL1 in the present embodiment), the voltage level of the inhibited bit line in the write phase is maintained at the bit line voltage VBL_inhibit, wherein the bit line voltage VBL_inhibit can be the power supply voltage VDD to increase the voltage level of the channel layer CH, thereby performing a write inhibit operation.

4D , for the ground selection line GSL, the ground voltage VSS is applied to the ground selection line GSL in the write phase. For the string selection line SSL, the string selection line voltage VSSL is applied to the string selection line SSL in the write phase. For the common source line CSL, the power supply voltage VDD is applied to the common source line CSL in the write phase. For the selected word line (word line _WL24 in the present embodiment) and the unselected word lines (including the dummy word lines _DBWL0 - _DBWL2 ), the write voltage Vpgm is applied to the selected word line by writing with an incremental step pulse in the write phase, and the pass voltage VDBWL is applied to the unselected word lines in the write phase. For the fast pass write bit line (bit line _BL2 in the present embodiment), the bit line voltage VBL_QPW is applied to the fast pass write bit line in the write phase to perform a fast pass write operation.

It is worth noting that, although the memory 10 of the present embodiment is a three-dimensional memory, the memory writing method of the present invention can be applied to a two-dimensional memory (e.g., a two-dimensional NAND flash memory). In addition, the memory writing method of the present invention can be applied to memory cells including single-level cells (SLC), double-level cells (MLC), triple-level cells (TLC), or quad-level cells (QLC).

5A and 5B illustrate voltage waveforms of a memory in another embodiment of the present invention when performing a write operation, and FIG. 6 illustrates a flow chart of a memory write method in another embodiment of the present invention, wherein the memory described in FIG. 6 takes the above-mentioned memory 10 as an example, but it should be noted that the present invention is not limited thereto.

Please refer to FIG. 5A and FIG. 6 at the same time. First, the memory 10 of the present embodiment performs a writing operation with multiple programming shots, wherein a writing operation of 15 programming shots is taken as an example, but the present invention is not limited thereto. In addition, although not shown in FIG. 6 , writing verification can be performed between two writing shots.

It is worth noting that although the present embodiment performs a write operation from the bottom of the memory 10 to the top of the memory 10 (in order from word line WL ₀ to word line WL ₉₅ ), the present invention is not limited thereto.

In step S10', during the precharge phase Tpre, a bit line voltage VBL_pre is applied to the bit line BL, wherein the bit line voltage VBL_pre is applied in the precharge phase Tpre of multiple write shots in an incremental step pulse programming (ISPP) manner. In this embodiment, the bit line BL includes a write bit line (BL ₀ ), an inhibit bit line (BL ₁ ), and a fast pass write bit line (BL ₂ ). For example, as shown in Figure 5A, during the pre-charge phase Tpre1 of the first write shot S1, the bit line voltage VBL_pre1 is applied to the bit line BL, during the pre-charge phase Tpre2 of the second write shot S2, the bit line voltage VBL_pre2 is applied to the bit line BL, and during the pre-charge phase Tpre3 of the third write shot S3, the bit line voltage VBL_pre3 is applied to the bit line BL, wherein the bit line voltage VBL_pre1 is less than or equal to the bit line voltage VBL_pre2, and the bit line voltage VBL_pre2 is less than or equal to the bit line voltage VBL_pre3 (VBL_pre1≦VBL_pre2≦VBL_pre3).

5A , after the bit line voltage VBL_pre is applied, the voltage level of the write bit line (BL ₀ ) in each precharge phase Tpre may be reduced from the bit line voltage VBL_pre to the ground voltage VSS, the voltage level of the inhibited bit line (BL ₁ ) in each precharge phase Tpre may be maintained at the bit line voltage VBL_pre, and the voltage level of the fast-pass write bit line (BL ₂ ) in each precharge phase Tpre may be reduced from the bit line voltage VBL_pre to the ground voltage VSS.

In this embodiment, the bit line voltage VBL_pre applied in each pre-charge phase Tpre in 15 write shots may be as shown in Table 2 below and will be described in detail below, but the present invention is not limited thereto.

[Table 2] Bit line voltage profile applied during the pre-charge phase Write Shooting Embodiment 6 Embodiment 7 Embodiment 8 Embodiment 9 Embodiment 10 first 1V 1V 1V 1V 1V Second time 1.1V 1V 1V 1V 1V The third time 1.2V 1V 1V 1V 1V Fourth 1.3V 1V 1V 1.2V 1V Fifth 1.4V 1V 1V 1.2V 1V Sixth 1.5V 1V 1V 1.2V 1V Seventh 1.6V 1V 1V 1.4V 1V Eighth 1.7V 1V 1V 1.4V 1V Ninth 1.8V 1V 1V 1.4V 1V The tenth time 1.9V 1V 1V 1.6V 1V Eleventh 2.0V 1.1V 1.3V 1.6V 2.4V Twelfth 2.1V 1.2V 1.6V 1.6V 2.4V Thirteenth 2.2V 1.3V 1.9V 1.8V 2.4V Fourteenth 2.3V 1.4V 2.2V 1.8V 2.4V The fifteenth 2.4V 1.5V 2.5V 1.8V 2.4V

In Embodiment 6, the bit line voltage applied in the precharge phase increases between a write shot and a subsequent write shot, and the bit line voltage increases by the same value between each write shot and a subsequent write shot. Specifically, the bit line voltage applied in the precharge phase of the first write shot (S1) is 1V, the bit line voltage applied in the precharge phase of the second write shot (S2) is 1.1V, The bit line voltage applied during the pre-charge phase of the third write shot (S3) is 1.2V, the bit line voltage applied during the pre-charge phase of the fourth write shot (S4) is 1.3V, the bit line voltage applied during the pre-charge phase of the fifth write shot (S5) is 1.4V, the bit line voltage applied during the pre-charge phase of the sixth write shot (S6) is 1.5V, the bit line voltage applied during the pre-charge phase of the seventh write shot (S7) is 1.6V, the bit line voltage applied during the pre-charge phase of the eighth write shot (S8) is 1.7V, and the bit line voltage applied during the pre-charge phase of the ninth write shot (S9) is 1.8V. The bit line voltage applied during the pre-charge phase of the tenth write shot (S10) is 1.9V, the bit line voltage applied during the pre-charge phase of the eleventh write shot (S11) is 2.0V, the bit line voltage applied during the pre-charge phase of the twelfth write shot (S12) is 2.1V, the bit line voltage applied during the pre-charge phase of the thirteenth write shot (S13) is 2.2V, the bit line voltage applied during the pre-charge phase of the fourteenth write shot (S14) is 2.3V, and the bit line voltage applied during the pre-charge phase of the fifteenth write shot (S15) is 2.4V. In addition, the value of each increase in the bit line voltage between one write shot and the subsequent write shot is 0.1V.

In Embodiment 7, the multiple write shots include a first period and a second period, the bit line voltage applied in the precharge phase does not change between a write shot in the first period and a subsequent write shot, and the bit line voltage applied in the precharge phase increases between a write shot in the second period and a subsequent write shot. Specifically, the first period of the multiple write shots is from the first write shot to the tenth write shot (S1-S10), wherein the bit line voltage applied in the precharge phase maintains a precharge voltage of 1.0V. The second period of the multiple write shots is from the tenth write shot to the fifteenth write shot (S10-S15), wherein the bit line voltage applied in the pre-charge phase increases between one write shot and a subsequent write shot, and the value of each increase in the bit line voltage between one write shot and a subsequent write shot is 0.1V.

In Embodiment 8, the multiple write shots include a first period and a second period, the bit line voltage applied in the precharge phase does not change between a write shot in the first period and a subsequent write shot, and the bit line voltage applied in the precharge phase increases between a write shot in the second period and a subsequent write shot. Specifically, the first period of the multiple write shots is from the first write shot to the tenth write shot (S1-S10), wherein the bit line voltage applied in the precharge phase maintains a precharge voltage of 1.0V. The second period of the multiple write shots is from the tenth write shot to the fifteenth write shot (S10-S15), wherein the bit line voltage applied in the precharge phase increases between one write shot and a subsequent write shot, and the value of each increase in the bit line voltage between one write shot and a subsequent write shot is 0.3V.

In Embodiment 9, the multiple write shots include multiple first periods and multiple second periods, and one of the multiple second periods is arranged between two of the adjacent multiple first periods. Specifically, the multiple write shots include five first periods, which are respectively the first write shot to the third write shot (S1-S3), the fourth write shot to the sixth write shot (S4-S6), the seventh write shot to the ninth write shot (S7-S9), the tenth write shot to the twelfth write shot (S10-S12), and the thirteenth write shot to the fifteenth write shot (S13-S15), wherein the bit line voltages applied in the pre-charge stage maintain the pre-charge voltages of 1.0V, 1.2V, 1.4V, 1.6V, and 1.8V, respectively. In addition, the multiple write shots include four second periods, which are respectively from the third write shot to the fourth write shot (S3-S4), from the sixth write shot to the seventh write shot (S6-S7), from the ninth write shot to the tenth write shot (S9-S10), and from the twelfth write shot to the thirteenth write shot (S12-S13), wherein the bit line voltage applied in the pre-charge stage increases between one write shot and a subsequent write shot, and the value of each increase in the bit line voltage between one write shot and a subsequent write shot is 0.2V.

In Embodiment 10, the multiple write shots include two first periods and one second period arranged in sequence, and one second period is arranged between the two first periods. Specifically, the write shots in the two first periods are respectively the first write shot to the tenth write shot (S1-S10) and the eleventh write shot to the fifteenth write shot (S11-S15), wherein the bit line voltages applied in the pre-charge stage are respectively maintained at the pre-charge voltages of 1.0V and 2.4V. In addition, the write shot of the second period is from the tenth write shot to the eleventh write shot (S10-S11), wherein the bit line voltage applied in the precharge stage increases between the tenth write shot and the eleventh write shot, and the value of the bit line voltage increased between the tenth write shot and the eleventh write shot is 1.4V.

In this embodiment, by using an incremental step pulse to write and apply the bit line voltage VBL_pre in each pre-charge phase Tpre of multiple write shots, the bit line voltage VBL_pre with a relatively high voltage level can be applied to the bit line BL in the last phase of the multiple write shots (e.g., the last five write shots S11 to S15). Based on this, it can be ensured that the channel potential of the unselected memory cell is at a sufficiently large voltage level to avoid the unselected memory cell from generating the FN tunneling effect, thereby reducing the possibility of the memory 10 generating write interference.

In addition, referring to FIG. 5A , a ground voltage VSS is applied to the selected word line (in this embodiment, the word line WL ₂₄ ) of each memory cell string in the precharge phase Tpre. In some embodiments, the ground voltage VSS has the same voltage level in each precharge phase Tpre of multiple write shots. In this embodiment, the ground voltage VSS is 0V.

Please refer to FIG. 5A and FIG. 6 simultaneously. In step S20, during the write phase Tpgm, a write voltage Vpgm is applied to the selected word line, wherein the write voltage Vpgm is applied in an incremental step pulse write manner during the write phase Tpgm of multiple write shots, which has been described in detail in the above-mentioned embodiment and will not be repeated here.

In the present embodiment, by applying the write voltage Vpgm using incremental step pulse writing in each write phase Tpgm of multiple write shots, the write voltage Vpgm can have a relatively low voltage level during the initial period of the multiple write shots (for example, the first five write shots S1 to S5), so that a bit line voltage VBL_pre with a relatively low voltage level can be applied to the bit line BL during the initial period of the multiple write shots in step S10', which can avoid generating a relatively large horizontal electric field on a specific word line (for example, word line WL ₂₄ ) to induce hot carrier interference.

In addition, referring to FIG. 5A , the bit line voltage VBL_pgm for writing to the selected memory cell is applied to the write bit line (BL ₀ ) in each write phase Tpgm. In the present embodiment, the bit line voltage VBL_pgm is 0 V, but the present disclosure is not limited thereto. The voltage level of the inhibit bit line (BL ₁ ) is first increased from the bit line voltage VBL_pre to the power voltage VDD in each write phase Tpgm, and then decreased from the power voltage VDD to the ground voltage VSS. The voltage level of the fast-pass write bit line (BL ₂ ) is first increased from the ground voltage VSS to the bit line voltage VBL_QPW for fast-pass writing to the memory cell in each write phase Tpgm, and then decreased from the bit line voltage VBL_QPW to the ground voltage VSS.

The following describes the voltage waveforms of the dummy word line DTWL, the ground selection line GSL, the serial selection line SSL and the common source line CSL when performing the write operation of the embodiment of the present invention.

5B , in each pre-charge phase (including pre-charge phase Tpre1, pre-charge phase Tpre2, and pre-charge phase Tpre3), the pre-charge voltage VPASS_pre is applied to the dummy word line DTWL. Specifically, in each pre-charge phase, the voltage level of the dummy word line DTWL may increase from the ground voltage VSS to the pre-charge voltage VPASS_pre, and then decrease from the pre-charge voltage VPASS_pre to the ground voltage VSS. Thereafter, in each write phase (including the write phase Tpgm1, the write phase Tpgm2, and the write phase Tpgm3), the voltage level of the dummy word line DTWL may increase from the ground voltage VSS to the pass voltage VDTWL, and then decrease from the pass voltage VDTWL to the ground voltage VSS.

5B , in each pre-charge phase (including pre-charge phase Tpre1, pre-charge phase Tpre2, and pre-charge phase Tpre3), the ground voltage VSS is applied to the ground selection line GSL. Thereafter, in each write phase (including write phase Tpgm1, write phase Tpgm2, and write phase Tpgm3), the voltage level of the ground selection line GSL is maintained at the ground voltage VSS.

5B , in each pre-charge phase (including pre-charge phase Tpre1, pre-charge phase Tpre2, and pre-charge phase Tpre3), the pre-charge voltage VPASS_pre is applied to the serial selection line SSL. Specifically, in each pre-charge phase, the voltage level of the serial selection line SSL may increase from the ground voltage VSS to the pre-charge voltage VPASS_pre, and then decrease from the pre-charge voltage VPASS_pre to the ground voltage VSS. Thereafter, in each write phase (including write phase Tpgm1, write phase Tpgm2, and write phase Tpgm3), the serial selection line voltage VSSL is applied to the serial selection line SSL. Specifically, the voltage level of the string selection line SSL may be increased from the ground voltage VSS to the string selection line voltage VSSL, and then decreased from the string selection line voltage VSSL to the ground voltage VSS. In the present embodiment, the string selection line voltage VSSL is 3.6V, but the present invention is not limited thereto.

Referring to FIG. 5B , in each pre-charging stage (including pre-charging stage Tpre1, pre-charging stage Tpre2, and pre-charging stage Tpre3), a common source line voltage VCSL is applied to a common source line CSL. Specifically, in each pre-charging stage, the voltage level of the common source line CSL may increase from the ground voltage VSS to the common source line voltage VCSL. In this embodiment, the common source line voltage VCSL is the power voltage VDD, but the present invention is not limited thereto. Thereafter, in each write phase (including the write phase Tpgm1, the write phase Tpgm2, and the write phase Tpgm3), the voltage level of the common source line CSL is maintained at the common source line voltage VCSL and then is reduced from the common source line voltage VCSL to the ground voltage VSS.

FIG. 7A is a schematic diagram showing voltages applied to a string select line SSL, a plurality of dummy word lines DTWL ₀ -DTWL ₂ , a bit line BL, a ground select line GSL, and a common source line CSL during a precharge phase of a write shot according to another embodiment of the present invention.

7A , for the serial selection line SSL and the plurality of dummy word lines DTWL ₀ -DTWL ₂ , the precharge voltage VPASS_pre is applied to the serial selection line SSL and the plurality of dummy word lines DTWL ₀ -DTWL ₂ in the precharge phase, so that the serial selection gate (not shown) coupled to the serial selection line SSL and the dummy gate (not shown) coupled to the dummy word lines DTWL ₀ -DTWL ₂ can be turned on. For the bit line BL, the bit line voltage VBL_pre is applied to the bit line BL in the precharge phase by using an incremental step pulse write. Since the above-mentioned series selection gate is turned on, the voltage level of the channel layer CH can be increased due to the application of the bit line voltage VBL_pre. For the ground selection line GSL, the ground voltage VSS is applied to the ground selection line GSL in the pre-charge stage, so that the ground selection gate (not shown) coupled to the ground selection line GSL can be closed and in a closed state. For the common source line CSL, the power voltage VDD can be applied to the common source line CSL in the pre-charge stage.

7B , 7C and 7D are schematic diagrams showing voltages applied to the ground select line GSL, the serial select line SSL, the common source line CSL, the selected word line, the unselected word line and the bit lines _BL0 - _BL2 during the write phase of a write shot according to another embodiment of the present invention, wherein the bit line BL0 in FIG. 7B is a write bit line, the bit line _BL1 in FIG _. 7C is an inhibit bit line, and the bit line _BL2 in FIG. 7D is a fast-pass write bit line.

7B , for the ground selection line GSL, the ground voltage VSS is applied to the ground selection line GSL during the write phase. For the string selection line SSL, the string selection line voltage VSSL is applied to the string selection line SSL during the write phase. For the common source line CSL, the voltage level of the common source line CSL is maintained at the power supply voltage VDD during the write phase. For the selected word line (in this embodiment, the word line _WL24 ) and the unselected word lines (including the dummy word lines DTWL0 _{- DTWL2} ), the write voltage Vpgm is applied to the selected word line by using an incremental step pulse write in the write phase, and the voltage VDTWL is applied to the unselected word lines in the write phase. For the write bit line ( _BL0 ), the bit line voltage VBL_pgm is applied to the write bit line ( _BL0 ) in the write phase to perform a write operation. Specifically, when a write voltage Vpgm is applied to a selected word line, electrons are tunneled from the channel layer CH to the charge trapping layer CTL (shown in FIG. 1B ) due to a relatively high voltage difference between the write voltage Vpgm and the bit line voltage VBL_pgm and are trapped therein.

7C , for the ground selection line GSL, the ground voltage VSS is applied to the ground selection line GSL during the write phase. For the serial selection line SSL, the serial selection line voltage VSSL is applied to the serial selection line SSL during the write phase. For the common source line CSL, the voltage level of the common source line CSL is maintained at the power supply voltage VDD during the write phase. For the selected word line (the word line _WL24 in the present embodiment) and the unselected word lines (including the dummy word lines DTWL0 _{- DTWL2} ), the write voltage Vpgm is applied to the selected word line by using an incremental step pulse write in the write phase, and the voltage VDTWL is applied to the unselected word lines in the write phase. For the inhibited bit line ( _BL1 ), the voltage level of the inhibited bit line ( _BL1 ) in the write phase is maintained at the bit line voltage VBL_inhibit, wherein the bit line voltage VBL_inhibit may be the power supply voltage VDD to increase the voltage level of the channel layer CH, thereby performing a write inhibit operation.

7D , for the ground selection line GSL, the ground voltage VSS is applied to the ground selection line GSL during the write phase. For the serial selection line SSL, the serial selection line voltage VSSL is applied to the serial selection line SSL during the write phase. For the common source line CSL, the voltage level of the common source line CSL is maintained at the power supply voltage VDD during the write phase. For the selected word line (word line _WL24 in the present embodiment) and the unselected word lines (including the dummy word lines DTWL0 _{- DTWL2} ), the write voltage Vpgm is applied to the selected word line by writing with an incremental step pulse in the write phase, and the pass voltage VDTWL is applied to the unselected word lines in the write phase. For the fast pass write bit line ( _BL2 ), the bit line voltage VBL_QPW is applied to the fast pass write bit line ( _BL2 ) in the write phase to perform a fast pass write operation.

It is worth noting that, although the memory 10 of the present embodiment is a three-dimensional memory, the memory writing method of the present invention can be applied to a two-dimensional memory (e.g., a two-dimensional NAND flash memory). In addition, the memory writing method of the present invention can be applied to memory cells including single-level cells (SLC), double-level cells (MLC), triple-level cells (TLC), or quad-level cells (QLC).

FIG8 is a block diagram of a memory system according to an embodiment of the present invention.

8 , the memory system 1000 of this embodiment includes a memory device 100 and a controller 200 .

The memory device 100 may include at least the memory 10 of the aforementioned embodiment, but the present invention is not limited thereto. That is, the memory device 100 may include a two-dimensional memory or a three-dimensional memory. It is to be noted that FIG. 8 is only a simplified block diagram, and a person skilled in the art may appropriately design electronic components such as an address decoder, a voltage generator, a page buffer, a control logic, and other functions in the memory device 100 based on the concept of the present invention.

The controller 200 is, for example, coupled to the memory device 100. The controller 200 may receive commands from, for example, a host device (not shown) to control the memory device 100. For example, the controller 200 may be used to issue a write command to the memory device 100 to write to the memory 10 in the memory device 100, but the present invention is not limited thereto. In other embodiments, the controller 200 may also be used to issue a read command or an erase command to the memory device 100.

In summary, the memory writing method of the present invention is performed by making the common source line voltage applied to the common source line be written in an incremental step pulse manner in multiple pre-charge stages. A common source line voltage with a relatively low voltage level can be applied during the initial period of multiple write shots (e.g., the first five write shots S1 to S5), which can avoid generating a relatively large horizontal electric field on a specific word line (e.g., a selected word line) to induce hot carrier interference.

Furthermore, by applying a common source line voltage to the common source line through the above-mentioned incremental step pulse writing method, a common source line voltage with a relatively high voltage level can be applied during the last period of multiple write shots (for example, the last five write shots S11 to S15), thereby ensuring that the channel potential of the unselected memory cells is at a sufficiently large voltage level to avoid the unselected memory cells from generating FN tunneling effects, thereby reducing the possibility of the memory of the present invention generating write interference.

10: Memory

10B: memory block

10S: memory cell string

100:Memory device

200: Controller

1000:Memory system

BL, BL ₀ , BL ₁ , BL ₂ , BL ₃ : bit line

CH: Channel layer

CSL: Common Source Line

CTL: Charge Trapping Layer

d1: first direction

d2: second direction

d3: normal direction of the base

DWL: Dummy Word Line Stack

DBWL: Dummy Character Line Stack

DBWL ₀ -DBWL ₂ : Dummy character line

DC: Insulation Column

DTWL: Dummy Word Line Stack

DTWL ₀ -DTWL ₂ : Dummy word line

GBL: Global Bit Line

GSL: Ground Select Line

S1, S2, S3: Write Shooting

S10, S10', S20: Steps

SB: Base

SSL: Serial Select Line

Tpgm, Tpgm1, Tpgm2, Tpgm3: write phase

Tpre, Tpre1, Tpre2, Tpre3: Pre-charge stage

VBL_inhibit, VBL_pgm, VBL_pre, VBL_pre1, VBL_pre2, VBL_pre3, VBL_QPW: bit line voltage

VC: Multiple vertical channel structures

VCSL, VCSL_pre, VCSL_pre1, VCSL_pre2, VCSL_pre3: Common source line voltage

VDBWL, VDTWL: pass voltage

VDD: power supply voltage

VPASS_pre: pre-charge voltage

Vpgm: write voltage

VSS: Ground voltage

VSSL: Serial selection line voltage

WL: character line stack

WL ₀ -WL ₉₅ : character line

FIG. 1A is a partial three-dimensional schematic diagram of a memory of an embodiment of the present invention. FIG. 1B is a partial three-dimensional schematic diagram of a memory cell string of an embodiment of the memory of FIG. 1A. FIG. 2A and FIG. 2B are voltage waveform diagrams of a memory of an embodiment of the present invention during a write operation. FIG. 3 is a flow chart of a write method of a memory of an embodiment of the present invention. FIG. 4A is a schematic diagram of applying voltage to a ground selection line, multiple dummy word lines, a common source line, and a series selection line during a precharge phase of a write shot of an embodiment of the present invention. FIG. 4B, FIG. 4C and FIG. 4D are schematic diagrams showing voltage applied to a ground selection line, a series selection line, a common source line, a selected word line, an unselected word line and a bit line during a write phase of a write shot in one embodiment of the present invention, wherein the bit line in FIG. 4B is a write bit line, the bit line in FIG. 4C is a suppress bit line, and the bit line in FIG. 4D is a quick pass write (QPW) bit line. FIG. 5A and FIG. 5B are voltage waveform diagrams of a memory in another embodiment of the present invention during a write operation. FIG. 6 is a flow chart of a memory write method in another embodiment of the present invention. FIG. 7A is a schematic diagram showing another embodiment of the present invention, in which voltage is applied to a series selection line, multiple dummy word lines, a bit line, a ground selection line, and a common source line during a precharge phase of a write shot. FIG. 7B, FIG. 7C, and FIG. 7D are schematic diagrams showing another embodiment of the present invention, in which voltage is applied to a ground selection line, a series selection line, a common source line, a selected word line, an unselected word line, and a bit line during a write phase of a write shot, wherein the bit line in FIG. 7B is a write bit line, the bit line in FIG. 7C is an inhibit bit line, and the bit line in FIG. 7D is a quick pass write (QPW) bit line. FIG. 8 is a block diagram showing a memory system of an embodiment of the present invention.

S10, S20: Steps

Claims (18)

A method for writing a memory includes performing multiple write shots, wherein each of the multiple write shots includes a precharge phase and a write phase and includes the following steps: in the precharge phase, applying a common source line voltage to a common source line, and applying the same precharge voltage to a ground selection line and multiple dummy word lines, wherein the common source line voltage is applied in a plurality of the precharge phases in an incremental step pulse writing manner; and in the write phase, applying a write voltage to a selected word line, wherein the write voltage is applied in a plurality of the write phases in an incremental step pulse writing manner. A memory writing method as described in claim 1, wherein the common source line voltage applied in the precharge phase increases between a write shot and a subsequent write shot, and the common source line voltage increases by the same value between each write shot and the subsequent write shot. A memory writing method as described in claim 1, wherein the multiple write shots include a first period and a second period, the common source line voltage applied in the precharge phase remains unchanged between a write shot in the first period and a subsequent write shot, and the common source line voltage applied in the precharge phase increases between a write shot in the second period and a subsequent write shot. A memory writing method as described in claim 3, wherein the multiple write shots include a first period and a second period arranged in sequence, and the common source line voltage increases by the same value between each write shot and the subsequent write shot in the second period. A memory writing method as described in claim 3, wherein the multiple writing shots include multiple first periods and multiple second periods, and one of the multiple second periods is arranged between two adjacent first periods. A memory writing method as described in claim 3, wherein the multiple writing shots include two first periods and one second period arranged in sequence, and the one second period is arranged between the two first periods. The memory writing method as described in claim 1 further includes applying a ground voltage to the serial selection line during the pre-charge phase so that the serial selection gate coupled to the serial selection line is in a closed state. The memory writing method as described in claim 1 further includes performing a fast pass write operation in the multiple write shots. A memory writing method as described in claim 1, wherein the memory includes a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC) memory cell. A method for writing a memory includes performing multiple write shots, wherein each of the multiple write shots includes a precharge phase and a write phase and includes the following steps: in the precharge phase, applying a bit line voltage to a bit line, and applying the same precharge voltage to a series selection line and a plurality of pull-up word lines, wherein the bit line voltage is applied in a plurality of the precharge phases in an incremental step pulse writing manner; and in the write phase, applying a write voltage to a selected word line, wherein the write voltage is applied in a plurality of the write phases in an incremental step pulse writing manner. A method for writing to a memory as described in claim 10, wherein the bit line voltage applied in the precharge phase increases between a write shot and a subsequent write shot, and the bit line voltage increases by the same value between each write shot and the subsequent write shot. A memory writing method as described in claim 10, wherein the multiple write shots include a first period and a second period, the bit line voltage applied in the precharge phase remains unchanged between a write shot in the first period and a subsequent write shot, and the bit line voltage applied in the precharge phase increases between a write shot in the second period and a subsequent write shot. A memory writing method as described in claim 12, wherein the multiple write shots include a first period and a second period arranged in sequence, and the bit line voltage increases by the same value between each write shot and the subsequent write shot in the second period. A memory writing method as described in claim 12, wherein the multiple writing shots include multiple first periods and multiple second periods, and one of the multiple second periods is arranged between two adjacent first periods. A memory writing method as described in claim 12, wherein the multiple writing shots include two first periods and one second period arranged in sequence, and the one second period is arranged between the two first periods. The memory writing method as described in claim 10 further includes applying a ground voltage to the ground selection line during the pre-charge phase so that the ground selection gate coupled to the ground selection line is in a closed state. The memory writing method as described in claim 10 further includes performing a fast pass write operation in the multiple write shots. A memory writing method as described in claim 10, wherein the memory includes a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC) or a quad-level cell (QLC) memory cell.

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