TWI871782B - Memory device and operating method for memory device - Google Patents

Abstract

A memory device and an operating method for the memory device are provided. The memory device includes a memory array and a control circuit. The memory array includes memory blocks. Each of the memory blocks is, for example a three-dimensional NAND flash memory block. The memory device provides a storage media with high-performance and high-capacity. The control circuit provides a first erasing voltage to perform a first erasing operation on target memory cell strings of a selected memory block in the memory blocks, performs a programming operation on the target memory cell strings after the first erasing operation, and provides a second erasing voltage to perform a second erasing operation on at least one part of memory cells of each of the target memory cell strings after the programming operation. The second erasing voltage is smaller than the first erasing voltage.

Description

Memory device and operation method for memory device

The present disclosure relates to a memory device and an operating method for the memory device, and in particular to a memory device and an operating method for reducing the difference between charge losses of memory cells in the memory device.

Generally speaking, charge retention (or data retention) plays an important role in product identification of memory devices. Different charge losses of multiple memory cells of a memory device may affect the error-correcting operation or read operation of programming. When the charge losses of the multiple memory cells are different, the read windows of the multiple memory cells of the memory device will be different. In particular, for the application of multi-level memory cells (e.g., Triple-level cells, TLC), errors in data read operations or programming error correction operations may occur. Therefore, how to reduce the difference between the charge losses of storage cells is one of the research focuses of technicians in this field.

The present disclosure provides a memory device and an operating method for reducing the difference between charge losses of memory cells in the memory device.

The memory device includes a memory array and a control circuit. The memory array includes a plurality of memory blocks. The control circuit is coupled to the memory array. The control circuit provides a first erase voltage to perform a first erase operation on a plurality of target memory cell strings of a selected memory block among the plurality of memory blocks, performs a programming operation on the plurality of target memory cell strings after the first erase operation, and provides a second erase voltage after the programming operation to perform a second erase operation on at least a portion of the memory cells of each of the plurality of target memory cell strings. The second erase voltage is less than the first erase voltage.

The operation method is used for a memory device. The memory device includes a memory array. The memory array includes a plurality of memory blocks. The operation method includes: providing a first erase voltage to perform a first erase operation on a plurality of target memory cell strings of a selected memory block among the plurality of memory blocks; performing a programming operation on the plurality of target memory cell strings after the first erase operation; and providing a second erase voltage after the programming operation to perform a second erase operation on at least a portion of the memory cells of each of the plurality of target memory cell strings, wherein the second erase voltage is less than the first erase voltage.

Based on the above, the memory device performs a second erase operation on at least a portion of the memory cells of each of the plurality of target memory cell strings after the programming operation. The second erase operation adjusts the charge loss of the memory cells after the programming operation. The difference between the charge losses of the plurality of memory cells is reduced. In this way, the difference between the charge losses of the plurality of memory cells can be reduced.

In order to make the above content clearer and easier to understand, several embodiments are described in detail below with reference to the attached figures.

100: Memory device

110:Memory array

120: Control circuit

BL1~BLn: bit line

CD1, CD2, CD2’, CD3, CD4, CD5: Charge distribution

CSL: Common Source Line

DWL1~DWL3: Virtual character line

M0~M95: memory unit

MBK: memory block

MBK_T: Select memory block

MCG1: First memory unit group

MCG2: Second memory unit group

MD1~MD3: virtual unit

NB: Critical charge number

P1, P2: intersection

RDG: Determination voltage

S100: Operation method

S110~S130: Steps

SS1, SS2: Select signal

ST1~STp: memory cell string

STT1~STT4: target memory unit string

TC1~TCp: Source selection transistor

TS1~TSp: string selection transistor

V1: First erase voltage

V2: Second erase voltage

VCSL: Source Line Signal

VT1, VT2, VT3: critical voltage

VWL: word line signal

WL0~WL95, WLm: character line

WLG1: First character line group

WLG2: Second character line group

X: First direction

Y: Second direction

Z: Third direction

FIG1 is a schematic diagram of a memory device according to an embodiment of the present disclosure.

FIG2 is a schematic diagram of a memory block according to an embodiment of the present disclosure.

FIG3 is a schematic diagram of the waveforms of the first erase voltage and the second erase voltage according to an embodiment of the present disclosure.

FIG4 is a schematic diagram showing the waveforms of the word line signals and the second erase voltage corresponding to the remaining memory cells according to an embodiment of the present disclosure.

FIG5 is a schematic diagram of a memory block according to an embodiment of the present disclosure.

FIG6 is a schematic diagram of charge distribution according to an embodiment of the present disclosure.

FIG. 7 is a schematic diagram showing charge distribution and critical voltage corresponding to different second erase voltages according to an embodiment of the present disclosure.

FIG8 is a schematic diagram of a target memory cell string drawn according to an embodiment of the present disclosure.

FIG9 is a schematic diagram of a target memory cell string drawn according to an embodiment of the present disclosure.

FIG10 is a schematic diagram of a target memory cell string according to an embodiment of the present disclosure.

Figure 11 is a flow chart of an operation method according to an embodiment of the present disclosure.

The present disclosure may be understood by referring to the following detailed description in conjunction with the drawings as described below. It should be noted that for the purpose of clarity and ease of understanding by the reader, the various drawings of the present disclosure depict a portion of an electronic device, and certain elements in the various drawings may not be drawn to scale. In addition, the number and size of each device depicted in the drawings are merely illustrative and are not intended to limit the scope of the present disclosure.

Please refer to FIG. 1, which is a schematic diagram of a memory device according to an embodiment of the present disclosure. In the present embodiment, the memory device 100 includes a memory array 110 and a control circuit 120. The memory array 110 includes a plurality of memory blocks MBK. For example, each memory block MBK can be a NAND flash memory block, but the present disclosure is not limited thereto.

In this embodiment, the control circuit 120 is coupled to the memory array 110. The control circuit 120 provides a first erase voltage V1 to perform a first erase operation on the target memory cell strings STT1~STT4 of the selected memory block MBK_T among the multiple memory blocks MBK. For example, the control circuit 120 responds to a command to select the selected memory block MBK_T among the memory blocks MBK, and then performs a first erase operation on the target memory cell strings STT1~STT4 of the selected memory block MBK_T. The control circuit 120 performs a programming operation on the target memory cell strings STT1~STT4 after the first erase operation.

In this embodiment, the control circuit 120 provides a second erase voltage V2 after the programming operation to perform a second erase operation on at least a portion of the memory cells of each of the plurality of target memory cell strings STT1-STT4. The second erase voltage V2 is lower than the first erase voltage V1. In this embodiment, the "at least a portion of the memory cells" includes at least one memory cell.

It should be noted that after executing the programming operation, the memory device 100 performs a second erase operation on at least a portion of the memory cells of each of the multiple target memory cell strings STT1~STT4 in the selected memory block MBK_T. The second erase operation can adjust the charge loss of the memory cells after the programming operation. The difference between the charge losses of the multiple memory cells can be reduced. In this way, the difference between the charge losses of the multiple memory cells can be reduced. In addition, for the application of Triple-level cells (TLC), because the difference between the read windows can be reduced, errors in data read operations or programming error correction operations will also be reduced. In this way, the memory device 100 provides a high-performance, large-capacity memory medium.

In this embodiment, the at least a portion of the memory cells to which the second erase operation is performed may be determined by a verification operation or an error-correcting operation. Generally speaking, the verification operation or the error-correcting operation is performed during or after the programming operation. In this embodiment, the at least a portion of the memory cells to which the second erase operation is performed may be determined by selecting different regions and/or different layers in the memory block MBK_T.

For example, based on different regions, different layers and/or yields, a first portion of memory cells in the selected memory block MBK_T has a first charge loss. A second portion of memory cells in the selected memory block MBK_T has a second charge loss. The first charge loss is different from the second charge loss. The control circuit 120 performs a second erase operation on the second portion of memory cells. Therefore, the second charge loss is adjusted to the first charge loss.

Please refer to Figures 1, 2 and 3 at the same time. Figure 2 is a schematic diagram of a memory block drawn according to an embodiment of the present disclosure. Figure 3 is a schematic diagram of the waveforms of the first erase voltage and the second erase voltage drawn according to an embodiment of the present disclosure. In this embodiment, the memory block MBK includes string selection transistors TS1~TS4, source selection transistors TC1~TC4 and memory cell strings ST1~ST4. The memory block MBK can be a 2-dimensional NAND flash memory block, but the present disclosure is not limited to this. The first end of the string selection transistor TS1 is connected to the bit line BL1. The second end of the string selection transistor TS1 is connected to one end of the memory cell string ST1. The control end of the string selection transistor TS1 receives the selection signal SS1. The memory cell string ST1 includes memory cells M0~Mm connected in series. The control end of the memory cell M0 is connected to the word line WL0. The control end of the memory cell M1 is connected to the word line WL1, and so on. The first end of the source selection transistor TC1 is connected to the other end of the memory cell string ST1. The first end of the source selection transistor TC1 is connected to the common source line CSL. The control end of the source selection transistor TC1 receives the selection signal SS2.

In other words, the string select transistor TS1, the source select transistor TC1, and the memory cell string ST1 are connected in series between the bit line BL1 and the common source line CSL.

Similarly, string selection transistor TS2, source selection transistor TC2, and memory cell string ST2 are connected in series between bit line BL2 and common source line CSL. String selection transistor TS3, source selection transistor TC3, and memory cell string ST3 are connected in series between bit line BL3 and common source line CSL. String selection transistor TS4, source selection transistor TC4, and memory cell string ST4 are connected in series between bit line BL4 and common source line CSL. String selection transistors TS1-TS4 receive selection signal SS1. Source selection transistors TC1-TC4 receive selection signal SS2. In addition, memory cell strings ST1-ST4 are connected to word lines WL0-WLm. Therefore, the multiple memory cells corresponding to the same word line WL0 in the memory cell string ST1~ST4 can be a memory page. The multiple memory cells corresponding to the same word line WL1 in the memory cell string ST1~ST4 can be another memory page.

In this embodiment, each memory cell string ST1~ST4 can be a NAND flash memory cell string, but the present disclosure is not limited to this.

In the present embodiment, string selection transistors TS1-TS4 and source selection transistors TC1-TC4 are turned on. The memory block MBK in FIG2 is selected. Therefore, the memory block MBK is the selected memory block MBK_T. The memory cell strings ST1-ST4 in FIG2 are target memory cell strings STT1-STT4, respectively. When the first erase operation is performed, the control circuit 120 applies the first erase voltage V1 to the common source line CSL. Therefore, when the first erase operation is performed, the voltage of the common source line signal VCSL provided to the common source line CSL is substantially equal to the first erase voltage V1. In this embodiment, when the first erase operation is performed, the control circuit 120 applies a word line signal VWL having a voltage of approximately 0 to the word lines WL0 to WLm. When the first erase operation is performed, the data of all memory cells of each memory cell string ST1 to ST4 are erased based on the first erase voltage V1.

When performing the second erase operation, the control circuit 120 applies the second erase voltage V2 to the common source line CSL. When performing the second erase operation, the voltage of the common source line signal VCSL is substantially equal to the second erase voltage V2. The control circuit 120 applies substantially zero voltage to the corresponding word lines of at least a portion of the memory cells.

In some embodiments, when performing a first erase operation, the control circuit 120 applies a first erase voltage V1 to the bit lines BL1 to BL4. When performing a second erase operation, the control circuit 120 applies a second erase voltage V2 to the bit lines BL1 to BL4.

In some embodiments, when performing a first erase operation, the control circuit 120 applies a first erase voltage V1 to the bit lines BL1-BL4 and the common source line CSL. When performing a second erase operation, the control circuit 120 applies a second erase voltage V2 to the bit lines BL1-BL4 and the common source line CSL.

In this embodiment, the second erase voltage V2 is lower than the first erase voltage V1. Therefore, the first erase operation is called a "normal erase operation". The second erase operation is called a "weak erase operation". For example, the difference between the second erase voltage V2 and the first erase voltage V1 is in the range of 7 to 13 volts. For example, the second erase voltage V2 is approximately 8 volts, but the disclosure is not limited thereto. The first erase voltage V1 is approximately 20 volts, but the disclosure is not limited thereto.

In addition, please refer to FIG. 1, FIG. 3 and FIG. 4 simultaneously. FIG. 4 is a schematic diagram of the waveform of the word line signal corresponding to the remaining memory cells and the second erase voltage according to an embodiment of the present disclosure. In the second erase operation, the remaining memory cells are excluded from the aforementioned at least a portion of the memory cells of the target memory cell string. In this embodiment, the control circuit 120 does not perform the second erase operation on the remaining memory cells of each target memory cell string ST1~ST4. When performing the second erase operation, the control circuit 120 floats the remaining memory cells. For example, when performing the second erase operation, the word line corresponding to the remaining memory cells is floated. Therefore, the voltage of the word line signal VWL follows the second erase voltage V2 based on the capacitive coupling effect in the remaining memory cells.

Please refer to Figures 1, 3 and 5 at the same time. Figure 5 is a schematic diagram of a memory block according to an embodiment of the present disclosure. The memory block MBK can be a 3D NAND flash memory block. In this embodiment, the memory block MBK at least includes a common source line CSL, bit lines BL1~BLn, word lines WL0~WLm, string selection transistors TS1~TSp, source selection transistors TC1~TCp and memory cell strings ST1~STp. Each memory cell string ST1~STp is respectively coupled to the corresponding bit line of the bit lines BL1~BLn and the common source line CSL. The memory cells of each memory cell string ST1~STp are connected in series along a third direction Z. The memory cells of each memory cell string ST1~STp are respectively coupled to the corresponding word lines of word lines WL0~WLm.

In this embodiment, the string selection transistor TS1, the memory cell string ST1, and the source selection transistor TC1 are connected in series between the bit line BL1 and the common source line CSL. The string selection transistor TS2, the memory cell string ST2, and the source selection transistor TC2 are connected in series between the bit line BL2 and the common source line CSL. Similarly, the string selection transistor TSp, the memory cell string STp, and the source selection transistor TCp are connected in series between the bit line BLp and the common source line CSL.

In this embodiment, the bit lines BL1-BLn extend along the first direction X. The bit lines BL1-BLn are arranged along the second direction Y. The word lines WL0-WLm extend along the plane defined by the first direction X and the second direction Y. The word lines WL0-WLm are arranged along the third direction Z. The first direction X, the second direction Y and the third direction Z are not parallel to each other.

In this embodiment, the memory cells corresponding to the same word line WL0 in different memory cell strings may be a memory page. The memory cells corresponding to the same word line WLm in different memory cell strings may be another memory page.

In the present embodiment, string selection transistors TS1~TSp and source selection transistors TC1~TCp are turned on. The memory block MBK in FIG5 is selected. Therefore, the memory block MBK is the selected memory block MBK_T. The memory cell strings ST1~STp are target memory cell strings, respectively. When performing the first erase operation, the control circuit 120 applies the first erase voltage V1 to the common source line CSL. When performing the first erase operation, the voltage of the common source line signal VCSL is substantially equal to the first erase voltage V1. The control circuit 120 applies substantially 0 voltage to the word lines WL0~WLm. Therefore, when the first erase operation is performed, all data of the memory cells of the memory cell string ST1~STp are erased based on the first erase voltage V1.

When performing the second erase operation, the control circuit 120 applies the second erase voltage V2 to the common source line CSL. When performing the second erase operation, the voltage of the common source line signal VCSL is substantially equal to the second erase voltage V2. The control circuit 120 applies substantially 0 voltage to the corresponding word line connected to at least a portion of the memory cells.

In some embodiments, when performing a first erase operation, the control circuit 120 applies a first erase voltage V1 to the corresponding bit line. When performing a second erase operation, the control circuit 120 applies a second erase voltage V2 to the corresponding bit line.

In some embodiments, when performing a first erase operation, the control circuit 120 applies a first erase voltage V1 to the corresponding bit line and the common source line CSL. When performing a second erase operation, the control circuit 120 applies a second erase voltage V2 to the corresponding bit line and the common source line CSL.

In the second erase operation, the remaining memory cells are excluded from the aforementioned at least a portion of the memory cells of the target memory cell string. Therefore, the control circuit 120 does not perform the second erase operation on the remaining memory cells of each target memory cell string ST1~STp. When the second erase operation is performed, the remaining memory cells are floated. For example, when the second erase operation is performed, the word lines corresponding to the remaining memory cells are floated.

Please refer to FIG. 1 and FIG. 6 at the same time. FIG. 6 is a schematic diagram of charge distribution according to an embodiment of the present disclosure. In this embodiment, FIG. 6 shows the charge distribution CD1 of the first memory cell with the first charge loss and the charge distribution CD2 of the second memory cell with the second charge loss.

In this embodiment, the first charge loss and the second charge loss are shown in FIG6 . The first charge loss is represented as a larger amount of charge loss after the programming operation. The second charge loss is represented as a smaller amount of charge loss after the programming operation. It should be noted that after the programming operation, the intersection P2 of the judgment voltage RDG and the charge distribution CD2 is higher than the intersection P1 of the judgment voltage RDG and the charge distribution CD1. In other words, the amount of charge exceeding the judgment voltage RDG in the charge distribution CD2 is higher than the amount of charge exceeding the judgment voltage RDG in the charge distribution CD1. This means that the charge distribution CD2 has a smaller amount of charge loss. The second memory cell has a poor ECC result. In order to improve the ECC result of the second memory unit, the intersection point P2 must be lowered.

In this embodiment, the control circuit 120 performs a second erase operation on the second memory cell. After performing the second erase operation, the second charge loss of the second memory cell is adjusted to the first charge loss. Therefore, the charge distribution CD2 of the second memory cell is adjusted to be similar to the charge distribution CD2' of the charge distribution CD1. The amount of charge exceeding the determination voltage RDG in the charge distribution CD2' is similar to the amount of charge exceeding the determination voltage RDG in the charge distribution CD1. Therefore, the ECC result of the second memory cell is improved.

For details, please refer to FIG. 1 and FIG. 7 simultaneously. FIG. 7 is a schematic diagram of charge distribution and critical voltage corresponding to different second erase voltages according to an embodiment of the present disclosure. FIG. 7 shows charge distributions CD3 to CD5 of memory cells corresponding to a single data state. Charge distribution CD3 is represented as a charge distribution before the second erase operation is performed. Charge distribution CD3 is a charge distribution after the programming operation. Charge distributions CD4 and CD5 are each represented as different charge distributions after the second erase operation. After performing the second erase operation, based on the fixed critical charge number NB, the critical voltage of the memory cell is adjusted from the critical voltage VT1 corresponding to the charge distribution CD3 to the critical voltage VT2 corresponding to the charge distribution CD4. The critical voltage VT2 is lower than the critical voltage VT1.

In addition, if the second erase voltage V2 is increased, the critical voltage of the memory cell is adjusted from the critical voltage VT1 corresponding to the charge distribution CD3 to the critical voltage VT3 corresponding to the charge distribution CD5. The critical voltage VT3 is lower than the critical voltage VT2.

Therefore, based on the actual situation, the second erase voltage V2 can be adjusted.

Please refer to FIG. 1 and FIG. 8 at the same time. FIG. 8 is a schematic diagram of a target memory cell string according to an embodiment of the present disclosure. In this embodiment, the target memory cell string STT1 is in the selected memory block MBK_T. The selected memory block MBK_T may be a 3D NAND flash memory block as shown in FIG. 5. The target memory cell string STT1 includes dummy cells MD1~MD3 and memory cells M0~M95. The selected memory block MBK_T includes word lines WL0~WL95 and dummy word lines DWL1~DWL3.

In this embodiment, the dummy word lines DWL1 and DWL2 extend along a plane defined by a first direction (i.e., the first direction X in FIG. 5 ) and a second direction Y. Word lines WL0 to WL95 are disposed between dummy word line DWL1 and dummy word line DWL2. Dummy word line DWL3 is disposed between dummy word line DWL1 and dummy word line DWL2. Dummy word line DWL3 extends along the second direction Y.

In the present embodiment, the memory cells M0~M95 are divided into a first memory cell group MCG1 and a second memory cell group MCG2 by the dummy cell MD3. For example, the first memory cell group MCG1 is disposed between the dummy cell MD1 and the dummy cell MD3. The first memory cell group MCG1 includes memory cells M0~M47. The second memory cell group MCG2 is disposed between the dummy cell MD2 and the dummy cell MD3. The second memory cell group MCG2 includes memory cells M48~M95, but the present disclosure is not limited thereto. The first memory cell group MCG1 can be the first deck in a 3D NAND flash memory block. The second memory cell group MCG2 may be a second layer different from the first layer in a 3D NAND flash memory block.

In this embodiment, the dummy word line DWL1 is connected to the dummy cell MD1. The dummy word line DWL2 is connected to the dummy cell MD2. The dummy word line DWL3 is connected to the dummy cell MD3. The word line WL0 is connected to the memory cell M0. The word line WL1 is connected to the memory cell M1, and so on. The word lines WL0~WL95 are divided into the first word line group WLG1 and the second word line group WLG2 by the dummy word line DWL3. The first word line group WLG1 includes word lines WL1~WL47. The second word line group WLG2 includes word lines WL48~WL95.

In this embodiment, when performing the second erase operation, the control circuit 120 applies the second erase voltage V2 to the bit line and/or the common source line corresponding to the target memory cell string STT1. When performing the second erase operation, the control circuit 120 applies the word line signal VWL having a voltage of approximately 0 to the first word line group WLG1 and the second word line group WLG2. Therefore, the control circuit 120 performs the second erase operation on all memory cells M0~M95.

Please refer to FIG. 1 and FIG. 9 simultaneously. FIG. 9 is a schematic diagram of a target memory cell string according to an embodiment of the present disclosure. In this embodiment, the connection of the target memory cell string STT1, the word lines WL0~WL95 and the dummy word lines DWL1~DWL3 has been clearly described in the embodiment of FIG. 8, so it will not be repeated here. In this embodiment, when performing the second erase operation, the control circuit 120 applies the second erase voltage V2 to the bit line and/or the common source line corresponding to the target memory cell string STT1. When performing the second erase operation, the control circuit 120 applies a word line signal VWL having a voltage of approximately 0 to the second word line group WLG2. In addition, the control circuit 120 floats the first word line group WLG1. Therefore, the control circuit 120 performs the second erase operation on the memory cells M48~M95. Therefore, the control circuit 120 does not perform the second erase operation on the memory cells M0~M47 (i.e., the remaining memory cells).

In some embodiments, when performing the second erase operation, the control circuit 120 applies a word line signal VWL having a voltage of approximately 0 to the first word line group WLG1 and floats the second word line group WLG2. Therefore, the control circuit 120 performs the second erase operation M0~M47 on the memory cells M0~M47.

Based on FIG. 8 and FIG. 9 , the control circuit 120 can apply substantially 0 voltage to at least one of the first word line group WLG1 and the second word line group WLG2.

Please refer to FIG. 1 and FIG. 10 , which is a schematic diagram of a target memory cell string according to an embodiment of the present disclosure. In this embodiment, the connection of the target memory cell string STT1, word lines WL0~WL95 and dummy word lines DWL1~DWL3 has been clearly explained in the embodiment of FIG. 8 , so it will not be repeated here. In this embodiment, when performing the second erase operation, the control circuit 120 floats at least one word line in the first word line group WLG1 and the second word line group WLG2 that is adjacent to the third dummy word line DWL3. For example, the word line WL47 in the first word line group WLG1 and the word line WL48 in the second word line group WLG2 are adjacent to the third dummy word line DWL3. When performing the second erase operation, the control circuit 120 applies the second erase voltage V2 to the bit line and/or the common source line corresponding to the target memory cell string STT1. When performing the second erase operation, the control circuit 120 applies the word line signal VWL having a voltage of approximately 0 to the word lines WL0-WL46, WL49-WL95. Therefore, the control circuit 120 performs the second erase operation on the memory cells M0-M46, M49-M95. When performing the second erase operation, the control circuit 120 floats the word lines WL47, WL48 adjacent to the third dummy word line DWL3. Therefore, the control circuit 120 does not perform the second erase operation on the memory cells M47 and M48 (i.e., the remaining memory cells) adjacent to the dummy cell MD3.

Please refer to FIG. 1 and FIG. 11 at the same time. FIG. 11 is a flow chart of an operation method according to an embodiment of the present disclosure. In this embodiment, the operation method S100 is used for the memory device 100. The operation method S100 includes steps S110 to S130. In step S110, the control circuit 120 provides a first erase voltage V1 to perform a first erase operation on the target memory cell string STT1 to STT4 of the selected memory block MBK_T in the memory block MBK. In step S120, the control circuit 120 performs a programming operation on the target memory cell string STT1 to STT4 after the first erase operation. In step S130, the control circuit 120 provides a second erase voltage V2 after the programming operation to perform a second erase operation on at least a portion of the memory cells of each of the plurality of target memory cell strings STT1-STT4. The second erase voltage V2 is lower than the first erase voltage V1. The first erase operation and the second erase operation have been clearly described in at least one of the embodiments of FIG. 1 to FIG. 10, so they will not be repeated here.

In summary, after executing the programming operation, the memory device 100 performs a second erase operation on at least a portion of the memory cells of each of the plurality of target memory cell strings. The second erase operation adjusts the charge loss of the memory cells after executing the programming operation. The difference between the charge losses of the plurality of memory cells can be reduced. In this way, the difference between the charge losses of the plurality of memory cells can be reduced. In addition, for the application of multi-level memory cells, since the difference between the read windows can be reduced, the errors of the data read operation or the programming error correction operation can also be reduced. In this way, the memory device provides a high-performance, large-capacity storage medium.

Although the present disclosure has been disclosed as above by way of embodiments, it is not intended to limit the present disclosure. Any person with ordinary knowledge in the relevant technical field may make some changes and modifications within the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the scope defined by the attached patent application.

100: Memory device

110:Memory array

120: Control circuit

MBK: memory block

MBK_T: Select memory block

STT1~STT4: target memory unit string

V1: First erase voltage

V2: Second erase voltage

Claims (20)

A memory device comprises: a memory array comprising a plurality of memory blocks; and a control circuit coupled to the memory array and configured to provide a first erase voltage to perform a first erase operation on a plurality of target memory cell strings of a selected memory block among the memory blocks, perform a programming operation on the target memory cell strings after the first erase operation, and provide a second erase voltage to perform a second erase operation on at least a portion of the memory cells of each of the target memory cell strings after the programming operation, wherein the second erase voltage is less than the first erase voltage. The memory device of claim 1, wherein a difference between the second erase voltage and the first erase voltage is in a range of 7 to 13 volts. The memory device of claim 1, wherein when performing the second erase operation, the control circuit applies substantially zero voltage to one or more corresponding word lines connected to the at least a portion of the memory cells. A memory device as described in claim 1, wherein the selected memory block includes: a common source line; a plurality of bit lines extending along a first direction and arranged along a second direction; and a plurality of word lines extending along a plane defined by the first direction and the second direction and arranged along a third direction, wherein the first direction, the second direction and the third direction are not parallel to each other, each of the target memory cell strings is respectively coupled between a corresponding bit line among the bit lines and the common source line, a plurality of memory cells of each of the target memory cell strings are connected in series along the third direction, and the memory cells of each of the target memory cell strings are respectively coupled to a corresponding word line of the word lines. A memory device as described in claim 4, wherein the control circuit applies the first erase voltage to the common source line and at least one of the bit lines to perform the first erase operation, and applies the second erase voltage to the common source line and at least one of the bit lines to perform the second erase operation. A memory device as described in claim 4, wherein a remaining portion of the target memory cell strings on which the second erase operation has not been performed is floated. The memory device as described in claim 4, wherein the selected memory block further comprises: a first virtual word line extending along the plane defined by the first direction and the second direction; and a second virtual word line extending along the plane defined by the first direction and the second direction, wherein the word lines are arranged between the first virtual word line and the second virtual word line. The memory device as described in claim 7, wherein the selected memory block further includes: A third virtual word line is arranged between the first virtual word line and the second virtual word line, and the word lines are divided into a first word line group and a second word line group by the third virtual word line. The memory device as described in claim 8, wherein when performing the second erase operation, the control circuit applies a word line signal to at least one of the first word line group and the second word line group. The memory device as described in claim 8, wherein when performing the second erase operation, the control circuit floats at least one word line in the first word line group and the second word line group that is adjacent to the third dummy word line. An operating method for a memory device, wherein the memory device includes a memory array, wherein the memory array includes a plurality of memory blocks, wherein the operating method includes: Providing a first erase voltage to perform a first erase operation on a plurality of target memory cell strings of a selected memory block among the memory blocks; Performing a programming operation on the target memory cell strings after the first erase operation; and Providing a second erase voltage after the programming operation to perform a second erase operation on at least a portion of the memory cells of each of the target memory cell strings, wherein the second erase voltage is less than the first erase voltage. The operating method of claim 11, wherein the difference between the second erase voltage and the first erase voltage is in the range of 7 to 13 volts. The operating method as described in claim 11, wherein the step of providing the second erase voltage after the programming operation to perform the second erase operation on the at least a portion of the memory cells of each of the target memory cell strings includes: When performing the second erase operation, applying substantially 0 voltage to one or more corresponding word lines connected to the at least a portion of the memory cells. The operating method as described in claim 11, wherein the selected memory block includes: a common source line; a plurality of bit lines extending along a first direction and arranged along a second direction; and a plurality of word lines extending along a plane defined by the first direction and the second direction and arranged along a third direction, wherein the first direction, the second direction and the third direction are not parallel to each other, each of the target memory cell strings is respectively coupled between a corresponding bit line among the bit lines and the common source line, and a plurality of memory cells of each of the target memory cell strings are connected in series along the third direction, and each of the memory cells of the target memory cell strings is respectively coupled to a corresponding word line of the word lines. The operating method as described in claim 14, wherein: The step of providing the first erase voltage to perform the first erase operation on the target memory cell strings of the selected memory block in the memory blocks includes: Applying the first erase voltage to the common source line and at least one of the bit lines to perform the first erase operation; and The step of providing the second erase voltage to perform the second erase operation on the at least a portion of the memory cells of each of the target memory cell strings includes: Applying the second erase voltage to the common source line and at least one of the bit lines to perform the second erase operation. The operating method as described in claim 14, wherein the step of providing the second erase voltage after the programming operation to perform the second erase operation on at least a portion of the memory cells of each of the target memory cell strings comprises: Floating a remaining portion of the memory cells of the target memory cell strings that are not subjected to the second erase operation. The operating method as described in claim 14, wherein the selected memory block further includes: a first virtual word line extending along the plane defined by the first direction and the second direction; and a second virtual word line extending along the plane defined by the first direction and the second direction, wherein the word lines are arranged between the first virtual word line and the second virtual word line. The operating method as described in claim 17, wherein the selected memory block further includes: A third virtual word line is set between the first virtual word line and the second virtual word line, and the word lines are divided into a first word line group and a second word line group by the third virtual word line. The operating method as described in claim 18, wherein the step of providing the second erase voltage after the programming operation to perform the second erase operation on at least a portion of the memory cells of each of the target memory cell strings includes: When performing the second erase operation, applying a word line signal to at least one of the first word line group and the second word line group. The operating method as described in claim 18, wherein the step of providing the second erase voltage after the programming operation to perform the second erase operation on the at least a portion of the memory cells of each of the target memory cell strings includes: When performing the second erase operation, floating the first word line group and at least one word line in the second word line group adjacent to the third dummy word line.

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