TWI911976B - Operation method for memory device and memory device therefore - Google Patents

Abstract

An operation method for a memory device and a memory device therefore are provided. The memory device may be a 3D NAND flash memory with high capacity and high performance. The operation method comprises: performing a programming operation to the plurality of the memory cells based on an i-th potential state. The programming operation to the plurality of the memory cells based on an i-th potential state comprises: in a program pulse phase, applying a program pulse corresponding to the i-th potential state to a plurality of first memory cells corresponding to the i-th potential state; and, in a verification phase after the program pulse phase, performing a first sensing operation to a plurality of second memory cells in the (i-1)-th potential state to verify a situation of threshold voltage distributions of the plurality of the second memory cells, and performing a second sensing operation to the plurality of the first memory cells to implement a program verification operation of the i-th potential state.

Description

Operating methods of memory devices and memory devices themselves

This invention relates to data processing technology for a memory device (e.g., stereoscopic and gated flash memory), and more particularly to a method of operating a memory device and the memory device thereof.

High-capacity and high-performance integrated circuit memory, including 3D NAND flash memory, is under continuous development. The aim is to increase data storage density by reducing the size of memory cells using 3D stacking technology and triple-level cells (TLC).

Multilevel memory types, such as multilevel cell (MLC), tertiary cell (TLC), and quadrilevel cell (QLC), can store multi-bit data through multiple critical voltage distribution regions. For example, a tertiary cell (TLC) can have an erase state S0 and potential states S1 to S7 after being programmed. In some applications, it's desirable to know the distribution of critical voltages in each memory cell after programmed operations to facilitate subsequent memory operations (e.g., verification of increment-step-pulse-programming (ISPP) operations, programmed operations on other memory regions, adjustment or manipulation of the tail region/lower boundary of the critical voltage distribution, etc.). However, knowing the number of memory cells in the upper or lower part of potential states S1-S7 requires additional time overhead. Therefore, reducing the time overhead of memory devices when accessing data in memory cells is one research direction.

This invention provides an operation method for a memory device and the memory device thereof, which obtains the critical voltage distribution by performing sensing operations on the memory cells of the previous potential state in the verification phase of the programmed operation, thereby reducing the time overhead of reading operations on the memory cells.

This invention provides a method for operating a memory device. The memory device includes a memory block having a plurality of memory cells. Each of the plurality of memory cells includes N latent states relating to a plurality of critical voltage distributions, where N is a positive integer. The method of operation includes performing a programmed operation on the plurality of memory cells based on an i-th latent state among the N latent states, where i is a positive integer greater than 1 and less than or equal to N. The programmed operation based on the i-th potential state includes: in a programmed pulse phase, applying a programmed pulse corresponding to the i-th potential state to a plurality of first memory cells corresponding to the i-th potential state; and in a verification phase following the programmed pulse phase, performing a first sensing operation on a plurality of second memory cells of the (i-1)-th potential state to verify the critical voltage distribution of the plurality of second memory cells, and performing a second sensing operation on the plurality of first memory cells to implement a programmed verification operation for the i-th potential state.

The memory device proposed in this embodiment includes a memory array and a memory controller. The memory array includes a plurality of memory cells. Each of the plurality of memory cells includes N potential states relating to a plurality of critical voltage distributions, where N is a positive integer. The memory controller is coupled to the memory array. The memory controller is configured to perform a programmed operation on the plurality of memory cells based on an i-th potential state among the N potential states, where i is a positive integer greater than 1 and less than or equal to N. The programmed operation based on the i-th latent state includes: in a programmed pulse phase, applying a programmed pulse corresponding to the i-th latent state to a plurality of first memory cells corresponding to the i-th latent state; and in a verification phase following the programmed pulse phase, performing a first sensing operation on a plurality of second memory cells of the (i-1)-th latent state to verify the critical voltage distribution of the plurality of second memory cells, and performing a second sensing operation on the plurality of first memory cells to implement a programmed verification operation for the i-th latent state.

Based on the above, the memory device operation method and the memory device described in this embodiment of the invention insert a sensing operation on the memory cell of the previous latent state into the programmed operation based on each latent state to verify the critical voltage distribution of the previous latent state. Furthermore, the programmed operation of each latent state does not experience a significant increase in operation time due to the inserted sensing operation. The aforementioned critical voltage distribution can be the upper and lower halves of the critical voltage distribution of the memory cell of the previous latent state. Therefore, this embodiment of the invention places the step of verifying the critical voltage distribution within the programmed operation, reducing the time overhead of reading operations on the memory cell.

Figure 1 is an equivalent circuit diagram of a memory block 150 in a three-dimensional (3D) reverse-gate NAND memory device 10 according to an embodiment of the present invention. The memory block 150 is part of a memory array in the memory device 10. Memory cells (e.g., memory cell M') are arranged in a three-dimensional manner in the memory block 150, for example, in an XYZ coordinate system. This does not mean that the circuit of the 3D NAND memory device is limited to a three-dimensional manner. In one example, the memory block 150 may be divided into four sub-blocks (e.g., Sub0 to Sub3), each of which can be controlled independently.

A string (e.g., string 100, string 101, or string 102) comprises multiple memory cells (e.g., memory cells M') connected in series along the Z direction. A single memory cell (e.g., memory cell M') in the string (e.g., string 100) corresponds to a character line (e.g., character line WLi+1). A character line (e.g., character line WLn) may correspond to a layer in the XY plane. Memory cell M may be configured as a string select transistor coupled to a string select line SSL (e.g., string select line SSL0), and another memory cell may be configured as a ground select transistor coupled to a ground select line GSL.

The string select transistor and the ground select transistor are located on opposite sides of the string (e.g., string 100). In this example, multiple strings (e.g., strings 100, 101, etc.) coupled to the same string select line SSL (e.g., string select line SSL0) on the same plane (e.g., a plane defined by the X and Z directions) can be defined as a sub-block (e.g., sub-block Sub0).

Each string (e.g., string 100, string 101, or string 102) is connected to the corresponding bit line (e.g., bit line BL1, BLn, or BLm) via a corresponding string select transistor on the string select line SSL (e.g., string select line SSL0). Strings (e.g., string 100) in the same column of different sub-blocks (e.g., sub-blocks Sub0, Sub1, etc.) along the Y direction are connected to the corresponding bit line (e.g., bit line BL1). The string select line SSL can be a conductor or conductive layer formed above the topmost character line layer (e.g., character line WL1). Each string (e.g., string 100, 101, or 102) can be connected to the same common source line CSL via a corresponding ground select transistor on the ground select line GSL. The ground select line GSL can be a conductive line or conductive layer formed below the bottommost character line layer (e.g., character line WLm). The common source line CSL can be a conductive layer formed above the substrate of the 3D memory device. The serial select lines SSL (e.g., serial select lines SSL0~SSL3) in memory block 150 can be on the same conductive layer, but divided into independent circuits. Each independent circuit (serial select line SSL) can independently control the operation of the corresponding sub-block (e.g., sub-blocks Sub0, Sub1, etc.) in memory block 150.

In one example, multiple memory cells (including memory cell M') coupled to the same character line or character line layer (e.g., character line WLn) in a subregion (e.g., subregion Sub0) can be defined as a page (in the Single-Level Memory (SLC) type). In another example, multiple memory cells (including memory cell M') coupled to the same character line or character line layer (e.g., character line WLn) in a subregion (e.g., subregion Sub0) can be defined as three pages (in the Triple-Level Memory (TLC) type). In the TLC type, these three pages include a high page, a middle page, and a low page. Memory cells M' located on the same character line (e.g., character line WLn) are subjected to the same voltage. Each character line (e.g., character line WLn) can be connected to a driver circuit, such as an X decoder (or scan driver). In one example, one or more virtual lines or layers (not shown) can be provided between the string select line SSL (e.g., string select lines SSL0~SSL3) and the character line layer (e.g., character line WL1), and between the ground select line GSL and the bottommost character line layer (e.g., character line WLm). In another example, one or more virtual lines or layers (not shown) can be provided in the middle portion of the strings (e.g., strings 100, 101, 102). The memory device 10 also includes a memory controller 110 for implementing corresponding operations on the memory cells.

Figure 2 is a schematic diagram illustrating multiple critical voltage distributions (e.g., erased state S0 and potential states S1-S7) using a three-level cell (TLC) as an example, according to the first embodiment of the present invention. Figure 2 shows the critical voltage distributions exhibited by the memory cells after programmed operations. These critical voltage distributions can be distinguished into erased state S0 and potential states S1-S7. The erased state S0 and potential states S1-S7 can be distinguished by reference voltages V1-V7. Potential states S1-S7 correspond to critical voltage distributions PD1-DP7, respectively.

In some applications, it may be necessary to know whether the critical voltage distributions PD1~DP7 are appropriate. For example, it may be necessary to know the number of the upper half (e.g., the number of the upper half SU_1~SU_7 shown in Figure 2) and the number of the lower half (e.g., the number of the lower half SD_1~SD_7 shown in Figure 2) of the critical voltage distributions PD1~DP7 as a basis for whether to 'adjust or fix the tail of the critical voltage distributions PD1~DP7'. "Adjusting or fixing the tail of the critical voltage distribution PD1~DP7" means that when performing a programmed operation (such as an ISPP operation) on the next page, an additional programmed pulse can be added to the ISPP operation to operate the lower boundary of the lower half of the critical voltage distribution PD1~DP7 (that is, to fix the tail of the critical voltage distribution PD1~DP7).

Therefore, to know the number of the upper half SU_1~SU_7 and the number of the lower half SD_1~SD_7 in the critical voltage distribution PD1~DP7, it is necessary to perform 7 additional read operations based on the reference voltages VS1~VS7, which requires additional execution time.

This invention embodiment inserts a sensing operation on the memory cells of the previous latent state (e.g., latent state S1) into the programmed operation based on a certain latent state (e.g., latent state S2) to verify the critical voltage distribution of the previous latent state (e.g., to know the number of the upper and lower halves of the critical voltage distribution in the previous latent state). Furthermore, the programmed operation of each latent state is not prolonged due to the inserted sensing operation. Therefore, this invention embodiment sets the step of verifying the critical voltage distribution within the programmed operation, reducing the time overhead of the memory device in performing data access.

Figure 3 is a flowchart of an operation method of a memory device according to an embodiment of the present invention. The operation method described in Figure 3 can be implemented by the memory device 10 of Figure 1. Furthermore, the control method described in Figure 3 can be applied to memory devices with different memory cell types. The multiple memory cells in the memory cell block 150 of Figure 1 can be multilevel memory cells. The aforementioned multilevel type can be one of multilevel cell (MLC), three-level cell (TLC), and four-level cell (QLC). Figure 4 is a schematic diagram of the signals in step S300 according to the first embodiment of the present invention.

Please refer to Figures 1, 3, and 4 simultaneously. The operation method described in Figure 3 mainly includes step S300. The memory controller 110 in Figure 1 performs standardized operations on multiple memory cells based on the i-th latent state among N latent states. i is a positive integer greater than 1 and less than or equal to N. Taking a three-level cell (TLC) as an example, N is 7. For example, TLC type memory cells include latent states S1~S7 in Figure 2. i is one of 2 to 7. For ease of explanation, i can be assumed to be 2 here.

Step S300 includes steps S310 to S360. In step S310, during the programmed pulse phase PPP, the memory controller 110 of FIG1 applies a programmed pulse corresponding to the i-th latent state (e.g., latent state S2) to a plurality of first memory cells corresponding to the i-th latent state (e.g., latent state S2).

In step S320, during the verification phase VP following the programmed pulse phase PPP, the memory controller 110 in Figure 1 performs a first sensing operation on multiple second memory cells in the (i-1)th latent state (e.g., latent state S1) in the first time phase STP11 to verify the critical voltage distribution of these second memory cells. The first sensing operation can also be referred to as the state verification operation of multiple second memory cells in the (i-1)th latent state (e.g., latent state S1). In this embodiment, the "first memory cell" refers to the memory cell to be programmed into the i-th potential state (e.g., potential state S2), and the "second memory cell" refers to the memory cell to be programmed into the (i-1)-th potential state (e.g., potential state S1). Therefore, the first memory cell and the second memory cell are not the same.

The detailed steps of step S320 are as follows: In the first time period STP11, the critical voltage of each second memory cell is sensed by comparing the current obtained at the sensing end of each second memory cell for the (i-1)th latent state (e.g., latent state S1) with a reference level. This reference level is related to the reference voltage Vs1 and corresponds to a predetermined sensing time (e.g., the first time period STP11).

When the current obtained by the sensing end of the second memory cell in the first time period STP11 is less than the predetermined current corresponding to the reference level (the logical value in this embodiment is "0"), it indicates that this second memory cell will be counted in the first part of the critical voltage distribution corresponding to the second memory cell, SU_i-1 (or, the upper half of the value). That is, the first part of the value SU_i-1 is the count of the first part of the memory cells in the (i-1)th latent state (e.g., latent state S1) as the first verification result, and this first verification result corresponds to the upper half of the critical voltage distribution of the second memory cell (e.g., critical voltage distribution PD1 in Figure 2) (e.g., the upper half of the value SU_1 in Figure 2).

When the current obtained by the sensing end of the second memory cell in the first time period STP11 is greater than the predetermined current corresponding to the reference level (the logical value in this embodiment is "1"), it indicates that this second memory cell will be counted in the second part of the critical voltage distribution of the second memory, SD_i-1 (or, the lower half of the value). That is, the second part of the value SD_i-1 is the number of the second part of the memory cells in the (i-1)th latent state (e.g., latent state S1) as a second verification result, and this second verification result corresponds to the lower half of the critical voltage distribution of the second memory (e.g., critical voltage distribution PD1 in Figure 2) (e.g., the lower half of the value SD_1 in Figure 2).

Through the aforementioned step S320, the upper half (e.g., the number of the first part SU_1) and the lower half (e.g., the number of the second part SD_1) values of the critical voltage distribution of multiple second memory cells in the (i-1)th latent state (e.g., latent state S1) after programming can be obtained to verify the critical voltage distribution of the second memory cells.

In step S330, the memory controller 110 performs a second sensing operation on multiple first memory cells of the i-th latent state (e.g., latent state S2) during the verification phase VP to implement a programmed verification operation for the i-th latent state (e.g., latent state S2). The second sensing operation can also be referred to as a programmed verification operation of multiple first memory cells of the i-th latent state (e.g., latent state S2).

The detailed steps of step S330 are as follows: In the second time period STP12, the critical voltage of each first memory cell is sensed by comparing the current obtained at the sensing terminal of each first memory cell in the i-th latent state (e.g., latent state S2) with a reference level. This reference level may be related to a reference voltage V2, and this reference level corresponds to a predetermined sensing time (e.g., the second time period STP12). The durations of the first time period STP11 and the second time period STP12 in this embodiment may be different.

When the current obtained by the sensing end of the first memory cell in the second time segment STP12 is less than the predetermined current corresponding to the reference level (the logical value in this embodiment is "0"), it indicates that the first memory cell is successfully verified, and the count is recorded in the verification success value CSX_pass corresponding to the critical voltage distribution PSi-1 of the first memory cell. Conversely, when the current obtained by the sensing end of the first memory cell in the second time segment STP12 is greater than the predetermined current corresponding to the reference level (the logical value in this embodiment is "1"), it indicates that the first memory cell is verified unsuccessfully, and the count is recorded in the verification failure value CSX_fail corresponding to the critical voltage distribution PSi-1 of the first memory cell.

In step S340, the memory controller 110 determines whether the aforementioned first memory cell has passed the programmed verification operation of the i-th potential state (e.g., potential state S2). The condition for passing the programmed verification operation is that the critical voltage of each first memory cell is greater than or equal to the reference voltage V2 (e.g., as shown in the critical voltage distribution Psi-T in Figure 4), that is, the verification failure value CSX_fail is zero. If step S340 is false, the process proceeds to step S350, where the memory controller 110 gradually increases the voltage of the programmed pulses and applies the programmed pulses multiple times to the first memory cell of the latent state S2 in step S310. Conversely, if step S340 is true and step S320 has already been performed, the process proceeds to step S360, where the memory controller 110 completes the programming operation for the i-th latent state. Furthermore, if 'i' is not N, 'i' is incremented by 1, and this embodiment continues with the programming operation for the next latent state. The programmed operation consisting of steps S310, S320 to S350 in this embodiment can be called the ISPP operation.

In this embodiment, the ISPP operation may be executed multiple times, while the state verification operation for the (i-1)th potential state (e.g., potential state S1) in step S320 only needs to be performed once. Step S320 does not necessarily need to be performed multiple times. For example, the execution time of step S320 can be set to one of the last one to three procedural verification operations of the ISPP operation.

In the first embodiment of Figure 4, the first time segment STP11 of the first sensing operation (state verification operation) is different from the second time segment STP12 of the second sensing operation (programmed verification operation). Both the first time segment STP11 and the second time segment STP12 are located in the verification phase VP. The first time segment STP11 is different from the second time segment STP12 and they do not overlap.

In the verification phase VP, a programmed pulse corresponding to the i-th latent state (e.g., latent state S2) is applied to the word line of the first memory cell, as shown by waveform SelWL in Figure 4. The voltage on the word line of the unselected memory cell is shown by waveform UnSelWL in Figure 4. During the second time phase STP12 of the second sensing operation, the second memory cell is masked. Conversely, during the first time phase STP11 of the first sensing operation, the first memory cell is masked. The second memory cell is also masked during the programmed pulse phase PPP.

Figure 5 is a schematic diagram of the state of each memory cell in the programmed verification operation for latent state S2 in an embodiment of the present invention. Referring to Figure 5, the first sensing operation is to perform a state verification operation on the memory cell (second memory cell) of latent state S1. When the current obtained by the sensing terminal of the second memory cell in the first time period STP11 is less than the predetermined current corresponding to the reference level (the logical value in this embodiment is "0"), it indicates that this second memory cell is counted in the first part of the number SU_1 of the critical voltage distribution corresponding to the second memory cell. On the other hand, when the current obtained by the sensing end of the second memory cell in the first time period STP11 is greater than the predetermined current corresponding to the reference level (the logical value in this embodiment is "1"), it means that this second memory cell is counted in the second part of the quantity SD_1 corresponding to the critical voltage distribution of the second memory.

The second sensing operation is to perform a programmed verification operation on the memory cell (first memory cell) of latent state S2. When the current obtained by the sensing end of the first memory cell in the second time segment STP12 is less than the predetermined current corresponding to the reference level (the logical value in this embodiment is "0"), it indicates that the first memory cell of latent state S2 has been successfully verified. Conversely, when the current obtained by the sensing end of the first memory cell in the second time period STP12 is greater than the predetermined current corresponding to the reference level (the logical value in this embodiment is "1"), it indicates that the programming verification operation of the first memory cell in the potential state S2 has failed, and the voltage of the programming pulse needs to be gradually increased to continue the programming verification operation of the first memory cell in the potential state S2.

Figure 6 is a schematic diagram of the signals in step S300 according to the second embodiment of the present invention. The main difference between the second embodiment of Figure 6 and the first embodiment of Figure 4 is that the first time segment STP21 for performing the first sensing operation (state verification operation) is the same as the second time segment STP22 for performing the second sensing operation (programmed verification operation). Both the first time segment STP21 and the second time segment STP22 are located in the verification phase VP. In the first time segment STP21 for performing the first sensing operation, the memory controller 110 of Figure 1 applies a first bit line voltage BLP21 to the bit lines BL of multiple second memory cells. On the other hand, in the second time segment STP22 for performing the second sensing operation, the memory controller 110 of Figure 1 applies a second bit line voltage BLP22 to the bit lines BL of multiple first memory cells. The voltage value of the first bit line voltage BLP21 is less than the voltage value of the second bit line voltage BLP22. The second embodiment in Figure 6, in addition to conforming to the steps in the control method of Figure 3, also conforms to the state of each memory cell in the programmed verification operation for the latent state S2 shown in Figure 5.

In summary, the memory device operation method and the memory device described in this invention insert sensing operations on the memory cells of the previous latent state into the programmed operations based on each latent state to verify the critical voltage distribution. Furthermore, the programmed operations for each latent state do not experience a significant increase in operation time due to the inserted sensing operations. The aforementioned critical voltage distribution can be the upper and lower halves of the critical voltage distribution of the memory cells in the previous latent state. Therefore, this invention sets the step of verifying the critical voltage distribution within the programmed operations, reducing the time overhead of reading operations on the memory cells.

Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone with ordinary skill in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended patent application.

10: Memory Device / 3D NAND Memory Device 100, 101, 102: Serial 110: Memory Controller 150: Memory Block S300~S360: Steps of Memory Device Operation M, M': Memory Cell Sub0~Sub3: Sub-block WL, WL1, WLi, WL1+1~WLn-1, WLn, WLm: Character Lines BL, BL1, BLn, BLm: Bit Lines SSL1~SSL3: Serial Select Lines GSL: Ground Select Lines CSL: Common Source Line S0: Erase State S1~S7: Latent State V1~V7, Vs1~Vs7: Reference Voltage SU_1~SU_7, SU_i-1: Number of Upper Half Units SD_1~SD_7, SD_i-1: Number of lower half components; PD1~DP7, PSi-1, PSi-T: Critical voltage distribution; PPP: Programmed pulse stage; VP: Verification stage; UnSelWL, SelWL: Waveform; STP11, STP21: First time segment; STP12, STP22: Second time segment; CSX_fail: Verification failure value; CSX_pass: Verification success value; BLP21: First bit line voltage; BLP22: Second bit line voltage.

Figure 1 is an equivalent circuit diagram of a memory block in a three-dimensional (3D) reverse-gate NAND memory device according to an embodiment of the present invention. Figure 2 is a schematic diagram illustrating multiple critical voltage distributions (e.g., erase state S0 and potential states S1-S7) using a three-level cell (TLC) memory cell as an example according to an embodiment of the present invention. Figure 3 is a flowchart of an operation method of a memory device according to an embodiment of the present invention. Figure 4 is a schematic diagram of each signal in step S300 according to the first embodiment of the present invention. Figure 5 is a schematic diagram of the state of each memory cell during the programmed verification operation for potential state S2 according to an embodiment of the present invention. Figure 6 is a schematic diagram of each signal in step S300 according to the second embodiment of the present invention.

S300~S360: Steps for operating the memory device

Claims (16)

A method of operating a memory device, wherein the memory device includes a memory block having a plurality of memory cells, each of the plurality of memory cells including N latent states relating to a plurality of critical voltage distributions, where N is a positive integer, the method of operating comprising: performing a programmed operation on the plurality of memory cells based on an i-th latent state among the N latent states, where i is a positive integer greater than 1 and less than or equal to N, wherein the programmed operation based on the i-th latent state includes: applying a programmed pulse corresponding to the i-th latent state to a plurality of first memory cells corresponding to the i-th latent state in a programmed pulse phase; and In a verification phase following the programmed pulse phase, a first sensing operation is performed on multiple second memory cells in the (i-1)th latent state to verify the critical voltage distribution of the multiple second memory cells, and a second sensing operation is performed on the multiple first memory cells to implement a programmed verification operation for the i-th latent state. The first sensing operation includes: sensing the critical voltage of the multiple second memory cells based on a predetermined sensing time at a reference level; and A first portion quantity and a second portion quantity are obtained, wherein the first portion quantity is a count of a first portion of memory cells as a first verification result, the first verification result corresponding to the upper half of a critical voltage distribution of the plurality of second memories, and the second portion quantity is a count of a second portion of memory cells as a second verification result, the second verification result corresponding to the lower half of the critical voltage distribution of the plurality of second memories. The method of operation as described in claim 1, wherein in the programmed operation based on the i-th potential state, the first sensing operation is performed once for the plurality of second memory cells. The operation method as described in claim 1, wherein a first time period for performing the first sensing operation is different from a second time period for performing the second sensing operation, both the first and second time periods are located in the verification phase, and the first time period is different from the second time period and they do not overlap. The method of operation as described in claim 1, wherein performing the first sensing operation includes: applying a first bit line voltage to the bit lines of the plurality of second memories during a first time period of performing the first sensing operation; and applying a second bit line voltage to the bit lines of the plurality of first memories during a second time period of performing the second sensing operation. The operating method as described in claim 4, wherein the first time segment is the same as the second time segment, and both the first time segment and the second time segment are located in the verification phase. The method of operation as described in claim 1, wherein the programmed pulse corresponding to the i-th potential state is applied to the character lines of the plurality of first memory cells, and the plurality of second memory cells are masked. The method of operation as described in claim 1, wherein the programmed operation is an incremental step pulse programmed (ISPP) operation. The method of operation as described in claim 7 further includes: when the programmed verification operation of the i-th potential state is not passed, progressively increasing the voltage of the programmed pulse, and applying the increased programmed pulse to the plurality of first memory cells corresponding to the i-th potential state. A memory device includes: a memory array comprising a plurality of memory cells, each of the plurality of memory cells including N latent states relating to a plurality of critical voltage distributions, where N is a positive integer; and a memory controller coupled to the memory array, wherein the memory controller is configured to: perform a programmed operation on the plurality of memory cells based on an i-th latent state among the N latent states, where i is a positive integer greater than 1 and less than or equal to N, wherein the programmed operation based on the i-th latent state includes: In a programmed pulse phase, a programmed pulse corresponding to the i-th latent state is applied to a plurality of first memory cells corresponding to the i-th latent state; and in a verification phase following the programmed pulse phase, a first sensing operation is performed on a plurality of second memory cells in the (i-1)-th latent state to verify the critical voltage distribution of the plurality of second memory cells, and a second sensing operation is performed on the plurality of first memory cells to implement a programmed verification operation for the i-th latent state, wherein performing the first sensing operation includes: sensing the critical voltage of the plurality of second memory cells based on a predetermined sensing time at a reference level; and A first portion quantity and a second portion quantity are obtained, wherein the first portion quantity is a count of a first portion of memory cells as a first verification result, the first verification result corresponding to the upper half of a critical voltage distribution of the plurality of second memories, and the second portion quantity is a count of a second portion of memory cells as a second verification result, the second verification result corresponding to the lower half of the critical voltage distribution of the plurality of second memories. The memory device as claimed in claim 9, wherein in the programmed operation based on the i-th potential state, the first sensing operation is performed once for the plurality of second memory cells. The memory device as claimed in claim 9, wherein a first time period for performing the first sensing operation is different from a second time period for performing the second sensing operation, both the first and second time periods are located in the verification phase, and the first time period is different from the second time period and they do not overlap. The memory device as claimed in claim 9, wherein performing the first sensing operation includes: applying a first bit line voltage to the bit lines of the plurality of second memories during a first time period of performing the first sensing operation; and applying a second bit line voltage to the bit lines of the plurality of first memories during a second time period of performing the second sensing operation. The memory device as claimed in claim 12, wherein the first time segment is the same as the second time segment, and both the first time segment and the second time segment are located in the verification phase. The memory device as claimed in claim 9, wherein the programmed pulse corresponding to the i-th potential state is applied to the character lines of the plurality of first memory cells and the plurality of second memory cells are masked. The memory device as described in claim 9, wherein the programming operation is an incremental step pulse programming (ISPP) operation. The memory device as claimed in claim 9, wherein the memory controller is further configured to: progressively increase the voltage of the programmed pulse when the programmed verification operation of the i-th potential state is not passed, and apply the increased programmed pulse to the plurality of first memory cells corresponding to the i-th potential state.