TWI870961B - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a semiconductor substrate, a fin-shaped structure, a first semiconductor wire, and a second semiconductor wire. The fin-shaped structure is disposed on the semiconductor substrate. The fin-shaped structure includes a semiconductor fin, a dielectric layer, and a barrier layer. The dielectric layer is disposed on the semiconductor fin. The barrier layer is disposed between the dielectric layer and the semiconductor fin in a thickness direction of the semiconductor substrate. The barrier layer includes a III-V compound semiconductor layer. The first semiconductor wire is disposed above the fin-shaped structure. The second semiconductor wire is disposed above the first semiconductor wire. The first semiconductor wire is disposed between the second semiconductor wire and the fin-shaped structure in the thickness direction of the semiconductor substrate. The first semiconductor wire is separated from the second semiconductor wire, and the first semiconductor wire directly contacts the dielectric layer.

Description

Semiconductor Devices

The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor device having a plurality of semiconductor wires and a manufacturing method thereof.

As semiconductor device technology continues to develop, it is difficult to continue to miniaturize the traditional planar metal-oxide-semiconductor (MOS) transistor process. Therefore, conventional technology proposes a solution to replace planar transistor devices with three-dimensional or non-planar multi-gate transistor devices. For example, dual-gate fin field effect transistor (Fin Field Effect Transistor, hereinafter referred to as FinFET) devices, tri-gate FinFET devices, and omega FinFET devices have been proposed. In addition, gate-all-around (GAA) transistor devices using nanowires as channels have recently been developed as a solution to continue to increase device integration and device performance. However, under the GAA design concept, process and/or structural design is still required to further improve process yield and/or electrical performance of semiconductor devices.

The present invention provides a semiconductor device and a method for manufacturing the same, which utilizes an opening formed in a dielectric layer to expose a portion of a semiconductor substrate, so that a semiconductor layer can grow from the semiconductor substrate exposed by the opening and be formed on the dielectric layer. In this way, a semiconductor layer with better quality can be formed on the dielectric layer, thereby achieving the effect of improving the process yield and/or the electrical performance of the semiconductor device.

According to one embodiment of the present invention, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps. A dielectric layer is formed on a semiconductor substrate. An opening is formed through the dielectric layer to expose a portion of the semiconductor substrate. A stacked structure is formed on the dielectric layer, and the stacked structure includes a first semiconductor layer, a sacrificial layer, and a second semiconductor layer. The first semiconductor layer is partially formed in the opening and partially formed on the dielectric layer, the sacrificial layer is formed on the first semiconductor layer, and the second semiconductor layer is formed on the sacrificial layer. A patterning process is performed to form at least one fin structure on the semiconductor substrate. The stacked structure is patterned by a patterning process, and the fin structure includes a portion of a first semiconductor layer, a portion of a sacrificial layer, and a portion of a second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin structure. The first semiconductor layer in the fin structure is etched by the etching process to form a first semiconductor line, and the second semiconductor layer in the fin structure is etched by the etching process to form a second semiconductor line.

According to an embodiment of the present invention, the present invention further provides a semiconductor device, comprising a semiconductor substrate, a fin structure, a first semiconductor line and a second semiconductor line. The fin structure is disposed on the semiconductor substrate. The fin structure comprises a semiconductor fin, a dielectric layer and a barrier layer. The dielectric layer is disposed on the semiconductor fin, the barrier layer is disposed between the dielectric layer and the semiconductor fin in a thickness direction of the semiconductor substrate, and the barrier layer comprises a III-V compound semiconductor layer. The first semiconductor line is disposed on the fin structure. The second semiconductor line is disposed on the first semiconductor line. The first semiconductor line is arranged between the second semiconductor line and the fin structure in the thickness direction of the semiconductor substrate. The first semiconductor line and the second semiconductor line are separated from each other, and the first semiconductor line directly contacts the dielectric layer.

The following detailed description of the present invention has disclosed sufficient details to enable a person skilled in the art to practice the present invention. The embodiments described below should be considered illustrative rather than restrictive. It will be apparent to a person of ordinary skill in the art that various changes and modifications in form and details may be made without departing from the spirit and scope of the present invention.

Before further describing various embodiments, specific terms used throughout the text are explained below.

The meanings of the terms “on,” “over,” and “over…” should be interpreted in the broadest manner, so that “on…” means not only “directly on” something, but also includes being on something with other intervening features or layers therebetween, and “over…” or “over…” means not only being “over” or “above” something, but also includes being “over” or “above” something with no other intervening features or layers therebetween (i.e., directly on something).

The term "etching" is generally used herein to describe a process for patterning a material such that at least a portion of the material remains after the etching is complete. In contrast, when "removing" material, substantially all of the material may be removed in the process. However, in some embodiments, "removing" may be considered a broad term and may include etching.

The terms "forming" or "disposing" are used hereinafter to describe the act of applying a material layer to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a semiconductor device according to a first embodiment of the present invention. As shown in FIG. 1, the present embodiment provides a semiconductor device 101, which includes a semiconductor substrate 10, a fin structure (e.g., a second fin structure FS2 shown in FIG. 1), a first semiconductor wire 16W, and a second semiconductor wire 20W. The second fin structure FS2 is disposed on the semiconductor substrate 10. The second fin structure FS2 includes a semiconductor fin 10F, a barrier layer 12, and a dielectric layer 14. The dielectric layer 14 is disposed on the semiconductor fin 10F, and the barrier layer 12 is disposed between the dielectric layer 14 and the semiconductor fin 10F in a thickness direction (e.g., a third direction D3 shown in FIG. 1 ) of the semiconductor substrate 10. The first semiconductor line 16W is disposed on the second fin structure FS2. The second semiconductor line 20W is disposed on the first semiconductor line 16W. The first semiconductor line 16W is disposed between the second semiconductor line (20W) and the second fin structure FS2 in the thickness direction (e.g., the third direction D3) of the semiconductor substrate 10.

To further explain, in some embodiments, the semiconductor device 101 may include a plurality of second fin structures FS2, a plurality of first semiconductor lines 16W, and a plurality of second semiconductor lines 20W. Each second fin structure FS2 may extend along a first direction D1, and a plurality of second fin structures FS2 may be repeatedly arranged along a second direction D2. Each first semiconductor line 16W may extend along the first direction D1, and each first semiconductor line 16W may be arranged on a corresponding second fin structure FS2 in a third direction D3. Each second semiconductor line 20W may extend along the first direction D1, and each second semiconductor line 20W may be arranged on a corresponding second fin structure FS2 and a corresponding first semiconductor line 16W in the third direction D3. In other words, the extension direction of each first semiconductor line 16W, the extension direction of each second semiconductor line 20W, and the extension direction of each second fin structure FS2 may be parallel to each other and orthogonal to the thickness direction (eg, the third direction D3) of the semiconductor substrate 10, but is not limited thereto.

In addition, in some embodiments, the semiconductor device 101 may further include an isolation structure 36, a gate dielectric layer 38, and a gate structure GS. The isolation structure 36 may be disposed between adjacent second fin structures FS2, and the isolation structure 36 may cover the sidewalls of the second fin structure FS2. The gate dielectric layer 38 may be disposed on each first semiconductor line 16W and each second semiconductor line 20W, and the gate structure GS may extend along the second direction D2 and be disposed on the gate dielectric layer 38. In some embodiments, the gate structure GS and the gate dielectric layer 38 may surround mutually separated semiconductor lines (e.g., mutually separated first semiconductor line 16W and second semiconductor line 20W), thereby forming a gate-all-around (GAA) transistor structure, but the present invention is not limited thereto. In addition, in some embodiments, the semiconductor device 101 may further include a plurality of third semiconductor lines 24W, each of which may extend along the first direction D1, and each of which may be disposed on the corresponding second fin structure FS2 and the corresponding second semiconductor line 20W in the third direction D3. In other words, a plurality of mutually separated semiconductor lines (e.g., mutually separated first semiconductor line 16W, second semiconductor line 20W, and third semiconductor line 24W) may be stacked on each second fin structure FS2, thereby increasing the total surface area of the semiconductor lines covered by the gate structure GS, thereby achieving the effect of improving the electrical performance of the semiconductor device 101.

In some embodiments, the semiconductor substrate 10 may include a substrate formed of a III-V compound semiconductor material, such as a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or a substrate formed of other suitable III-V compound semiconductor materials, but the invention is not limited thereto. In some embodiments, the semiconductor substrate 10 may include a base substrate (such as a silicon substrate) and a III-V compound semiconductor material layer formed thereon. In some embodiments, the semiconductor fin 10F in each second fin structure FS2 may be directly connected to the semiconductor substrate 10, and the material composition of the semiconductor fin 10F may be the same as the material composition of the semiconductor substrate 10, but the invention is not limited thereto. For example, the semiconductor fin 10F can be formed by partially etching the semiconductor substrate 10, so the semiconductor fin 10F can also be regarded as a part of the semiconductor substrate 10 and has the same material composition, but the present invention is not limited thereto. In addition, the barrier layer 12 in each second fin-shaped structure FS2 can include a III-V compound semiconductor layer or a barrier layer formed by other suitable barrier materials. It is worth noting that in some embodiments, the barrier layer 12 can be used to protect the semiconductor substrate 10 during the process of forming the dielectric layer 14, so as to prevent the material of the semiconductor substrate 10 from being affected by the process of forming the dielectric layer 14 and indirectly affecting the quality of other semiconductor layers subsequently formed on the semiconductor substrate 10. The barrier layer 12 can preferably be formed on the semiconductor substrate 10 using an epitaxial growth process, so the barrier layer 12 can include a III-V compound material different from the semiconductor substrate 10, but is not limited to this. For example, the material of the barrier layer 12 may include aluminum gallium nitride (AlGaN), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs) or other suitable III-V compound materials. Therefore, the material composition of the barrier layer 12 may be different from the material composition of the dielectric layer 14 and the material composition of the semiconductor fin 10F, but is not limited thereto.

In some embodiments, the material of the dielectric layer 14 may include oxides (e.g., aluminum oxide, silicon oxide), nitrides, oxynitrides, or other suitable dielectric materials. It is worth noting that in some embodiments, the first semiconductor line 16W may directly contact the dielectric layer 14, so part of the dielectric layer 14 may also be used as a gate dielectric layer, but the invention is not limited thereto. In this case, the material of the dielectric layer 14 may be the same as the material of the gate dielectric layer 38, but the invention is not limited thereto. In addition, the isolation structure 36 may include a single layer or multiple layers of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, but the invention is not limited thereto. The first semiconductor line 16W, the second semiconductor line 20W, and the third semiconductor line 24W may include III-V compound semiconductor materials, such as gallium nitride, gallium arsenide, indium phosphide, or other suitable III-V compound semiconductor materials. It is worth noting that in some embodiments, the first semiconductor line 16W may be formed by patterning a semiconductor layer formed by epitaxial growth on the semiconductor substrate 10, so the material composition of the first semiconductor line 16W may be the same as the material composition of the semiconductor fin 10F and the material composition of the semiconductor substrate 10, but the present invention is not limited thereto. In addition, in consideration of simplifying the manufacturing process, the first semiconductor line 16W, the second semiconductor line 20W, and the third semiconductor line 24W may be formed by the same semiconductor material, thereby simplifying the corresponding etching steps, but the present invention is not limited thereto. In some embodiments, the first semiconductor line 16W, the second semiconductor line 20W, and/or the third semiconductor line 24W may be formed of different semiconductor materials as needed. As needed, the cross-section of the first semiconductor line 16W, the second semiconductor line 20W, and/or the third semiconductor line 24W may be a perfect circle, an ellipse, a square, a rectangle, a triangle, or a rhombus.

In some embodiments, the gate dielectric layer 38 may include silicon oxide, silicon oxynitride, high dielectric constant (high-k) material or other suitable dielectric materials. The high dielectric constant material may include, for example, hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), zirconium oxide (ZrO ₂ ) or other suitable high dielectric constant materials. In addition, the gate structure GS may include a single layer or multiple layers of conductive material. For example, the gate structure GS may include a work function layer 40 and a conductive layer 42 disposed on the work function layer 40. The gate dielectric layer 38 may be conformally formed on the first semiconductor line 16W, the second semiconductor line 20W, and the third semiconductor line 24W, and the work function layer 40 may be substantially conformally formed on the gate dielectric layer 38 and the isolation structure 36. The work function layer 40 may include tantalum nitride (TaN), titanium nitride (TiN), titanium carbide (TiC), titanium aluminide (TiAl), titanium aluminum carbide (TiAlC) or other suitable N-type or/and P-type work function materials, and the conductive layer 42 may include a low-resistance metal material such as aluminum, tungsten, copper, titanium aluminum alloy or other suitable low-resistance metal conductive materials, but is not limited thereto.

Please refer to Figures 2 to 13, and please refer to Figure 1 together. Figures 2 to 13 are schematic diagrams of the method for manufacturing the semiconductor device 101 of this embodiment, wherein Figure 3 is a schematic diagram of the state after Figure 2, Figure 4 is a schematic diagram of the state after Figure 3, Figure 5 is a schematic diagram of the state after Figure 4, Figure 6 is a schematic diagram of the state after Figure 5, Figure 7 is a schematic diagram of the state after Figure 6, and Figure 8 is a schematic diagram of the state after Figure 7. , FIG. 9 is a schematic diagram showing a state after FIG. 8, FIG. 10 is a schematic diagram showing a state after FIG. 9, FIG. 11 is a schematic diagram showing a state after FIG. 10, FIG. 12 is a schematic diagram showing a state after FIG. 11, FIG. 13 is a schematic diagram showing a cross-sectional state in another direction (for example, in the first direction D1) under the state of FIG. 12, and FIG. 1 can be regarded as showing a schematic diagram showing a state after FIG. 12. The method for manufacturing the semiconductor device 101 of the present embodiment may include but is not limited to the following steps. First, as shown in FIG. 2, a semiconductor substrate 10 is provided, and a dielectric layer 14 is formed on the semiconductor substrate 10. In some embodiments, a barrier layer 12 may be formed on the semiconductor substrate 10 before the dielectric layer 14 is formed. In other words, the dielectric layer 14 may be formed on the barrier layer 12, and the barrier layer 12 may be located between the dielectric layer 14 and the semiconductor substrate 10. Then, as shown in FIGS. 2 to 3, a plurality of openings OP are formed, and each opening OP may penetrate the dielectric layer 14 to expose a portion of the semiconductor substrate 10. When the barrier layer 12 is located between the dielectric layer 14 and the semiconductor substrate 10, each opening OP may further penetrate the barrier layer 12 to expose a portion of the semiconductor substrate 10, but the invention is not limited thereto. In some embodiments, the opening OP may be formed by a patterning process such as a lithography process, and in this patterning process, a single or multiple etching steps may be used to etch the dielectric layer 14 and the barrier layer 12, respectively. The dielectric layer 14 and the barrier layer 12 may be etched into a plurality of patterned dielectric layers 14A and a plurality of patterned barrier layers 12A, and each patterned dielectric layer 14A and each patterned barrier layer 12A may substantially overlap each other in the third direction D3, but the present invention is not limited thereto.

Then, as shown in FIGS. 4 to 5 , a stacked structure MS is formed on the dielectric layer 14, and the stacked structure MS includes a first semiconductor layer 16, a sacrificial layer (e.g., the first sacrificial layer 18 shown in FIG. 5 ), and a second semiconductor layer 20. The first semiconductor layer 16 may be partially formed in the opening OP and partially formed on the dielectric layer 14, the first sacrificial layer 18 may be formed on the first semiconductor layer 16, and the second semiconductor layer 20 may be formed on the first sacrificial layer 18. In some embodiments, the first semiconductor layer 16 may be formed by performing an epitaxial growth process on the portion of the semiconductor substrate 10 exposed by each opening OP, so each opening OP may be filled with the first semiconductor layer 16, but the present invention is not limited thereto. In addition, in some embodiments, the material composition of the first semiconductor layer 16 can be the same as the material composition of the semiconductor substrate 10, but the present invention is not limited thereto. In some embodiments, the first semiconductor layer 16 can also be formed by using different materials and/or processes as needed. As shown in FIG. 4 , when the first semiconductor layer 16 is formed by an epitaxial growth process, in order to ensure that the first semiconductor layer 16 formed on the dielectric layer 14 has a sufficient thickness, the first semiconductor layer 16 is usually formed thicker. However, in this case, the surface flatness of the first semiconductor layer 16 is poor. Therefore, before forming the first sacrificial layer 18, a planarization process 91 may be performed on the first semiconductor layer 16, such as a chemical mechanical polishing (CMP) process or other suitable planarization method, to planarize the upper surface of the first semiconductor layer 16 and control the thickness of the first semiconductor layer 16 on the dielectric layer 14. In other words, a portion of the first semiconductor layer 16 may remain on the dielectric layer 14 after the planarization process 91.

In some embodiments, the stack structure MS may include a plurality of semiconductor layer/sacrificial layer pairs stacked in the third direction D3, and the number of the semiconductor layer/sacrificial layer pairs may be adjusted according to the number of semiconductor lines to be formed. For example, the stack structure MS may further include a second sacrificial layer 22, a third semiconductor layer 24, and a third sacrificial layer 26. The second sacrificial layer 22 may be formed on the second semiconductor layer 20, the third semiconductor layer 24 may be formed on the second sacrificial layer 22, and the third sacrificial layer 26 may be formed on the third semiconductor layer 24. In some embodiments, epitaxial growth or other suitable film forming processes may be used to form the first sacrificial layer 18, the second semiconductor layer 20, the second sacrificial layer 22, the third semiconductor layer 24 and the third sacrificial layer 26. Therefore, the first semiconductor layer 16, the second semiconductor layer 20 and the third semiconductor layer 24 may include III-V compound semiconductor materials such as gallium nitride, gallium arsenide, indium phosphide or other suitable III-V compound semiconductor materials, and the first sacrificial layer 18, the second sacrificial layer 22 and the third sacrificial layer 26 may include aluminum gallium nitride, aluminum gallium arsenide, indium gallium arsenide or other suitable III-V compound materials, but are not limited thereto. In some embodiments, the semiconductor layers and the sacrificial layers in the stacked structure MS may be formed with other suitable materials or/other suitable process methods as needed. It is worth noting that, in order to smoothly perform the etching process for removing the sacrificial layers in the subsequent process, the first semiconductor layer 16, the second semiconductor layer 20 and the third semiconductor layer 24 are preferably formed of the same semiconductor material, the first sacrificial layer 18, the second sacrificial layer 22 and the third sacrificial layer 26 are preferably formed of the same material, and the materials of the semiconductor layers and the sacrificial layers in the stacked structure MS must have a better etching selectivity for the etching process for removing the sacrificial layers, but the present invention is not limited thereto. In other words, the materials of each semiconductor layer and each sacrificial layer in the stacked structure MS can have a more suitable combination to ensure the subsequent process. For example, when the first semiconductor layer 16, the second semiconductor layer 20 and the third semiconductor layer 24 are formed of gallium nitride, the first sacrificial layer 18, the second sacrificial layer 22 and the third sacrificial layer 26 are preferably formed of aluminum gallium nitride; when the first semiconductor layer 16, the second semiconductor layer 20 and the third semiconductor layer 24 are formed of gallium arsenide, the first sacrificial layer 18, the second sacrificial layer 22 and the third sacrificial layer 26 are preferably formed of aluminum gallium nitride; The first sacrificial layer 18, the second sacrificial layer 22 and the third sacrificial layer 26 are preferably formed of aluminum gallium arsenide; when the first semiconductor layer 16, the second semiconductor layer 20 and the third semiconductor layer 24 are formed of indium phosphide, the first sacrificial layer 18, the second sacrificial layer 22 and the third sacrificial layer 26 are preferably formed of indium gallium arsenide, but not limited thereto.

Then, as shown in FIGS. 6 to 8 , a patterning process 92 is performed to form a plurality of fin structures (e.g., the first fin structure FS1 shown in FIG. 8 ) on the semiconductor substrate 10. In some embodiments, multiple patterning processes such as a self-aligned double patterning (SADP) process may be used to form the first fin structure FS1, but the present invention is not limited thereto. For example, a hard mask HM may be formed on the stacked structure MS, and a plurality of mandrels 32 may be formed on the hard mask HM. Then, a sidewall 34 is formed on the sidewall of each mandrel 32, and after the sidewall 34 is formed, the mandrel 32 is removed, and the patterning process 92 is performed using the sidewall 34. In some embodiments, the pattern of the sidewall sub-layer 34 may be first transferred to the hard mask HM, and then the hard mask HM may be used as an etching mask to etch the stacked structure MS, the patterned dielectric layer 14A, the patterned barrier layer 12A, and the semiconductor substrate 10 to form the first fin structure FS1. However, the manufacturing method of the first fin structure FS1 of the present embodiment is not limited to the above-mentioned method, and the first fin structure FS1 may be formed by other suitable patterning methods as needed. It is worth noting that when the sidewall sub-layer 34 is used to perform the patterning process 92, the formation position and size of each core line 32 need to be controlled to ensure that the sidewall sub-layer 34 formed on the sidewall of the core line 32 does not overlap with the first semiconductor layer 16 in the opening OP in the third direction D3. In other words, each core line 32 may be only a region outside the opening OP in the third direction D3, and the projection area of each core line 32 in the third direction D3 may be smaller than the projection area of each patterned dielectric layer 14A in the third direction D3. In addition, in some embodiments, the material of the core line 32 may include a dielectric material such as an organic dielectric layer (ODL) or other suitable materials, and the hard mask HM may include a single layer or multiple layers of mask material. For example, the hard mask HM may include a stacked first hard mask layer 28 and a second hard mask layer 30, and the first hard mask layer 28 and the second hard mask layer 30 may be formed of different conductive materials or/and insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, amorphous silicon or polycrystalline silicon, etc., but not limited thereto. In addition, the sidewall 34 may include silicon oxide or other suitable materials with a better etching selectivity between the core line 32 and the hard mask HM.

In some embodiments, the patterning process 92 may include one or more anisotropic etching steps to etch each layer in the stack structure MS, the patterned dielectric layer 14A, the patterned barrier layer 12A, and the semiconductor substrate 10, but the present invention is not limited thereto. Therefore, the stack structure MS, the patterned dielectric layer 14A, the patterned barrier layer 12A, and the semiconductor substrate 10 may be patterned by the patterning process 92 to form a plurality of first fin structures FS1, and the first semiconductor layer 16 in each opening OP may be completely removed by the patterning process 92. Each first fin structure FS1 may include a portion of the second hard mask layer 30, a portion of the first hard mask layer 28, a portion of the third sacrificial layer 26, a portion of the third semiconductor layer 24, a portion of the second sacrificial layer 22, a portion of the second semiconductor layer 20, a portion of the first sacrificial layer 18, a portion of the first semiconductor layer 16, a portion of the dielectric layer 14, a portion of the barrier layer 12, and a portion of the semiconductor substrate 10. In other words, the second hard mask layer 30, the first hard mask layer 28, the third sacrificial layer 26, the third semiconductor layer 24, the second sacrificial layer 22, the second semiconductor layer 20, the first sacrificial layer 18, the first semiconductor layer 16, the dielectric layer 14, the barrier layer 12, and a portion of the semiconductor substrate 10 may be patterned by the process 92. The fins 10F, fin barrier layers 12F, fin dielectric layers 14F, first fin semiconductor layers 16F, first fin sacrificial layers 18F, second fin semiconductor layers 20F, second fin sacrificial layers 22F, third fin semiconductor layers 14F, and fin dielectric layers 14F are formed. The semiconductor layer 24F, a plurality of third fin sacrificial layers 26F, a plurality of first fin hard mask layers 28F and a plurality of second fin hard mask layers 30F, wherein each second fin hard mask layer 30F, each first fin hard mask layer 28F, each third fin sacrificial layer 26F, each third fin semiconductor layer 24F, each first fin hard mask layer 28F, each third fin sacrificial layer 26F, each third fin semiconductor layer 24F, each first fin hard mask layer 30F, each second fin hard mask layer 30 ...30F, each first fin hard mask layer 30F, each third fin sacrificial layer 30F, each third fin semiconductor The two fin sacrificial layers 22F, the second fin semiconductor layers 20F, the first fin sacrificial layers 18F, the first fin semiconductor layers 16F, the fin dielectric layers 14F, the fin barrier layers 12F and the semiconductor fins 10F may be stacked and overlapped in the third direction D3 to form a first fin structure FS1.

As shown in FIGS. 8 to 9, in some embodiments, after the first fin structures FS1 are formed, an isolation structure 36 may be formed between each first fin structure FS1. In some embodiments, the isolation structure 36 may be formed by filling the space between each first fin structure FS1 with an isolation material, and removing the excess isolation material by a chemical mechanical polishing process to expose the second mask layer 30, but the present invention is not limited thereto. In some embodiments, before the isolation structure 36 is formed, the unnecessary first fin structure FS1 may be removed or/and a portion of a specific first fin structure FS1 may be removed, but the present invention is not limited thereto. Then, an etching back process may be performed to remove the second fin hard mask layer 30F and the first fin hard mask layer 28F in each first fin structure FS1 to expose the third fin sacrificial layer 26F. In some embodiments, the isolation structure 36 may also be partially removed in the above-mentioned etching back process, but the present invention is not limited thereto. In addition, after removing the second fin hard mask layer 30F and the first fin hard mask layer 28F, a doping process 93 may be performed as needed. The doping process 93 may include one or more doping steps to implant the desired dopants into the first fin structure FS1 or/and the semiconductor substrate 10, but the present invention is not limited thereto.

Then, as shown in FIGS. 9 to 10 , the isolation structure 36 may be subjected to an etching back process to remove a portion of the relatively upper portion of the isolation structure 36 to expose the third fin sacrificial layer 26F, the third fin semiconductor layer 24F, the second fin sacrificial layer 22F, the second fin semiconductor layer 20F, the first fin sacrificial layer 18F, and the first fin semiconductor layer 16F in each of the first fin structures FS1. Then, an etching process 94 is performed to remove the sacrificial layers (e.g., the first sacrificial layer 18, the second sacrificial layer 22, and the third sacrificial layer 26) in each of the first fin structures FS1. During the etching process 94, the isolation structure 36 may cover the sidewalls of the dielectric layer 14, the sidewalls of the barrier layer 12, and the sidewalls of the semiconductor fin 10F in each of the first fin structures FS1, but the present invention is not limited thereto. After the etching process 94, the remaining fin dielectric layer 14F, the fin barrier layer 12F, and the semiconductor fin 10F may be regarded as the second fin structure FS2, but the present invention is not limited thereto. By designing the material combination of the sacrificial layer and the semiconductor layer in the first fin structure FS1 and/or adjusting the process parameters of the etching process 94 (such as process time, etching rate, etc.), the etching process 94 can be used to completely remove the first sacrificial layer 18, the second sacrificial layer 22 and the third sacrificial layer 26, and the etching process 94 does not produce an etching effect on the semiconductor layer in the first fin structure FS1 or only produces a slight etching effect on the semiconductor layer in the first fin structure FS1. Therefore, the first semiconductor layer 16 in the first fin structure FS1 can be etched by the etching process 94 to become a first semiconductor line 16W, the second semiconductor layer 20 in the first fin structure FS1 can be etched by the etching process 94 to become a second semiconductor line 20W, and the third semiconductor layer 24 in the first fin structure FS1 can be etched by the etching process 94 to become a third semiconductor line 24W. In some embodiments, the etching process 94 may not produce an etching effect on the first semiconductor layer 16, the second semiconductor layer 20, and the third semiconductor layer 24, and the first sacrificial layer 18, the second sacrificial layer 22, and the third sacrificial layer 26 may only be removed by the etching process 94, so that the remaining first fin semiconductor layer 16F is regarded as the first semiconductor line 16W, the remaining second fin semiconductor layer 20F is regarded as the second semiconductor line 20W, and the remaining third fin semiconductor layer 24F is regarded as the third semiconductor line 24W.

In some embodiments, the etching process 94 may include an isotropic etching process (e.g., a wet etching process) to provide a better etching selectivity, but is not limited thereto. For example, when the material of the first semiconductor layer 16, the second semiconductor layer 20, and the third semiconductor layer 24 is gallium nitride and the material of the first sacrificial layer 18, the second sacrificial layer 22, and the third sacrificial layer 26 is aluminum gallium nitride, the etching process 94 may be a wet etching process using sodium hydroxide, potassium hydroxide, or/and other suitable etching solutions. When the materials of the first semiconductor layer 16, the second semiconductor layer 20 and the third semiconductor layer 24 are InP and the materials of the first sacrificial layer 18, the second sacrificial layer 22 and the third sacrificial layer 26 are InGaAs, the etching process 94 may be a wet etching process using hydrochloric acid (HCl) or/and other suitable etching solutions. When the material of the first semiconductor layer 16, the second semiconductor layer 20 and the third semiconductor layer 24 is GaAs and the material of the first sacrificial layer 18, the second sacrificial layer 22 and the third sacrificial layer 26 is AlGaAs, the etching process 94 may be a wet etching process including hydrofluoric acid (HF) or/and other suitable etching solutions.

It is worth noting that, in some embodiments, due to reducing the etching degree of the semiconductor layer by the etching process 94, the first semiconductor line 16W, the second semiconductor line 20W, and the third semiconductor line 24W overlapped in the third direction D3 can be separated from each other, but the first semiconductor line 16W can still directly contact the dielectric layer 14 in the corresponding second fin structure FS2, but the present invention is not limited thereto. Then, as shown in FIG. 12 and FIG. 13, a gate dielectric layer 38 can be formed on the first semiconductor line 16W, the second semiconductor line 20W, and the third semiconductor line 24W. In some embodiments, the gate dielectric layer 38 can be formed by an atomic layer deposition (ALD) process or other suitable film forming processes. The gate dielectric layer 38 may surround each first semiconductor line 16W, each second semiconductor line 20W, and each third semiconductor line 24W, and the lower portion of each first semiconductor line 16W may still be directly connected to the dielectric layer 14. Then, as shown in FIG. 1 , a gate structure GS is formed to cover the gate dielectric layer 38, each first semiconductor line 16W, each second semiconductor line 20W, each third semiconductor line 24W, and the isolation structure 36. In some embodiments, the gate structure GS may only cover a portion of each first semiconductor line 16W, each second semiconductor line 20W, and each third semiconductor line 24W, while a portion of each first semiconductor line 16W, each second semiconductor line 20W, and each third semiconductor line 24W that is not covered by the gate dielectric layer 38 and the gate structure GS may be formed into a source region and a drain region (not shown) through a doping process or other suitable processing methods, thereby forming a transistor structure, which may be regarded as a GAA transistor structure, but is not limited to this. By using the manufacturing method of this embodiment, the first semiconductor layer 16 can be formed by epitaxial growth on the semiconductor substrate exposed by the opening and then formed on the dielectric layer 14, thereby forming a first semiconductor layer 16 with better quality on the dielectric layer 14, thereby achieving the effect of improving the process yield of the semiconductor device 101 and/or enhancing the electrical performance of the semiconductor device 101.

The following will describe different embodiments of the present invention, and for simplicity, the following description will mainly describe the differences between the embodiments, and will not repeat the same parts. In addition, the same components in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

Please refer to Fig. 14, Fig. 15 and Fig. 10. Fig. 14 and Fig. 15 are schematic diagrams showing the method for manufacturing the semiconductor device 102 according to the second embodiment of the present invention, wherein Fig. 15 is a schematic diagram showing the state after Fig. 14, and Fig. 14 can be regarded as a schematic diagram showing the state after Fig. 10. The difference from the first embodiment described above is that, as shown in FIGS. 10 and 14 , in this embodiment, each first semiconductor line 16W can be separated from the dielectric layer 14 by adjusting the etching condition of the etching process 94, controlling the thickness condition of the first semiconductor layer 16, the second semiconductor layer 20 and the third semiconductor layer 24, or/and controlling the width of each first fin structure (for example, controlling the width of each first fin structure FS1 shown in FIG. 8 when it is formed). Therefore, as shown in FIGS. 14 to 15 , after the gate dielectric layer 38 and the gate structure GS are formed, the gate dielectric layer 38 can be located between the first semiconductor line 16W and the dielectric layer 14 in the third direction D3, thereby increasing the surface area of the gate structure GS covering the first semiconductor line 16W, thereby achieving the effect of improving the electrical performance of the semiconductor device 102.

In summary, in the semiconductor device and its manufacturing method of the present invention, an opening can be formed in the dielectric layer covering the semiconductor substrate to expose a portion of the semiconductor substrate, so that the first semiconductor layer can grow from the semiconductor substrate exposed by the opening and be formed on the dielectric layer. In this way, a first semiconductor layer with better quality can be formed on the dielectric layer, thereby achieving the effect of improving the process yield of the semiconductor device or/and enhancing the electrical performance of the semiconductor device. In addition, by setting the barrier layer, the semiconductor substrate can be prevented from being affected by the process of forming the dielectric layer and indirectly affecting the film quality of the subsequent first semiconductor layer formed on the semiconductor substrate, so the electrical performance of the semiconductor device can be further improved. The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: semiconductor substrate 10F: semiconductor fin 12: barrier layer 12A: patterned barrier layer 12F: fin barrier layer 14: dielectric layer 14A: patterned dielectric layer 14F: fin dielectric layer 16: first semiconductor layer 16F: first fin semiconductor layer 16W: first semiconductor line 18: first sacrificial layer 18F: first fin sacrificial layer 20: second semiconductor layer 20F: second fin semiconductor layer 20W: second semiconductor line 22: second sacrificial layer 22F: second fin sacrificial layer 24: Third semiconductor layer 24F: Third fin semiconductor layer 24W: Third semiconductor line 26: Third sacrificial layer 26F: Third fin sacrificial layer 28: First hard mask layer 28F: First fin hard mask layer 30: Second hard mask layer 30F: Second fin hard mask layer 32: Core line 34: Sidewall 36: Isolation structure 38: Gate dielectric layer 40: Work function layer 42: Conductive layer 91: Planarization process 92: Patterning process 93: Doping process 94: Etching process 101: semiconductor device 102: semiconductor device D1: first direction D2: second direction D3: third direction FS1: first fin structure FS2: second fin structure GS: gate structure HM: hard mask MS: stacking structure OP: opening

Figure 1 is a schematic diagram of a semiconductor device according to the first embodiment of the present invention. Figures 2 to 13 are schematic diagrams of the method for manufacturing a semiconductor device of the first embodiment of the present invention, wherein Figure 3 is a schematic diagram of the state after Figure 2; Figure 4 is a schematic diagram of the state after Figure 3; Figure 5 is a schematic diagram of the state after Figure 4; Figure 6 is a schematic diagram of the state after Figure 5; Figure 7 is a schematic diagram of the state after Figure 6; Figure 8 is a schematic diagram of the state after Figure 7; Figure 9 is a schematic diagram of the state after Figure 8; Figure 10 is a schematic diagram of the state after Figure 9; Figure 11 is a schematic diagram of the state after Figure 10; Figure 12 is a schematic diagram of the state after Figure 11; FIG. 13 is a schematic diagram showing a cross-sectional view of FIG. 12 in another direction. FIG. 14 and FIG. 15 are schematic diagrams showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention, wherein FIG. 15 is a schematic diagram showing a state after FIG. 14.

10: semiconductor substrate 10F: semiconductor fin 12: barrier layer 12F: fin barrier layer 14: dielectric layer 14F: fin dielectric layer 16: first semiconductor layer 16W: first semiconductor line 20: second semiconductor layer 20W: second semiconductor line 24: third semiconductor layer 24W: third semiconductor line 36: isolation structure 38: gate dielectric layer 40: work function layer 42: conductive layer 101: semiconductor device D1: first direction D2: second direction D3: third direction FS2: second fin structure GS: gate structure

Claims (4)

A semiconductor device comprises: a semiconductor substrate; a fin structure disposed on the semiconductor substrate, wherein the fin structure comprises: a semiconductor fin; a dielectric layer disposed on the semiconductor fin; and a barrier layer disposed between the dielectric layer and the semiconductor fin in a thickness direction of the semiconductor substrate, wherein the barrier layer comprises a III-V compound semiconductor layer; a first semiconductor line disposed on the fin structure; and A second semiconductor line is disposed on the first semiconductor line, wherein the first semiconductor line is disposed between the second semiconductor line and the fin structure in the thickness direction of the semiconductor substrate, the first semiconductor line and the second semiconductor line are separated from each other, and the first semiconductor line directly contacts the dielectric layer, wherein the material of the barrier layer includes aluminum gallium nitride, aluminum gallium arsenide or indium gallium arsenide, the material composition of the semiconductor substrate is different from the material composition of the barrier layer, and the material composition of the barrier layer is different from the material composition of the dielectric layer and the material composition of the semiconductor fin. A semiconductor device as described in claim 1, wherein an extension direction of the first semiconductor line, an extension direction of the second semiconductor line, and an extension direction of the fin structure are parallel to each other and orthogonal to the thickness direction of the semiconductor substrate. A semiconductor device as described in claim 1, wherein the semiconductor fin is directly connected to the semiconductor substrate, and the material composition of the first semiconductor line is the same as the material composition of the semiconductor fin and the material composition of the semiconductor substrate. The semiconductor device as described in claim 1 further includes: a gate dielectric layer disposed on the first semiconductor line and the second semiconductor line; and a gate structure disposed on the gate dielectric layer.

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