TWI870235B - Electrostatic discharge protection device - Google Patents

Abstract

The present disclosure provides electrostatic discharge protection device, which includes an electrostatic discharge protection component and a trigger circuit. After the trigger circuit detects electrostatic discharge, the trigger circuit applies a voltage to the polycrystalline silicon layer on the shallow trench isolation area of ​​the electrostatic discharge protection component, thereby reducing a trigger voltage of the electrostatic discharge protection component.

Description

Electrostatic discharge protection device

The present invention relates to a protection device, and in particular to an electrostatic discharge protection device.

Generally speaking, the trigger voltage of an electrostatic discharge (ESD) protection component must be lower than the circuit breakdown voltage. In practice, an ESD protection component based on a PNP transistor is a universal solution for high voltage protection. However, the trigger voltage of an ESD protection component based on a PNP transistor can easily exceed the circuit breakdown voltage.

It can be seen that the above-mentioned existing electrostatic discharge protection still has inconveniences and defects, and needs to be further improved. In order to solve the above problems, relevant fields have spared no effort to seek solutions, but for a long time, no applicable method has been developed. Therefore, how to better meet the design specifications of electrostatic discharge protection is one of the current important research and development topics, and has also become a goal that the current relevant fields urgently need to improve.

The present invention proposes an innovative electrostatic discharge protection device to improve the problems of the prior art.

In some embodiments of the present invention, the electrostatic discharge protection device provided by the present invention includes an electrostatic discharge protection element and a trigger circuit. The electrostatic discharge protection element includes a first high voltage N-type well, a first N-type well, a first P-type heavily doped region, a first high voltage P-type well, a first P-type well, a second P-type heavily doped region, a first shallow trench isolation region, a first polysilicon layer, a second high voltage N-type well, a second N-type well, a first N-type heavily doped region, a second shallow trench isolation region, a second high voltage P-type well, a second P-type well, a third P-type heavily doped region, a third shallow trench isolation region, a second polysilicon layer, a third high voltage N-type well, a third N-type well, a second N-type heavily doped region, and a fourth shallow trench isolation region. The first N-type well is located in the first high voltage N-type well, and the first P-type heavily doped region is located on the first N-type well. One side of the first high voltage P-type well directly contacts one side of the first high voltage N-type well. The first P-type well is located in the first high voltage P-type well, and the second P-type heavily doped region is located on the first P-type well. The first shallow trench isolation region is located between the second P-type heavily doped region and the first P-type heavily doped region, and the first polysilicon layer is located on the first shallow trench isolation region, and the first polysilicon layer directly contacts the first shallow trench isolation region. One side of the second high voltage N-type well directly contacts the other side of the first high voltage P-type well, the second N-type well is located in the second high voltage N-type well, the first N-type heavily doped region is located on the second N-type well, and the second shallow trench isolation region is located between the first N-type heavily doped region and the second P-type heavily doped region. One side of the second high voltage P-type well directly contacts the other side of the first high voltage N-type well, the second P-type well is located in the second high voltage P-type well, and the third P-type heavily doped region is located on the second P-type well. The third shallow trench isolation region is located between the third P-type heavily doped region and the first P-type heavily doped region, the second polysilicon layer is located on the third shallow trench isolation region, and the second polysilicon layer directly contacts the third shallow trench isolation region. One side of the third high voltage N-type well directly contacts the other side of the second high voltage P-type well, the third N-type well is located in the third high voltage N-type well, the second N-type heavily doped region is located on the third N-type well, and the fourth shallow trench isolation region is located between the second N-type heavily doped region and the third P-type heavily doped region. The trigger circuit is electrically connected to a first voltage terminal, a second voltage terminal and a trigger terminal. The first voltage terminal is electrically connected to a first N-type heavily doped region, a second P-type heavily doped region, a third P-type heavily doped region and a second N-type heavily doped region. The second voltage terminal is electrically connected to the first P-type heavily doped region. The trigger terminal is electrically connected to a first polysilicon layer and a second polysilicon layer. After the trigger circuit detects electrostatic discharge through the first voltage terminal, the trigger circuit applies a voltage to the first polysilicon layer and the second polysilicon layer through the trigger terminal, thereby reducing a trigger voltage of the electrostatic discharge protection element.

In some embodiments of the present invention, the trigger circuit includes a resistor and capacitor unit and a semiconductor switch unit. One end of the resistor and capacitor unit is electrically connected to the first N-type heavily doped region, the second P-type heavily doped region, the third P-type heavily doped region and the second N-type heavily doped region through a first voltage terminal, and the other end of the resistor and capacitor unit is electrically connected to the first P-type heavily doped region through a second voltage terminal. Two ends of the semiconductor switch unit are electrically connected to the first voltage terminal and the trigger terminal, respectively, and the control terminal of the semiconductor switch unit is electrically connected to the resistor and capacitor unit.

In some embodiments of the present invention, the width of the first polysilicon layer is smaller than the width of the first shallow trench isolation region, or the width of the second polysilicon layer is smaller than the width of the third shallow trench isolation region.

In some embodiments of the present invention, a ratio of a width of the first polysilicon layer divided by a width of the first shallow trench isolation region is between 70% and 90%, or a ratio of a width of the second polysilicon layer divided by a width of the third shallow trench isolation region is between 70% and 90%.

In some embodiments of the present invention, the sum of the shortest distance from the first P-type well to one side of the first high-voltage P-type well plus the shortest distance from the first N-type well to one side of the first high-voltage N-type well is less than the width of the first polysilicon layer, or the sum of the shortest distance from the second P-type well to one side of the second high-voltage P-type well plus the shortest distance from the first N-type well to the other side of the first high-voltage N-type well is less than the width of the second polysilicon layer.

In some embodiments of the present invention, the electrostatic discharge protection device provided by the present invention includes an electrostatic discharge protection element and a trigger circuit. The electrostatic discharge protection element includes a first high voltage N-type well, a second high voltage N-type well, a third high voltage N-type well, a first high voltage P-type well, a second high voltage P-type well, a first N-type well, a second N-type well, a third N-type well, a first P-type well, a second P-type well, a first P-type heavily doped region, a second P-type heavily doped region, a third P-type heavily doped region, a first N-type heavily doped region, a second N-type heavily doped region, a first shallow trench isolation region, a second shallow trench isolation region, a third shallow trench isolation region, a fourth shallow trench isolation region, a first polysilicon layer, and a second polysilicon layer. The opposite sides of the first high voltage P-type well directly contact one side of the first high voltage N-type well and one side of the second high voltage N-type well, respectively, and the opposite sides of the second high voltage P-type well directly contact the other side of the first high voltage N-type well and one side of the third high voltage N-type well, respectively. The first N-type well, the second N-type well, and the third N-type well are located in the first high voltage N-type well, the second high voltage N-type well, and the third high voltage N-type well, respectively. The first P-type well and the second P-type well are located in the first high voltage P-type well and the second high voltage P-type well, respectively. The first P-type heavily doped region, the second P-type heavily doped region, and the third P-type heavily doped region are located on the first N-type well, the first P-type well, and the second P-type well, respectively. The first N-type re-doped region and the second N-type re-doped region are located on the second N-type well and the third N-type well, respectively. The first shallow trench isolation region is located between the second P-type re-doped region and the first P-type re-doped region, the second shallow trench isolation region is located between the first N-type re-doped region and the second P-type re-doped region, the third shallow trench isolation region is located between the third P-type re-doped region and the first P-type re-doped region, and the fourth shallow trench isolation region is located between the second N-type re-doped region and the third P-type re-doped region. The first polysilicon layer is located on the first shallow trench isolation region, and the first polysilicon layer directly contacts the first shallow trench isolation region. The second polysilicon layer is located on the third shallow trench isolation region, and the second polysilicon layer directly contacts the third shallow trench isolation region. The trigger circuit is electrically connected to the electrostatic discharge protection element through the first voltage terminal, the second voltage terminal and the trigger terminal, and the trigger circuit includes a resistor, a capacitor and a transistor. One end of the resistor is electrically connected to the first N-type heavily doped region, the second P-type heavily doped region, the third P-type heavily doped region and the second N-type heavily doped region through the first voltage terminal. One end of the capacitor is electrically connected to the other end of the resistor, and the other end of the capacitor is electrically connected to the first P-type heavily doped region through the second voltage end. Two ends of the transistor are electrically connected to the first voltage end and the trigger end respectively, the trigger end is electrically connected to the first polysilicon layer and the second polysilicon layer, and the control end of the transistor is electrically connected to the other end of the resistor and one end of the capacitor. After the trigger circuit detects electrostatic discharge through the first voltage end, the trigger circuit applies voltage to the first polysilicon layer and the second polysilicon layer through the trigger end to reduce the trigger voltage of the electrostatic discharge protection element.

In some embodiments of the present invention, a ratio of a width of the first polysilicon layer divided by a width of the first shallow trench isolation region is between 70% and 90%, and a ratio of a width of the second polysilicon layer divided by a width of the third shallow trench isolation region is between 70% and 90%.

In some embodiments of the present invention, the sum of the shortest distance from the first P-type well to one side of the first high-voltage P-type well plus the shortest distance from the first N-type well to one side of the first high-voltage N-type well is less than the width of the first polysilicon layer, and the sum of the shortest distance from the second P-type well to one side of the second high-voltage P-type well plus the shortest distance from the first N-type well to the other side of the first high-voltage N-type well is less than the width of the second polysilicon layer.

In some embodiments of the present invention, the transistor is a P-type transistor, the gate of the P-type transistor serves as the control terminal, the source of the P-type transistor is electrically connected to the first voltage terminal, and the drain of the P-type transistor is electrically connected to the trigger terminal.

In some embodiments of the present invention, the width of the first polysilicon layer is smaller than the width of the first shallow trench isolation region, and the width of the second polysilicon layer is smaller than the width of the third shallow trench isolation region.

In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. After the trigger circuit detects electrostatic discharge, the trigger circuit applies voltage to the polysilicon layer on the shallow trench isolation area of the electrostatic discharge protection element to change the electric field, thereby reducing the triggering voltage of the electrostatic discharge protection element, which means that during the electrostatic discharge stress period, the electrostatic discharge protection device of the present invention can protect the internal circuit more safely.

The following will describe the above description in detail with an implementation method and provide a further explanation of the technical solution of the present invention.

In order to make the description of the present invention more detailed and complete, reference may be made to the attached drawings and various embodiments described below, in which the same numbers represent the same or similar elements. On the other hand, well-known elements and steps are not described in the embodiments to avoid unnecessary limitations on the present invention.

Please refer to FIG. 1. The technical aspect of the present invention is an electrostatic discharge protection device 100, which can be applied to various electronic devices or widely used in related technical links. The electrostatic discharge protection device 100 of the technical aspect can achieve considerable technical progress and has a wide range of industrial utilization value. The specific implementation of the electrostatic discharge protection device 100 will be described below in conjunction with FIG. 1.

It should be understood that various embodiments of the electrostatic discharge protection device 100 are described in conjunction with FIG. 1. In the following description, for the convenience of explanation, many specific details are further set to provide a comprehensive description of one or more embodiments. However, the present technology can be implemented without these specific details. In other examples, in order to effectively describe these embodiments, known structures and devices are shown in block diagram form. The term "for example" used here means "as an example, instance or illustration". Any embodiment described here as "for example" need not be interpreted as better or superior to other embodiments.

FIG. 1 is a circuit diagram of an ESD protection device 100 according to an embodiment of the present invention. As shown in FIG. 1 , the ESD protection device 100 includes an ESD protection element 101 and a trigger circuit 102. Structurally, the trigger circuit 102 is electrically connected to the ESD protection element 101 through a first voltage terminal 251, a second voltage terminal 252, and a trigger terminal 253. In practice, for example, the first voltage terminal 251 can be a high voltage terminal, and the second voltage terminal 252 can be a low voltage terminal, and the voltage level of the first voltage terminal 251 is higher than the voltage level of the second voltage terminal 252.

In a normal operation mode, the trigger end 253 is floating, so that the first polysilicon layer 181 on the first shallow trench isolation region 171 and the second polysilicon layer 182 on the third shallow trench isolation region 173 remain in a floating state, and the ESD protection device 101 can obtain a higher breakdown voltage and triggering voltage to avoid false triggering of the ESD protection device 101. In practice, for example, the trigger terminal 253 is floating, and when the current of the ESD protection device 101 is about 2.5A, the breakdown voltage of the ESD protection device 101 is about 103V, and the trigger voltage of the ESD protection device 101 is about 119.6V.

In the ESD mode, after the trigger circuit 102 detects ESD through the first voltage terminal 251, the trigger circuit 102 applies a voltage (e.g., a high voltage) to the first polysilicon layer 181 and the second polysilicon layer 182 through the trigger terminal 253, thereby reducing the breakdown voltage and the triggering voltage of the ESD protection element 101, making the ESD protection element 101 easier to trigger. This means that during ESD stress, the ESD protection device 100 of the present invention can protect the internal circuit more safely. In practice, for example, when a high voltage is applied to the trigger end 253, when the current of the ESD protection device 101 is about 2.5A, the breakdown voltage of the ESD protection device 101 is about 63V, and the triggering voltage of the ESD protection device 101 is about 65.1V.

The terms "about", "approximately" or "substantially" used herein are used to modify any quantity that may vary slightly, but such slight variations do not change its essence. If there is no special explanation in the implementation method, the error range of the value modified by "about", "approximately" or "substantially" is generally allowed within 20%, preferably within 10%, and more preferably within 5%.

Regarding the specific structure of the ESD protection element 101, in FIG. 1, the ESD protection element 101 includes a first high-voltage N-well (HVNW) 111, a second high-voltage N-well 112, a third high-voltage N-well 113, a first high-voltage P-well (HVNW), and a second high-voltage P-well 114. PVNW) 121, a second high voltage P-type well 122, a first N-type well 131, a second N-type well 132, a third N-type well 133, a first P-type well 141, a second P-type well 142, a first P-type heavily doped region 151, a second P-type heavily doped region 152, a third P-type heavily doped region 153, a first N-type heavily doped region 161, a second N-type heavily doped region 162, a first shallow trench isolation region 171, a second shallow trench isolation region 172, a third shallow trench isolation region 173, a fourth shallow trench isolation region 174, a first polycrystalline silicon layer 181, and a second polycrystalline silicon layer 182.

In terms of structure, the opposite sides of the first high voltage P-type well 121 directly contact one side of the first high voltage N-type well 111 and one side of the second high voltage N-type well 112, respectively, and the opposite sides of the second high voltage P-type well 122 directly contact the other side of the first high voltage N-type well 111 and one side of the third high voltage N-type well 113, respectively. The first N-type well 131, the second N-type well 132 and the third N-type well 133 are respectively located in the first high voltage N-type well 111, the second high voltage N-type well 112 and the third high voltage N-type well 113. The first P-type well 141 and the second P-type well 142 are respectively located in the first high voltage P-type well 121 and the second high voltage P-type well 122. The first P-type heavily doped region 151, the second P-type heavily doped region 152 and the third P-type heavily doped region 153 are respectively located on the first N-type well 131, the first P-type well 141 and the second P-type well 142. The first N-type heavily doped region 161 and the second N-type heavily doped region 162 are respectively located on the second N-type well 132 and the third N-type well 133. The first shallow trench isolation region 171 is located between the second P-type heavily doped region 152 and the first P-type heavily doped region 151, the second shallow trench isolation region 172 is located between the first N-type heavily doped region 161 and the second P-type heavily doped region 152, the third shallow trench isolation region 173 is located between the third P-type heavily doped region 153 and the first P-type heavily doped region 151, and the fourth shallow trench isolation region 174 is located between the second N-type heavily doped region 162 and the third P-type heavily doped region 153. The first polysilicon layer 181 is located on the first shallow trench isolation region 171 , and the first polysilicon layer 181 directly contacts the first shallow trench isolation region 171 . The second polysilicon layer 182 is located on the third shallow trench isolation region 173 , and the second polysilicon layer 182 directly contacts the third shallow trench isolation region 173 .

In other words, the first N-type well 131 is located in the first high voltage N-type well 111, and the first P-type heavily doped region 151 is located on the first N-type well 131. One side of the first high voltage P-type well 121 directly contacts one side of the first high voltage N-type well 111, the first P-type well 141 is located in the first high voltage P-type well 121, and the second P-type heavily doped region 152 is located on the first P-type well 141. The first shallow trench isolation region 171 is located between the second P-type heavily doped region 152 and the first P-type heavily doped region 151 . The first polysilicon layer 181 is located on the first shallow trench isolation region 171 . The first polysilicon layer 181 directly contacts the first shallow trench isolation region 171 . One side of the second high voltage N-type well 112 directly contacts the other side of the first high voltage P-type well 121, the second N-type well 132 is located in the second high voltage N-type well 112, the first N-type heavily doped region 161 is located on the second N-type well 132, and the second shallow trench isolation region 172 is located between the first N-type heavily doped region 161 and the second P-type heavily doped region 152. One side of the second high voltage P-type well 122 directly contacts the other side of the first high voltage N-type well 111, the second P-type well 142 is located in the second high voltage P-type well 122, and the third P-type heavily doped region 153 is located on the second P-type well 142. The third shallow trench isolation region 173 is located between the third P-type heavily doped region 153 and the first P-type heavily doped region 151 . The second polysilicon layer 182 is located on the third shallow trench isolation region 173 . The second polysilicon layer 182 directly contacts the third shallow trench isolation region 173 . One side of the third high voltage N-type well 113 directly contacts the other side of the second high voltage P-type well 122. The third N-type well 133 is located in the third high voltage N-type well 113. The second N-type heavily doped region 162 is located on the third N-type well 133. The fourth shallow trench isolation region 174 is located between the second N-type heavily doped region 162 and the third P-type heavily doped region 153.

In practice, for example, the electrostatic discharge protection element 101 can be an element extended based on a PNP bipolar transistor, the first P-type heavily doped region 151 can be used as an emitter, the second P-type heavily doped region 152 can be used as a collector, the third P-type heavily doped region 153 can be used as a collector, the first N-type heavily doped region 161 can be used as a base, and the second N-type heavily doped region 162 can be used as a base, but the present invention is not limited thereto.

In addition, the electrostatic discharge protection element 101 may selectively include a third high voltage P-type well 123, a third P-type well 143, a fourth P-type heavily doped region 154, and a fifth shallow trench isolation region 175. In terms of structure, one side of the third high voltage P-type well 123 directly contacts the other side of the second high voltage N-type well 112, the third P-type well 143 is located in the third high voltage P-type well 123, the fourth P-type heavily doped region 154 is located on the third P-type well 143, and the fifth shallow trench isolation region 175 is located between the fourth P-type heavily doped region 154 and the first N-type heavily doped region 161. In practice, for example, the fourth P-type heavily doped region 154 may be electrically connected to the P-type substrate, but the present invention is not limited thereto.

In addition, the electrostatic discharge protection device 101 may selectively include a fourth high voltage P-type well 124, a fourth P-type well 144, a fifth P-type heavily doped region 155, and a sixth shallow trench isolation region 176. In terms of structure, one side of the fourth high voltage P-type well 124 directly contacts the other side of the third high voltage N-type well 113, the fourth P-type well 144 is located in the fourth high voltage P-type well 124, the fifth P-type heavily doped region 155 is located on the fourth P-type well 144, and the sixth shallow trench isolation region 176 is located between the fifth P-type heavily doped region 155 and the second N-type heavily doped region 162.

In FIG. 1 , the first high voltage N-type well 111, the second high voltage N-type well 112, the third high voltage N-type well 113, the first high voltage P-type well 121 and the second high voltage P-type well 122 are located on the N-type buried layer 192, and the N-type buried layer 192 is located on the semiconductor substrate 191 (e.g., wafer). The third high voltage P-type well 123 and the fourth high voltage P-type well 124 are located on the semiconductor substrate 191.

On the other hand, regarding the connection relationship between the trigger circuit 102 and the ESD protection device 101, in FIG. 1 , the trigger circuit 102 electrically connects the first voltage terminal 251, the second voltage terminal 252, and the trigger terminal 253. Structurally, the first voltage terminal 251 is electrically connected to the first N-type heavily doped region 161, the second P-type heavily doped region 152, the third P-type heavily doped region 153 and the second N-type heavily doped region 162; the second voltage terminal 252 is electrically connected to the first P-type heavily doped region 151; the second voltage terminal 252 can also be selectively electrically connected to the fourth P-type heavily doped region 154; the trigger terminal 253 is electrically connected to the first polysilicon layer 181 and the second polysilicon layer 182.

During use, after the trigger circuit 102 detects electrostatic discharge through the first voltage terminal 251, the trigger circuit 102 applies a voltage (e.g., a high voltage) to the first polysilicon layer 181 and the second polysilicon layer 182 through the trigger terminal 253 to reduce the triggering voltage of the electrostatic discharge protection element 101. This means that during electrostatic discharge stress, the electrostatic discharge protection device 100 of the present invention can protect the internal circuit more safely.

In some embodiments of the present invention, the width A1 of the first polysilicon layer 181 is smaller than the width B1 of the first shallow trench isolation region 171, so as to facilitate the fabrication of the first polysilicon layer 181. Alternatively or further, in some embodiments of the present invention, the width A2 of the second polysilicon layer 182 is smaller than the width B2 of the third shallow trench isolation region 173, so as to facilitate the fabrication of the second polysilicon layer 182.

The areas covered by the first polysilicon layer 181 and the second polysilicon layer 182 will affect the electric field distribution thereunder, and therefore require a sufficient proportion to exert their effectiveness. In some embodiments of the present invention, the ratio of the width A1 of the first polysilicon layer 181 divided by the width B1 of the first shallow trench isolation region 171 is between about 70% and about 90%, so as to enhance the effectiveness of the electric field distribution formed when the first polysilicon layer 181 is subjected to a voltage. Alternatively or additionally, in some embodiments of the present invention, a ratio of a width A2 of the second polysilicon layer 182 divided by a width B2 of the third shallow trench isolation region 173 is between about 70% and about 90% to enhance the efficiency of the electric field distribution formed when the second polysilicon layer 182 is subjected to a voltage.

In some embodiments of the present invention, the sum of the shortest distance E1 between the first P-type well 141 and one side of the first high voltage P-type well 121 plus the shortest distance F1 between the first N-type well 131 and one side of the first high voltage N-type well 111 is smaller than the width A1 of the first polysilicon layer 181, so as to enhance the efficiency of electric field distribution. Alternatively or further, in some embodiments of the present invention, the sum of the shortest distance E2 between the second P-type well 142 and one side of the second high voltage P-type well 122 plus the shortest distance F2 between the first N-type well 131 and the other side of the first high voltage N-type well 111 is smaller than the width A2 of the second polysilicon layer 182, so as to enhance the efficiency of electric field distribution.

FIG. 2 is a schematic diagram of an ESD protection device 200 according to some embodiments of the present invention. The ESD protection device 101 of FIG. 2 is substantially the same as the ESD protection device 101 of FIG. 1 , and will not be described in detail herein.

In FIG. 2 , the trigger circuit 202 is electrically connected to the ESD protection device 101 through the first voltage terminal 251, the second voltage terminal 252 and the trigger terminal 253. In some embodiments of the present invention, the trigger circuit 202 may include a resistor and capacitor unit 210 and a semiconductor switch unit 220. In terms of structure, one end of the resistor and capacitor unit 210 is electrically connected to the first N-type heavily doped region 161, the second P-type heavily doped region 152, the third P-type heavily doped region 153 and the second N-type heavily doped region 162 through the first voltage terminal 251, and the other end of the resistor and capacitor unit 210 is electrically connected to the first P-type heavily doped region 151 through the second voltage terminal 252. The two ends 221 and 223 of the semiconductor switch unit 220 are electrically connected to the first voltage terminal 251 and the trigger terminal 253 respectively, and the control terminal 222 of the semiconductor switch unit 220 is electrically connected to the resistor and capacitor unit 210.

In FIG. 2 , the resistor/capacitor unit 210 may include a resistor R and a capacitor C, and the semiconductor switch unit 220 may include a transistor P1. In some embodiments of the present invention, the trigger circuit 202 may include a resistor R, a capacitor C, and a transistor P1. Structurally, one end of the resistor R is electrically connected to the first N-type heavily doped region 161, the second P-type heavily doped region 152, the third P-type heavily doped region 153, and the second N-type heavily doped region 162 through the first voltage terminal 251. One end of the capacitor C is electrically connected to the other end of the resistor R, and the other end of the capacitor C is electrically connected to the first P-type heavily doped region 151 through the second voltage terminal 253. The two ends of the transistor P1 are electrically connected to the first voltage end 251 and the trigger end 253, respectively. The trigger end 253 is electrically connected to the first polysilicon layer 181 and the second polysilicon layer 182. The control end 222 of the transistor P1 is electrically connected to the other end of the resistor R and the one end of the capacitor C. During operation, after the trigger circuit 202 detects electrostatic discharge through the first voltage end 251, the trigger circuit 202 applies voltage to the first polysilicon layer 181 and the second polysilicon layer 182 through the trigger end 253, thereby reducing the trigger voltage of the electrostatic discharge protection element 101.

In some embodiments of the present invention, the transistor P1 is a P-type transistor. In terms of structure, the gate of the P-type transistor serves as the control terminal 222, the source of the P-type transistor is electrically connected to the first voltage terminal 251, and the drain of the P-type transistor is electrically connected to the trigger terminal 253.

In practice, for example, the first voltage terminal 251 can be a high voltage terminal, and the second voltage terminal 252 can be a low voltage terminal. In a normal operation mode, since the first voltage terminal 251 is at a high voltage level, the transistor P1 is turned off, so that the trigger terminal 253 is floating, the first polysilicon layer 181 on the first shallow trench isolation region 171 and the second polysilicon layer 182 on the third shallow trench isolation region 173 remain in a floating state, and the ESD protection device 101 can obtain a higher breakdown voltage and trigger voltage to prevent the ESD protection device 101 from being accidentally triggered.

Next, in the electrostatic discharge mode, after the trigger circuit 102 receives the electrostatic discharge through the first voltage terminal 251, the resistor and capacitor unit 210 turns on the transistor P1, and the trigger terminal 253 is electrically connected to the high voltage level of the first voltage terminal 251, thereby the first polysilicon layer is electrically connected to the first polysilicon layer through the trigger terminal 253. 181 and the second polysilicon layer 182 apply a voltage (e.g., a high voltage) to reduce the breakdown voltage and the triggering voltage of the ESD protection element 101, making the ESD protection element 101 easier to trigger. This means that during the ESD stress period, the ESD protection device 200 of the present invention can protect the internal circuit more safely.

In other embodiments, the present invention may also use trigger circuits with other structures to replace the trigger circuit 202. Those skilled in the art may flexibly select the trigger circuit according to actual needs.

In order to further explain the characteristics of the above-mentioned ESD protection device 101, please refer to Figures 1 to 3 at the same time. Figure 3 is a current-voltage relationship diagram of the ESD protection device 101 according to some embodiments of the present invention. In practice, for example, the electrical characteristics of the ESD protection device 101 can be measured and verified through a transmission line pulse (TLP) generator to obtain the current-voltage relationship diagram of the ESD protection device 101.

When the trigger terminal 253 is floating, the measurement curve 310 of the ESD protection device 101 reflects a higher trigger voltage to avoid false triggering. When the trigger terminal 253 is connected to a voltage (eg, a high voltage), the measurement curve 320 of the ESD protection device 101 reflects a reduced trigger voltage.

In practice, for example, the electrostatic discharge protection devices 100 and 200 of the present invention can be manufactured by any standard process and/or high voltage (HV) process. The present invention can also be applied to EPI process. The present invention can also be applied to single-polycrystalline or double-polycrystalline process.

In practice, for example, the N-type heavily doped (N+) and N-type well (NW) of a transistor can be replaced by any N-type implant, and the P-type heavily doped (P+) and P-type well (PW) of a transistor can be replaced by any P-type implant.

In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. After the triggering circuit 102, 202 detects electrostatic discharge, the triggering circuit 102, 202 applies voltage to the first and second polysilicon layers 181, 182 on the first and third shallow trench isolation regions 171, 173 of the electrostatic discharge protection element 101 to change the electric field, thereby reducing the triggering voltage of the electrostatic discharge protection element 101, which means that during the electrostatic discharge stress period, the electrostatic discharge protection device 100, 200 of the present invention can protect the internal circuit more safely.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the attached patent application.

In order to make the above and other purposes, features, advantages and embodiments of the present invention more clearly understandable, the attached symbols are described as follows 100, 200: ESD protection device 101: ESD protection element 102, 202: Trigger circuit 111: First high voltage N-type well 112: Second high voltage N-type well 113: Third high voltage N-type well 121: First high voltage P-type well 122: Second high voltage P-type well 123: Third high voltage P-type well 124: Fourth high voltage P-type well 131: First N-type well 132: Second N-type well 133: Third N-type well 141: First P-type well 142: Second P-type well 143: Third P-type well 144: Fourth P-type well 151: First P-type heavy doping region 152: Second P-type heavy doping region 153: Third P-type heavy doping region 154: Fourth P-type heavy doping region 155: Fifth P-type heavy doping region 161: First N-type heavy doping region 162: Second N-type heavy doping region 171: First shallow trench isolation region 172: Second shallow trench isolation region 173: Third shallow trench isolation region 174: Fourth shallow trench isolation region 175: Fifth shallow trench isolation region 176: Sixth shallow trench isolation region 181: First polysilicon layer 182: Second polysilicon layer 191: Semiconductor substrate 192: N-type buried layer 210: Resistor and capacitor unit 220: Semiconductor switch unit 221: Terminal 222: Control terminal 223: Terminal 251: First voltage terminal 252: Second voltage terminal 253: Trigger terminal 310, 320: Measurement curves A1, A2, B1, B2: Width C: Capacitor E1, F1, E2, F2: Shortest distance P1: Transistor R: Resistor

In order to make the above and other purposes, features, advantages and embodiments of the present invention more clearly understandable, the attached drawings are described as follows: FIG. 1 is a structural diagram of an electrostatic discharge protection device according to some embodiments of the present invention; FIG. 2 is a structural diagram of an electrostatic discharge protection device according to some embodiments of the present invention; and FIG. 3 is a current-voltage relationship diagram of an electrostatic discharge protection element according to some embodiments of the present invention.

100: Electrostatic discharge protection device

101: Electrostatic discharge protection element

102: Trigger circuit

111: The first high voltage N-type well

112: The second highest voltage N-type well

113: The third highest voltage N-type well

121: The first high voltage P-type well

122: The second highest voltage P-type well

123: The third highest voltage P-type well

124: The fourth highest voltage P-type well

131: The first N-type well

132: The second N-type well

133: The third N-type well

141: The first P-type well

142: The second P-type well

143: The third P-type well

144: The fourth P-type well

151: The first P-type heavily doped region

152: The second P-type heavily doped region

153: The third P-type heavily doped region

154: The fourth P-type heavily doped region

155: Fifth P-type heavily doped region

161: The first N-type heavily doped region

162: The second N-type heavily doped region

171: The first shallow trench isolation area

172: Second shallow trench isolation area

173: The third shallow trench isolation area

174: Fourth shallow trench isolation area

175: Fifth shallow trench isolation area

176: The sixth shallow trench isolation area

181: First polysilicon layer

182: Second polysilicon layer

191:Semiconductor substrate

192: N-type buried layer

251: First voltage terminal

252: Second voltage terminal

253:Trigger

A1, A2, B1, B2: Width

E1, F1, E2, F2: shortest distance

Claims (10)

An electrostatic discharge protection device comprises: An electrostatic discharge protection element comprises: A first high voltage N-type well; A first N-type well located in the first high voltage N-type well; A first P-type heavily doped region located on the first N-type well; A first high voltage P-type well, one side of the first high voltage P-type well directly contacts one side of the first high voltage N-type well; A first P-type well located in the first high voltage P-type well; A second P-type heavily doped region located on the first P-type well; A first shallow trench isolation region located between the second P-type heavily doped region and the first P-type heavily doped region; A first polysilicon layer, located on the first shallow trench isolation region, the first polysilicon layer directly contacts the first shallow trench isolation region; A second high voltage N-type well, one side of the second high voltage N-type well directly contacts the other side of the first high voltage P-type well; A second N-type well, located in the second high voltage N-type well; A first N-type heavily doped region, located on the second N-type well; A second shallow trench isolation region, located between the first N-type heavily doped region and the second P-type heavily doped region; A second high voltage P-type well, one side of which directly contacts the other side of the first high voltage N-type well; A second P-type well, located in the second high voltage P-type well; A third P-type heavily doped region, located on the second P-type well; A third shallow trench isolation region, located between the third P-type heavily doped region and the first P-type heavily doped region; A second polysilicon layer, located on the third shallow trench isolation region, the second polysilicon layer directly contacts the third shallow trench isolation region; A third high voltage N-type well, one side of which directly contacts the other side of the second high voltage P-type well; A third N-type well, located in the third high voltage N-type well; A second N-type heavily doped region, located on the third N-type well; and A fourth shallow trench isolation region, located between the second N-type heavily doped region and the third P-type heavily doped region; and a trigger circuit electrically connected to a first voltage terminal, a second voltage terminal and a trigger terminal, wherein the first voltage terminal is electrically connected to the first N-type heavily doped region, the second P-type heavily doped region, the third P-type heavily doped region and the second N-type heavily doped region, and the second voltage terminal is electrically connected to the first P-type heavily doped region. The trigger terminal is electrically connected to the first polysilicon layer and the second polysilicon layer. After the trigger circuit detects electrostatic discharge through the first voltage terminal, the trigger circuit applies voltage to the first polysilicon layer and the second polysilicon layer through the trigger terminal to reduce the trigger voltage of the electrostatic discharge protection element. The electrostatic discharge protection device as described in claim 1, wherein the trigger circuit comprises: a resistor and capacitor unit, one end of which is electrically connected to the first N-type heavily doped region, the second P-type heavily doped region, the third P-type heavily doped region and the second N-type heavily doped region through the first voltage terminal, and the other end of which is electrically connected to the first P-type heavily doped region through the second voltage terminal; and a semiconductor switch unit, two ends of which are electrically connected to the first voltage terminal and the trigger terminal respectively, and a control terminal of the semiconductor switch unit is electrically connected to the resistor and capacitor unit. An electrostatic discharge protection device as described in claim 1, wherein the width of the first polysilicon layer is smaller than the width of the first shallow trench isolation region, or the width of the second polysilicon layer is smaller than the width of the third shallow trench isolation region. An electrostatic discharge protection device as described in claim 1, wherein the ratio of the width of the first polysilicon layer divided by the width of the first shallow trench isolation region is between 70% and 90%, or the ratio of the width of the second polysilicon layer divided by the width of the third shallow trench isolation region is between 70% and 90%. An electrostatic discharge protection device as described in claim 1, wherein the sum of the shortest distance between the first P-type well and the side of the first high-voltage P-type well plus the shortest distance between the first N-type well and the side of the first high-voltage N-type well is less than the width of the first polysilicon layer, or the sum of the shortest distance between the second P-type well and the side of the second high-voltage P-type well plus the shortest distance between the first N-type well and the other side of the first high-voltage N-type well is less than the width of the second polysilicon layer. An electrostatic discharge protection device comprises: An electrostatic discharge protection element comprises: A first high voltage N-type well, a second high voltage N-type well and a third high voltage N-type well; A first high voltage P-type well and a second high voltage P-type well, the first high voltage P-type well having two opposite sides directly contacting one side of the first high voltage N-type well and one side of the second high voltage N-type well, and the second high voltage P-type well having two opposite sides directly contacting the other side of the first high voltage N-type well and one side of the third high voltage N-type well; A first N-type well, a second N-type well and a third N-type well are respectively located in the first high-voltage N-type well, the second high-voltage N-type well and the third high-voltage N-type well; A first P-type well and a second P-type well are respectively located in the first high-voltage P-type well and the second high-voltage P-type well; A first P-type heavily doped region, a second P-type heavily doped region and a third P-type heavily doped region are respectively located on the first N-type well, the first P-type well and the second P-type well; A first N-type heavily doped region and a second N-type heavily doped region are respectively located on the second N-type well and the third N-type well; a first shallow trench isolation region, a second shallow trench isolation region, a third shallow trench isolation region and a fourth shallow trench isolation region, the first shallow trench isolation region is located between the second P-type heavily doped region and the first P-type heavily doped region, the second shallow trench isolation region is located between the first N-type heavily doped region and the second P-type heavily doped region, the third shallow trench isolation region is located between the third P-type heavily doped region and the first P-type heavily doped region, and the fourth shallow trench isolation region is located between the second N-type heavily doped region and the third P-type heavily doped region; and A first polysilicon layer and a second polysilicon layer, the first polysilicon layer is located on the first shallow trench isolation region, the first polysilicon layer directly contacts the first shallow trench isolation region, the second polysilicon layer is located on the third shallow trench isolation region, the second polysilicon layer directly contacts the third shallow trench isolation region; and A trigger circuit, electrically connected to the electrostatic discharge protection element through a first voltage terminal, a second voltage terminal and a trigger terminal, the trigger circuit comprising: A resistor, one end of which is electrically connected to the first N-type heavily doped region, the second P-type heavily doped region, the third P-type heavily doped region and the second N-type heavily doped region through the first voltage terminal; A capacitor, one end of which is electrically connected to the other end of the resistor, and the other end of which is electrically connected to the first P-type heavily doped region through the second voltage terminal; and A transistor, two ends of the transistor are electrically connected to the first voltage end and the trigger end respectively, the trigger end is electrically connected to the first polysilicon layer and the second polysilicon layer, a control end of the transistor is electrically connected to the other end of the resistor and the end of the capacitor, after the trigger circuit detects electrostatic discharge through the first voltage end, the trigger circuit applies voltage to the first polysilicon layer and the second polysilicon layer through the trigger end, so as to reduce the trigger voltage of the electrostatic discharge protection element. An electrostatic discharge protection device as described in claim 6, wherein the ratio of the width of the first polysilicon layer divided by the width of the first shallow trench isolation region is between 70% and 90%, and the ratio of the width of the second polysilicon layer divided by the width of the third shallow trench isolation region is between 70% and 90%. An electrostatic discharge protection device as described in claim 6, wherein the sum of the shortest distance between the first P-type well and the side of the first high-voltage P-type well plus the shortest distance between the first N-type well and the side of the first high-voltage N-type well is less than the width of the first polysilicon layer, and the sum of the shortest distance between the second P-type well and the side of the second high-voltage P-type well plus the shortest distance between the first N-type well and the other side of the first high-voltage N-type well is less than the width of the second polysilicon layer. An electrostatic discharge protection device as described in claim 6, wherein the transistor is a P-type transistor, the gate of the P-type transistor serves as the control terminal, the source of the P-type transistor is electrically connected to the first voltage terminal, and the drain of the P-type transistor is electrically connected to the trigger terminal. An electrostatic discharge protection device as described in claim 6, wherein the width of the first polysilicon layer is smaller than the width of the first shallow trench isolation region, and the width of the second polysilicon layer is smaller than the width of the third shallow trench isolation region.

Images