TW202008550A - Semiconductor structure and ESD protection device - Google Patents

Abstract

A semiconductor structure includes a first P-well, a first P-type diffusion region, a first N-type diffusion region, a second P-type diffusion region, and a first poly-silicon layer. The first P-type diffusion region is deposited in the first P-well and coupled to a first electrode. The first N-well is adjacent to the P-well. The first N-type diffusion region is deposited in the first N-well. The second P-type diffusion region is deposited between the first P-type diffusion region and the first N-type diffusion region, which is deposited in the first N-well. The second P-type diffusion region and the first N-type diffusion region are coupled to a second electrode. The first poly-silicon layer is deposited on the first P-type diffusion region.

Description

Semiconductor structure and electrostatic protection device

The present invention relates in detail to a semiconductor structure, and particularly relates to a semiconductor structure as an electrostatic protection device.

The integrated circuit system can cause serious damage due to various electrostatic discharge events. A major electrostatic discharge mechanism comes from the human body, which is called the Human Body Model (HBM). The human body is in 100 nanoseconds ( In the time of about nano-second), a tip current of several amperes is generated to the integrated circuit and the circuit is burned. The second electrostatic discharge mechanism comes from metal objects and is called the machine discharge mode (Machine Model, MM), which produces a much higher rise time and current level than the human discharge mode. The third ESD mechanism is the Charged-Device Model (CDM), in which the integrated circuit itself accumulates charge and discharges to ground in less than 0.5 nanosecond rise time. Therefore, we need effective electrostatic protection devices to protect integrated circuits from electrostatic discharge.

In view of this, the present invention provides a semiconductor structure including: a first P-type well, a first P-type diffusion region, a first N-type well, a first N-type diffusion region, and a second P-type diffusion region And a first polysilicon layer. The first P-type diffusion region is disposed in the first P-type well, and is coupled to a first electrode. The first N-type well is adjacent to the first P-type well. The first N-type diffusion region is disposed in the first N-type well. The second P-type diffusion region is disposed between the first P-type diffusion region and the first N-type diffusion region, and is disposed within the first N-type well, wherein the second P-type diffusion region and the first An N-type diffusion region is coupled to a second electrode. The first polysilicon layer is disposed on the first P-type diffusion region.

According to an embodiment of the invention, the semiconductor structure further includes: an epitaxial layer, a second P-type well and a second N-type well. The second P-type well is disposed above the epitaxial layer, and the first P-type well is disposed within the first P-type well. The second N-type well is disposed above the epitaxial layer and adjacent to the second P-type well, wherein the first N-type well is disposed within the second N-type well, wherein the epitaxial layer is It is N type.

According to an embodiment of the invention, the first polysilicon layer is coupled to the first electrode.

According to another embodiment of the present invention, the first polysilicon layer is floating.

According to an embodiment of the invention, the semiconductor structure further includes: a first oxide protective layer and a shallow trench isolation region. The first oxidation protection layer is formed on the second P-type diffusion region and is adjacent to the first polysilicon layer, wherein the oxidation protection layer and the first polysilicon layer have a first distance. The shallow trench isolation region is formed between the first P-type diffusion region and the second P-type diffusion region.

According to an embodiment of the invention, the first P-type diffusion region and the shallow trench isolation region have a second spacing, and the second type diffusion region is directly coupled to the shallow trench isolation region.

According to another embodiment of the present invention, the first polysilicon layer is disposed on the first P-type diffusion region and the second P-type diffusion region.

According to an embodiment of the invention, the semiconductor structure further includes a second polysilicon layer. The second polysilicon layer is disposed on the second P-type diffusion region and the first N-type diffusion region, wherein the second polysilicon layer is floating.

The present invention further provides an electrostatic protection device for discharging the electrostatic charge of a first electrode to a second electrode, including: a first P-type well, a first P-type diffusion region, a first N-type well, A first N-type diffusion region, a second P-type diffusion region and a first polysilicon layer. The first P-type diffusion region is disposed in the first P-type well, and is coupled to the first electrode. The first N-type well is adjacent to the first P-type well. The first N-type diffusion region is disposed in the first N-type well. The second P-type diffusion region is disposed between the first P-type diffusion region and the first N-type diffusion region, and is disposed within the first N-type well, wherein the second P-type diffusion region and the first An N-type diffusion region is coupled to the second electrode. The first polysilicon layer is disposed on the first P-type diffusion region.

According to an embodiment of the invention, the first polysilicon layer is coupled to the first electrode.

According to another embodiment of the present invention, the first polysilicon layer is floating.

According to an embodiment of the invention, the electrostatic protection device further includes: a first oxide protective layer and a shallow trench isolation region. The first oxidation protection layer is formed on the second P-type diffusion region and adjacent to the first polysilicon layer, wherein the oxidation protection layer and the first polysilicon layer have a first distance. The shallow trench isolation region is formed between the first P-type diffusion region and the second P-type diffusion region.

According to an embodiment of the invention, the first P-type diffusion region and the shallow trench isolation region have a second spacing, and the second type diffusion region is directly coupled to the shallow trench isolation region.

According to another embodiment of the present invention, the first polysilicon layer is disposed on the first P-type diffusion region and the second P-type diffusion region.

According to an embodiment of the invention, the electrostatic protection device further includes: a second polysilicon layer. The second polysilicon layer is disposed on the second P-type diffusion region and the first N-type diffusion region, wherein the second polysilicon layer is floating.

100, 200, 300, 400, 500 ‧‧‧ semiconductor structure

600, 700, 800, 900, 1000 ‧‧‧ semiconductor structure

110‧‧‧First P-type diffusion area

120‧‧‧Second P-type diffusion area

130‧‧‧First N-type diffusion area

141, 541, 641, 741, 841, 941, 1043 ‧‧‧ polysilicon layer

142‧‧‧oxidation protective layer

151‧‧‧First electrode

152‧‧‧Second electrode

160‧‧‧ Shallow trench isolation area

943、1043‧‧‧Second polysilicon layer

PW1‧‧‧The first P type well

PW2‧‧‧Second P type well

NW1‧‧‧The first N-type well

NW2‧‧‧Second N-type well

EPI‧‧‧Epitaxial layer

S1‧‧‧ First pitch

S2‧‧‧Second pitch

Figure 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention; Figure 2 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention; Figure 3 is a display according to the present invention A cross-sectional view of a semiconductor structure according to another embodiment of the invention; FIG. 4 is a cross-sectional view showing a semiconductor structure according to another embodiment of the invention; FIG. 5 is a further embodiment according to the invention The cross-sectional view of the semiconductor structure; FIG. 6 is a cross-sectional view of another semiconductor structure according to another embodiment of the present invention; FIG. 7 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. Figure 8 is a cross-sectional view showing a semiconductor structure according to another embodiment of the present invention; Figure 9 is a cross-sectional view showing a semiconductor structure according to another embodiment of the present invention; and Figure 10 FIG. 2 is a cross-sectional view of a semiconductor structure according to another embodiment of the invention.

The following is a detailed description of the device substrate, the semiconductor device, and the manufacturing method of the semiconductor device of some embodiments of the present disclosure. It should be understood that the following description provides many different embodiments or examples for implementing different embodiments of the disclosed embodiments. The specific elements and arrangements described below are simply and clearly describing some embodiments of the present disclosure. Of course, these are only examples and not limitations of this disclosure. In addition, repeated reference numbers or labels may be used in different embodiments. These repetitions are merely to briefly describe some embodiments of the present disclosure, and do not mean that there is any correlation between the different embodiments and/or structures discussed. Furthermore, when a first material layer is located on or above a second material layer, it includes the case where the first material layer and the second material layer are in direct contact. Alternatively, there may be a situation where one or more other material layers are spaced apart, in which case, the first material layer and the second material layer may not be in direct contact.

In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element of the drawing to another element. It is understandable that if the device of the figure is turned upside down, the element on the "lower" side will become an element on the "higher" side.

Here, the terms “about”, “approximately” and “approximately” generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. The quantity given here is an approximate quantity, that is, if there is no specific description of "about", "approximate", or "approximately", the meaning of "approximate", "approximate", and "approximately" may still be implied.

It can be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or parts, these elements, components, regions , Layers, and/or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and/or parts. Therefore, a first element, component, region, layer, and/or portion discussed below may be referred to as a second element, component, region, layer, or without departing from the teachings of some embodiments of the present disclosure And/or part.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the disclosure. Understandably, these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be in an idealized or excessively formal manner Interpretation, unless specifically defined in the disclosed embodiments.

Some embodiments of the present disclosure can be understood together with the drawings. The drawings of the disclosed embodiments are also regarded as part of the description of the disclosed embodiments. It should be understood that the drawings of the disclosed embodiments are not shown in proportion to actual devices and components. The shape and thickness of the embodiment may be exaggerated in the drawings so as to clearly show the features of the disclosed embodiment. In addition, the structures and devices in the drawings are shown in a schematic manner so as to clearly show the features of the disclosed embodiments.

In some embodiments of the disclosure, relative terms such as "down", "up", "horizontal", "vertical", "below", "above", "top", "bottom", etc. should be treated as It is understood as the orientation shown in this paragraph and related drawings. This relative term is only for convenience of description, it does not mean that the device described in it needs to be manufactured or operated in a specific orientation. Terms such as "connection" and "interconnection", etc., for joints and connections, unless specifically defined, may refer to two structures directly contacting, or may refer to two structures not directly contacting, where other structures are located here Between the two structures. In addition, the term “joining and connecting” may also include a case where both structures are movable or both structures are fixed.

The embodiments of the present invention disclose embodiments of semiconductor devices, and the above embodiments may be included in integrated circuits (ICs) such as microprocessors, memory devices, and/or other devices. The above integrated circuit may also include different passive and active microelectronic components, such as thin-film resistors, other types of capacitors such as metal-insulator-metal capacitors (MIMCAP), inductors , Diodes, metal oxide semiconductor field-effect transistors (MOSFETs), complementary MOS transistors, bipolar junction transistors (BJTs), lateral diffusion Type MOS transistor, high power MOS transistor or other types of transistor. Those of ordinary skill in the technical field to which the present invention pertains will understand that semiconductor devices can also be used in integrated circuits that include other types of semiconductor devices.

FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the invention. As shown in FIG. 1, the semiconductor structure 100 includes a first P-type well PW1 and a first N-type well NW1. The first P-type diffusion region 110 is disposed within the first P-type well PW1, and the second P-type diffusion region 120 and the first N-type diffusion region 130 are disposed within the first N-type well NW1.

According to an embodiment of the invention, the semiconductor structure 100 further includes a first polysilicon layer 141 and an oxidation protection layer 142. As shown in FIG. 1, the first polysilicon layer 141 is formed on the first P-type diffusion region 110, and the oxidation protection layer 142 is formed on the second P-type diffusion region 120 and the first N-type diffusion region 130 Above, there is a first spacing S1 between the first polysilicon layer 141 and the oxidation protection layer 142.

According to an embodiment of the present invention, as shown in FIG. 1, the first polysilicon layer 141 is coupled to the first electrode 151. According to an embodiment of the present invention, the first N-type well NW1 surrounds the first P-type well PW1. Therefore, in the cross-sectional view of FIG. 1, the first N-type well NW1 is shown as being located in the first P-type well PW1 On both sides.

As shown in FIG. 1, the first P-type diffusion region 110 is coupled to the first electrode 151, and the second P-type diffusion region 120 and the first N-type diffusion region 130 are coupled to the second electrode 152. According to an embodiment of the invention, both the first electrode 151 and the second electrode 152 are metal layers.

As shown in FIG. 1, a shallow trench isolation (STI) 160 is disposed between the first P-type diffusion layer 110, the second P-type diffusion layer 120, and the first N-type diffusion layer 130 for The first P-type diffusion layer 110, the second P-type diffusion layer 120, and the first N-type diffusion layer 130 are electrically separated from each other.

According to an embodiment of the present invention, the first P-type diffusion region 110, the first N-type diffusion region 130, and the second P-type diffusion region 120 form a PNP transistor, wherein the first P-type diffusion region 110 is a collector ( collector), the first N-type diffusion region 130 is a base, and the second P-type diffusion region 130 is an emitter.

According to an embodiment of the invention, the semiconductor structure 100 shown in FIG. 1 is an electrostatic protection device. According to an embodiment of the present invention, the first electrode 151 is coupled to the supply voltage pad, and the second electrode 152 is coupled to the ground terminal, wherein the semiconductor structure 100 is used to accumulate static electricity accumulated by the supply voltage pad The charge is discharged to ground.

According to another embodiment of the present invention, the first electrode 151 is coupled to the input and output pads, and the second electrode 152 is coupled to the ground, wherein the semiconductor structure 100 is used to accumulate the electrostatic charge accumulated by the output and input pads Exclude to ground.

According to an embodiment of the present invention, the first polysilicon layer 141 can be used to generate free electron-electric pairs in the first P-type diffusion region 110, thereby increasing the protection capability of the electrostatic discharge machine model (MM). According to an embodiment of the invention, the protection capability of the mechanical discharge mode of the semiconductor structure 100 can reach 550V.

FIG. 2 is a cross-sectional view of a semiconductor structure according to another embodiment of the invention. Compared with FIG. 1, the semiconductor structure 200 of FIG. 2 further includes a second P-type well PW2, a second N-type well NW2, and an epitaxial layer EPI. The first P-type well PW1 is formed within the second P-type well PW2, and the first N-type well NW1 is formed within the second N-type well NW2. The second P-type well PW2 and the second N-type well NW2 are formed on the epitaxial layer EPI. According to an embodiment of the invention, the epitaxial layer EPI is N-type. According to an embodiment of the present invention, the second P-type well PW2, the second N-type well NW2, and the epitaxial layer EPI help to reduce the impedance of the path of electrostatic discharge, thereby effectively improving the machine discharge mode of electrostatic protection (machine model, MM) protection capability.

FIG. 3 is a cross-sectional view of a semiconductor structure according to another embodiment of the invention. Comparing the semiconductor structure 300 of FIG. 3 with the semiconductor structure 100 of FIG. 1, the first P-type diffusion region 110 and the shallow trench isolation region 160 have a second spacing S2 to increase the first P-type diffusion region 110 and The distance and the impedance of the second P-type diffusion region 120 are used to improve the protection capability of the electrostatic discharge machine model (MM).

FIG. 4 is a cross-sectional view of a semiconductor structure according to another embodiment of the invention. Comparing the semiconductor structure 400 of FIG. 4 with FIG. 2, the first P-type diffusion region 110 of the semiconductor structure 400 of FIG. 4 and the shallow trench isolation region 160 have a second spacing S2 to increase the first P-type diffusion The distance between the region 110 and the second P-type diffusion region 120 is to improve the protection capability of the machine model (MM) of electrostatic protection.

FIG. 5 is a cross-sectional view of a semiconductor structure according to another embodiment of the invention. Comparing the semiconductor structure 500 of FIG. 5 with the semiconductor structure 100 of FIG. 1, the semiconductor structure 500 includes a first polysilicon layer 541, wherein the first polysilicon layer 541 is formed in the first P-type diffusion region 110 on. As shown in FIG. 5, the first polysilicon layer 541 is not electrically coupled to the first electrode 151. In other words, the first polysilicon layer 541 is in a floating state.

FIG. 6 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. Comparing the semiconductor structure 600 of FIG. 6 with the semi-contractor structure 200 of FIG. 2, the semiconductor structure 600 includes a first polysilicon layer 641, where the first polysilicon layer 641 is not electrically coupled to the first Electrode 151. In other words, the first polysilicon layer 641 is in a floating state.

FIG. 7 is a cross-sectional view of a semiconductor structure according to another embodiment of the invention. Comparing the semiconductor structure 700 of FIG. 7 with the semiconductor structure 100 of FIG. 1, the semiconductor structure 700 includes a first polysilicon layer 741. As shown in FIG. 7, the first polysilicon layer 741 is formed on the first P-type diffusion layer 110 and the second P-type diffusion layer 120 and extends from the first P-type diffusion layer 110 to the second P-type diffusion layer 120, and the first polysilicon layer 741 is in a floating state.

According to an embodiment of the present invention, since the first polysilicon layer 741 extends from the first P-type diffusion layer 110 to the second P-type diffusion layer 120, the first pitch S1 shown in FIG. 1 can be omitted, and The circuit area occupied by the semiconductor structure 700 is reduced, thereby saving manufacturing costs. According to another embodiment of the present invention, the first polysilicon layer 741 may also be coupled to the first electrode 151 as shown in FIG. 1, which will not be repeated here.

FIG. 8 is a cross-sectional view of a semiconductor structure according to another embodiment of the invention. Comparing the semiconductor structure 800 of FIG. 8 with the semiconductor structure 200 of FIG. 2, the semiconductor structure 800 includes a first polysilicon layer 841. As shown in FIG. 8, the first polysilicon layer 841 is formed on the first P-type diffusion layer 110 and the second P-type diffusion layer 120 and extends from the first P-type diffusion layer 110 to the second P-type diffusion layer 120, and the first polysilicon layer 841 is in a floating state.

According to an embodiment of the present invention, since the first polysilicon layer 841 extends from the first P-type diffusion layer 110 to the second P-type diffusion layer 120, the first pitch S1 shown in FIG. 2 can be omitted. Compared with the semiconductor structure 200 shown in FIG. 2, the semiconductor structure 800 occupies a smaller circuit area, thereby saving manufacturing costs. According to another embodiment of the present invention, the first polysilicon layer 841 may also be coupled to the first electrode 151 as shown in FIG. 2 and will not be repeated here.

FIG. 9 is a cross-sectional view of a semiconductor structure according to another embodiment of the invention. Comparing the semiconductor structure 900 of FIG. 9 with the semiconductor structure 700 of FIG. 7, the semiconductor structure 900 includes a first polysilicon layer 941 and a second polysilicon layer 943, wherein the oxidation protection layer 142 of the semiconductor structure 700 is composed of The second polysilicon layer 943 is replaced.

As shown in FIG. 9, the first polysilicon layer 941 is also formed on the first P-type diffusion layer 110 and the second P-type diffusion layer 120 and extends from the first P-type diffusion layer 110 to the second P-type diffusion layer 120. The second polysilicon layer 943 is formed on the second P-type diffusion layer 120 and the first N-type diffusion layer 130.

According to an embodiment of the present invention, since the oxidation protection layer 142 of the semiconductor structure 700 of FIG. 7 is replaced by the second polysilicon layer 943, the first P-type diffusion layer 110, the second P-type diffusion layer 120, and the first The N-type diffusion layer 130 is all a polysilicon layer, so that the manufacturing cost of the photomask of the oxidation protection layer can be saved.

According to an embodiment of the invention, the first polysilicon layer 941 is in a floating state. According to another embodiment of the present invention, the first polysilicon layer 941 may also be coupled to the first electrode 151. According to an embodiment of the invention, the second polysilicon layer 943 is in a floating state. According to another embodiment of the present invention, the second polysilicon layer 943 can also be coupled to the second electrode 152.

FIG. 10 is a cross-sectional view of a semiconductor structure according to another embodiment of the invention. Comparing the semiconductor structure 1000 of FIG. 10 with the semiconductor structure 800 of FIG. 8, the semiconductor structure 1000 includes a first polysilicon layer 1041 and a second polysilicon layer 1043, wherein the oxidation protection layer 142 of the semiconductor structure 800 is composed of The second polysilicon layer 1043 is replaced.

According to an embodiment of the present invention, since the oxidation protection layer 142 of the semiconductor structure 800 of FIG. 8 is replaced by the second polysilicon layer 1043, the first P-type diffusion layer 110, the second P-type diffusion layer 120, and the first The N-type diffusion layer 130 is all a polysilicon layer, so that the manufacturing cost of the photomask of the oxidation protection layer can be saved.

According to an embodiment of the invention, the first polysilicon layer 1041 is in a floating state. According to another embodiment of the present invention, the first polysilicon layer 1041 can also be coupled to the first electrode 151. According to an embodiment of the invention, the second polysilicon layer 1043 is in a floating state. According to another embodiment of the present invention, the second polysilicon layer 1043 can also be coupled to the second electrode 152.

The present invention proposes a semiconductor structure of an electrostatic protection device to effectively improve the protection capability of the electrostatic discharge machine discharge mode. According to many embodiments of the present invention, the protection capability of the machine discharge mode can be up to 550V.

Although the embodiments and advantages of the present disclosure have been disclosed above, it should be understood that anyone with ordinary knowledge in the technical field can make changes, substitutions, and retouching without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material composition, devices, methods, and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the technical field can implement some implementations from the present disclosure. In the disclosure of the examples, understand the current or future development of processes, machines, manufacturing, material composition, devices, methods and steps, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein. This disclosure uses some embodiments. Therefore, the protection scope of the present disclosure includes the above processes, machines, manufacturing, material composition, devices, methods and steps. In addition, each patent application scope constitutes a separate embodiment, and the protection scope of the present disclosure also includes a combination of each patent application scope and embodiment.

100‧‧‧Semiconductor structure

110‧‧‧First P-type diffusion area

120‧‧‧Second P-type diffusion area

130‧‧‧First N-type diffusion area

141‧‧‧The first polysilicon layer

142‧‧‧oxidation protective layer

151‧‧‧First electrode

152‧‧‧Second electrode

160‧‧‧ Shallow trench isolation area

PW1‧‧‧The first P type well

NW1‧‧‧The first N-type well

S1‧‧‧ First pitch

Claims (15)

A semiconductor structure includes: a first P-type well; a first P-type diffusion region, disposed within the first P-type well, and coupled to a first electrode; a first N-type well, and the above The first P-type wells are adjacent; a first N-type diffusion area is disposed within the first N-type well; a second P-type diffusion area is disposed within the first P-type diffusion area and the first N-type well Between the diffusion regions and within the first N-type well, wherein the second P-type diffusion region and the first N-type diffusion region are coupled to a second electrode; and a first polysilicon layer , Disposed above the first P-type diffusion region. The semiconductor structure as described in item 1 of the patent application scope further includes: an epitaxial layer; a second P-type well disposed on the epitaxial layer, wherein the first P-type well is disposed on the first Within the P-type well; and a second N-type well disposed on the epitaxial layer and adjacent to the second P-type well, wherein the first N-type well is disposed in the second N-type well In the above, the above epitaxial layer system is N-type. The semiconductor structure as described in item 1 of the patent application scope, wherein the first polysilicon layer is coupled to the first electrode. The semiconductor structure as described in item 1 of the patent application scope, wherein the first polysilicon layer is floating. The semiconductor structure as described in item 1 of the patent application scope further includes: a first oxidation protection layer formed on the second P-type diffusion region and adjacent to the first polysilicon layer, wherein the oxidation protection The layer and the first polysilicon layer have a first distance; and a shallow trench isolation region is formed between the first P-type diffusion region and the second P-type diffusion region. The semiconductor structure as recited in item 5 of the patent application range, wherein the first P-type diffusion region and the shallow trench isolation region have a second pitch, and the second type diffusion region is directly coupled to the shallow trench isolation region. The semiconductor structure as described in item 1 of the patent application range, wherein the first polysilicon layer is disposed on the first P-type diffusion region and the second P-type diffusion region. The semiconductor structure as described in item 1 of the patent application scope further includes: a second polysilicon layer disposed on the second P-type diffusion region and the first N-type diffusion region, wherein the second polysilicon layer The silicon layer is floating. An electrostatic protection device for discharging the electrostatic charge of a first electrode to a second electrode, comprising: a first P-type well; a first P-type diffusion area, which is arranged in the first P-type well, And coupled to the first electrode; a first N-type well adjacent to the first P-type well; a first N-type diffusion region disposed within the first N-type well; a second P-type well A diffusion region is disposed between the first P-type diffusion region and the first N-type diffusion region, and is disposed within the first N-type well, wherein the second P-type diffusion region and the first N-type diffusion The region is coupled to the second electrode; and a first polysilicon layer is disposed on the first P-type diffusion region. The electrostatic protection device as described in item 9 of the patent application range, wherein the first polysilicon layer is coupled to the first electrode. The electrostatic protection device as described in item 9 of the patent application scope, wherein the first polysilicon layer is floating. The electrostatic protection device as described in item 9 of the patent application scope further includes: a first oxidation protection layer formed on the second P-type diffusion region and adjacent to the first polysilicon layer, wherein the oxidation The protective layer and the first polysilicon layer have a first distance; and a shallow trench isolation region is formed between the first P-type diffusion region and the second P-type diffusion region. The electrostatic protection device as described in item 12 of the patent application range, wherein the first P-type diffusion region and the shallow trench isolation region have a second spacing, and the second type diffusion region is directly coupled to the shallow trench isolation region . The electrostatic protection device as described in item 9 of the patent application range, wherein the first polysilicon layer is disposed on the first P-type diffusion region and the second P-type diffusion region. The electrostatic protection device as described in item 9 of the patent application scope further includes: a second polysilicon layer disposed on the second P-type diffusion region and the first N-type diffusion region, wherein the second The crystalline silicon layer is floating.

Images