TWI870188B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a plurality of word line structures and a insulating structure. Each of the plurality of word line structures includes a floating gate, a control gate a first mask layer and a second mask layer. The control gate is disposed over the floating gate. The first mask layer is disposed over the control gate. A material of the first mask layer includes a nitride. The second mask layer is disposed on the first mask layer. A material of the second mask layer includes semiconductor. The insulating structure is disposed on the plurality of word line structures and covers top surfaces and sidewalls of the second mask layers of the plurality of word line structures. An air gap is between the adjacent word line structures.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a device and a manufacturing method thereof, and in particular to a semiconductor device and a manufacturing method thereof.

Flash memory has become a non-volatile memory component widely used in personal computers and electronic products because it can store, read, and erase data multiple times, and the stored data will not disappear after power failure.

With the advancement of technology, all kinds of electronic products are developing towards being thinner and smaller. However, under this trend, the critical size of flash memory is also gradually shrinking, which leads to many challenges in the flash memory manufacturing process. For example, as the density of flash memory continues to increase, the coupling interference between memory cells also increases, which in turn affects the durability and reliability of flash memory.

The present invention provides a semiconductor device and a manufacturing method thereof, which can improve the gate coupling rate of the semiconductor device.

The semiconductor device of the present invention includes a plurality of word line structures and an insulating structure. The plurality of word line structures are arranged on a substrate. Each of the plurality of word line structures includes a floating gate, a control gate, a first mask layer and a second mask layer. The control gate is arranged on the floating gate. The first mask layer is arranged on the control gate, wherein the material of the first mask layer includes nitride. The second mask layer is arranged on the first mask layer, wherein the material of the second mask layer includes a semiconductor. The insulating structure is arranged on the plurality of word line structures and covers the top surface and side walls of the second mask layer of the plurality of word line structures. There is an air gap between the plurality of adjacent word line structures.

In one embodiment of the present invention, the above-mentioned insulating structure also extends to the side walls of a plurality of word line structures.

In one embodiment of the present invention, the above-mentioned insulating structure further extends from the sidewalls of a plurality of word line structures to the substrate between a plurality of adjacent word line structures.

In one embodiment of the present invention, the air gap is surrounded by an insulating structure.

In one embodiment of the present invention, each of the above-mentioned multiple word line structures further includes a protection layer, and the protection layer partially covers the side wall of the control gate.

In an embodiment of the present invention, the control gate includes a first control gate and a second control gate. The material of the first control gate includes polysilicon. The second control gate is disposed on the first control gate, wherein the material of the second control gate includes metal. The protective layer is located on the sidewall of the first control gate.

In one embodiment of the present invention, the second control gate directly contacts the air gap.

In one embodiment of the present invention, the second mask layer has a chamfered structure.

In an embodiment of the present invention, the maximum width of the second mask layer is greater than the maximum width of the first mask layer.

In one embodiment of the present invention, the side wall of the second mask layer is substantially aligned with the side wall of the first mask layer.

The manufacturing method of the semiconductor device of the present invention includes the following steps. A plurality of stacked structures separated from each other are formed on a substrate. Each of the plurality of stacked structures includes a floating gate, a control gate, a first mask layer and a second mask material layer. The control gate is arranged on the floating gate. The first mask layer is arranged on the control gate, wherein the material of the first mask layer includes nitride. The second mask material layer is arranged on the first mask layer, wherein the material of the second mask material layer includes semiconductor. The second mask material layer is subjected to an epitaxial growth process. The second mask material layer that has undergone the epitaxial growth process is subjected to an oxidation process, wherein the periphery of the second mask material layer is oxidized to form a cap layer, and the unoxidized portion of the second mask material layer forms a second mask layer.

In an embodiment of the present invention, after the second mask material layer that has undergone the epitaxial growth process is oxidized, the cap layers of the adjacent stacked structures are laterally connected to each other, so that the spaces between the adjacent stacked structures are sealed to form air gaps.

In one embodiment of the present invention, before the second mask material layer that has undergone the epitaxial growth process is subjected to the oxidation process, the second mask material layers of the adjacent stacked structures are connected to each other.

In an embodiment of the present invention, the shortest distance between the cap layers of the adjacent stacked structures is smaller than the shortest distance between the control gates of the adjacent stacked structures.

In an embodiment of the present invention, the manufacturing method further includes forming an interlayer dielectric layer on the cap layer, and the interlayer dielectric layer is laterally connected on the plurality of stacked structures.

In one embodiment of the present invention, the interlayer dielectric layer is formed on the sidewalls of the stacked structures through the gaps between the cap layers of the adjacent stacked structures.

In one embodiment of the present invention, the interlayer dielectric layer seals the gaps between the capping layers of the plurality of stacked structures, and forms air gaps between the adjacent plurality of stacked structures.

In one embodiment of the present invention, the manufacturing method further includes forming a protective layer on a portion of the side walls of the plurality of stacked structures through a plasma oxidation process.

Based on the above, the semiconductor device of the present invention forms a partial insulating structure on the word line structure through an epitaxial growth process and an oxidation process, and connects the insulating structures to form an air gap between adjacent word line structures, so that the gate coupling rate of the semiconductor device is improved, thereby improving the writing speed and durability of the semiconductor device and improving the coupling interference between the word line structures. In addition, by controlling the epitaxial growth process and the oxidation process, the size of the air gap can be flexibly controlled to meet the process requirements.

The present invention is more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numerals represent the same or similar elements, and the following paragraphs will not be repeated one by one.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or portions, these elements, components, regions, and/or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Therefore, the "first element", "component", "region", "layer" or "portion" discussed below may be referred to as a second element, component, region, layer or portion without departing from the teachings of this article.

In addition, directional terms mentioned herein, such as “upper”, “lower”, etc., are only used to refer to the directions of the drawings and are not used to limit the present invention.

1A to 1I are cross-sectional schematic diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG2A and FIG2B are cross-sectional schematic diagrams of other embodiments of FIG1G.

Referring to FIG. 1A , first, a plurality of stacked structures 100 separated from each other are formed on a substrate 102. The plurality of stacked structures 100 are arranged in a first direction D1, and each stacked structure 100 includes a floating gate 120, a control gate 140, a first mask layer 150, and a second mask material layer 160 stacked in a second direction D2, wherein the first direction D1 intersects the second direction D2. In some embodiments, the first direction D1 and the second direction D2 are perpendicular to each other. The control gate 140 is disposed on the floating gate 120. The first mask layer 150 is disposed on the control gate 140. The second mask material layer 160 is disposed on the first mask layer 150. In this embodiment, the stack structure 100 further includes a tunnel dielectric layer 110 and an inter-gate dielectric layer 130. The tunnel dielectric layer 110 is disposed between the substrate 102 and the floating gate 120, and extends on the top surface of the substrate 102 to connect with the tunnel dielectric layer 110 of the adjacent stack structure 100. The inter-gate dielectric layer 130 is disposed between the floating gate 120 and the control gate 140. That is, the floating gates 120 , the intergate dielectric layer 130 , the control gate 140 , the first mask layer 150 and the second mask material layer 160 of the plurality of stacked structures 100 are separated from each other in the first direction D1 , and the tunnel dielectric layers 110 of the plurality of stacked structures 100 are connected to each other in the first direction D1 .

In some embodiments, the substrate 102 includes a semiconductor substrate (eg, silicon, silicon germanium, or other suitable semiconductor materials), a silicon on insulator (SOI) substrate, or a combination thereof.

In some embodiments, the tunnel dielectric layer 110 may include silicon oxide. The intergate dielectric layer 130 may be, for example, a composite layer composed of oxide/nitride/oxide (ONO), or a single layer structure including silicon oxide or silicon nitride.

In some embodiments, the floating gate 120 may include polysilicon or other suitable materials.

In some embodiments, the control gate 140 may include polysilicon, metal, a combination thereof, or other suitable materials. In some embodiments, the control gate 140 may be a single-layer or multi-layer structure. For example, the control gate 140 may include a first control gate 142 and a second control gate 144. The first control gate 142 is located on the inter-gate dielectric layer 130, and its material includes polysilicon. The second control gate 144 is located on the first control gate 142, and the material of the second control gate 144 includes a metal, such as tungsten, copper, gold, an alloy thereof, or other suitable metal materials. However, the present invention is not limited thereto, and the number of layers and materials of the control gate 140 can be selected according to actual needs.

The material of the first mask material layer 150 may include nitride, such as silicon nitride. The material of the second mask material layer 160 may include semiconductor, such as polysilicon. In some embodiments, the material of the second mask material layer 160 may be undoped polysilicon.

1B , a protective layer 170 is formed on a portion of the sidewalls of the plurality of stacked structures 100. For example, the protective layer 170 may be selectively formed on the sidewalls of the tunnel dielectric layer 110, the sidewalls of the floating gate 120, the sidewalls of the intergate dielectric layer 130, the sidewalls of the first control gate 142, the sidewalls of the first mask layer 150, and the top surface and sidewalls of the second mask material layer 160 by a plasma oxidation process, but the protective layer 170 is not formed on the sidewalls of the second control gate 144. In some embodiments, the plasma oxidation process is a slot plane antenna (SPA) process, which is a process that uses a microwave slot antenna to generate plasma to form oxide. In some embodiments, the process temperature of the plasma oxidation process is between 400°C and 500°C. In some embodiments, the plasma oxidation process includes introducing process gases of _H2 and _O2 , wherein the ratio of _H2 to _O2 is 2:1 to 4:1. In this way, the plasma oxidation process can oxidize non-metallic materials without oxidizing metal materials. Therefore, in FIG. 1B, only the tunneling dielectric layer 110, the floating gate 120, the intergate dielectric layer 130, the first control gate 142, the first mask layer 150 and the second mask material layer 160 are oxidized, while the second control gate 144 is basically not oxidized.

1C , a sacrificial layer 109 is formed on the substrate 102 and covers the plurality of stacked structures 100 and the protective layer 170. In other words, the sacrificial layer 109 fills the space between adjacent stacked structures 100 and covers the protective layer 170. In some embodiments, the material of the sacrificial layer 109 includes photoresist, polysilicon or a combination thereof.

1D , the sacrificial layer 109 is etched back to remove a portion of the sacrificial layer 109 and expose a portion of the protective layer 170 . For example, the sacrificial layer 109 may be etched back to approximately the middle of the first mask layer 150 , so that the top surface of the remaining sacrificial layer 109 is approximately at the middle of the first mask layer 150 .

1E , the exposed protective layer 170 is removed to expose the second mask material layer 160 and a portion of the first mask layer 150. Specifically, the top surface and sidewalls of the second mask material layer 160 and a portion of the sidewalls of the first mask layer 150 are exposed. The remaining protective layer 170 is located on another portion of the sidewalls of the first mask layer 150, the sidewalls of the tunnel dielectric layer 110, the sidewalls of the floating gate 120, the sidewalls of the intergate dielectric layer 130, and the sidewalls of the first control gate 142.

Referring to FIG. 1F , the remaining sacrificial layer 109 is removed.

Referring to FIG. 1G , an epitaxy growth process is performed on the second mask material layer 160. For ease of description, the second mask material layer before the epitaxy growth process is represented by symbol 160, and the second mask material layer after the epitaxy growth process is represented by symbol 160'. The second mask material layer 160' after the epitaxy growth process grows outward from the top surface and side walls of the second mask material layer 160 into the second mask material layer 160' according to the lattice arrangement of the original second mask material layer 160 and the adjustment of process parameters. In some embodiments, the cross-sectional shape of the second mask material layer 160' is a pentagon. In other embodiments, as shown in FIG. 2A and FIG. 2B , the cross-sectional shape of the second mask material layer 160′ after the epitaxial growth process may also be a hexagonal or arcuate profile. However, the present invention is not limited thereto, and the cross-sectional shape of the second mask material layer 160′ may include an ellipse, a rectangle, a pentagon, a hexagon, or other polygonal shapes.

In some embodiments, there is a gap g1 between the second mask material layers 160' of the adjacent stacked structures 100, that is, the adjacent second mask material layers 160' are not connected to each other. In some embodiments, the shortest distance d1 of the gap g1 (i.e., the shortest distance between the adjacent second mask material layers 160') is smaller than the shortest distance d2 between the adjacent second control gates 144. The shortest distance d2 between the adjacent second control gates 144 and the shortest distance d1 of the gap g1 can be adjusted according to actual needs, and the present invention is not limited thereto. For example, the shortest distance d1 of the gap g1 can be smaller than 1/3 of the shortest distance d2 between the second control gates 144 (i.e., ) so that the gap g1 is sealed during the subsequent oxidation process.

Referring to FIG. 1H , the second mask material layer 160′ that has undergone the epitaxial growth process is subjected to an oxidation process P, wherein the periphery of the second mask material layer 160′ is oxidized to form a cap layer 182, and the unoxidized portion of the second mask material layer 160′ is formed as a second mask layer 160″. Thus, the tunnel dielectric layer 110, the floating gate 120, the intergate dielectric layer 130, the control gate 140, the first mask layer 150, and the second mask layer 160″ can form a stacked structure 100′ or a word line structure 100′, and the cap layer 182 is disposed on the stacked structure 100′. In some embodiments, the oxidation process P may be similar to the above-mentioned plasma oxidation process, so that the second mask material layer 160' is oxidized from the outside to the inside. In some embodiments, the profile of the top cover layer 182 obtained after the oxidation process P is larger than the profile of the second mask material layer 160' (as shown in FIG. 1G ) before the oxidation process P is performed. From another perspective, the sum of the volumes of the top cover layer 182 and the second mask layer 160'' obtained after the oxidation process P is larger than the volume of the second mask material layer 160' before the oxidation process P is performed.

In FIG. 1H , the second mask layer 160″ has a protruding portion pr protruding from the sidewall 150a of the first mask layer 150, so that the maximum width W2 of the second mask layer 160″ in the first direction D1 is greater than the maximum width W1 of the first mask layer 150 in the first direction D1. For example, the protruding portion pr is located on the sidewall 160d of the second mask layer 160″. However, the present invention is not limited thereto, and in other embodiments, the portion pr of the second mask layer 160″ protruding from the sidewall 150a of the first mask layer 150 may also be oxidized in the oxidation process P.

In some embodiments, the second mask layer 160'' has a chamfered structure C. Specifically, in FIG. 1H , the top surface 160a of the second mask layer 160'' is connected to the inclined surface 160b, wherein the angle θ between the top surface 160a and the inclined surface 160b is greater than 90 degrees. In some embodiments, the inclined surface 160b is connected to the side wall 160c of the protruding portion pr. In some embodiments, the side wall 160d of the lower portion of the second mask layer 160'' is substantially aligned with the side wall 150a of the first mask layer 150. That is, the protruding portion pr protrudes from the lower portion of the second mask layer 160''.

In some embodiments, the capping layers 182 of adjacent stacking structures 100' are connected to each other laterally, so that the space between the adjacent stacking structures 100' is sealed to form an air gap AG. In some embodiments, the air gap AG directly contacts the second control gate 144. In some embodiments, the maximum width W of the air gap AG in the first direction D1 is the shortest distance d2 between the adjacent second control gates 144 in the first direction D1. In this way, the gate coupling ratio can be improved by improving the air gap ratio.

In some embodiments, the tunnel dielectric layer 110, the floating gate 120, the intergate dielectric layer 130, the first control gate 142, and the first mask layer 150 may also be oxidized in the oxidation process P, so that the protective layer 170 is slightly thickened, but the present invention is not limited thereto. In some embodiments, the protective layer 170 still maintains the same thickness after the oxidation process P.

1I , an interlayer dielectric layer 184 is formed on the cap layer 182, and the interlayer dielectric layer 184 is laterally connected on the plurality of stacked structures 100′. The cap layer 182 and the interlayer dielectric layer 184 may constitute an insulating structure 180. In some embodiments, the material of the interlayer dielectric layer 184 may include silicon oxide or other suitable insulating materials. Since the adjacent capping layers 182 are laterally connected before the interlayer dielectric layer 184 is formed, the interlayer dielectric layer 184 is only formed on the capping layer 182 and does not enter the air gap AG, so that the air gap AG between the adjacent stacking structures 100' can be maximized.

In FIG. 1I , the interface between the cap layer 182 and the interlayer dielectric layer 184 is indicated by a dotted line for convenience of explanation and is not intended to limit the present invention. It should be understood that if the cap layer 182 and the interlayer dielectric layer 184 are made of the same material, the interface between the two may be difficult to distinguish in practice.

The above process can substantially complete the manufacturing of the semiconductor device 10. Since the top cap layer 182 seals the space between adjacent stacked structures 100' during the oxidation process to maximize the air gap AG, the gate coupling rate can be significantly improved, thereby improving the performance of the semiconductor device 10 (including improving the writing speed, durability and improving the coupling interference between word line structures).

1I , the semiconductor device 10 includes a plurality of word line structures 100′ and an insulating structure 180. The plurality of word line structures 100′ are disposed on a substrate 102, wherein each of the plurality of word line structures 100′ includes a floating gate 120, a control gate 140, a first mask layer 150, and a second mask layer 160″. The control gate 140 is disposed on the floating gate 120. The first mask layer 150 is disposed on the control gate 140, wherein the material of the first mask layer 150 includes a nitride, such as silicon nitride or other suitable nitride materials. The second mask layer 160'' is disposed on the first mask layer 150, wherein the material of the second mask layer 160'' includes a semiconductor, such as polysilicon or other suitable semiconductor materials. The insulating structure 180 is disposed on the plurality of word line structures 100' and covers the top surface and sidewalls of the second mask layer 160'' of the plurality of word line structures 100'. There is an air gap AG between adjacent word line structures 100'.

Each of the plurality of word line structures 100' further includes a tunnel dielectric layer 110 and an inter-gate dielectric layer 130. The tunnel dielectric layer 110 is disposed on the substrate 102 and extends on the top surface of the substrate 102 to connect with the tunnel dielectric layer 110 of the adjacent word line structure 100'. The inter-gate dielectric layer 130 is disposed between the floating gate 120 and the control gate 140.

In some embodiments, the insulating structure 180 may include a plurality of cap layers 182 and an interlayer dielectric layer 184. The plurality of cap layers 182 are respectively disposed on the second mask layer 160″, and the interlayer dielectric layer 184 is disposed on the plurality of cap layers 182. In some embodiments, the material of the insulating structure 180 includes silicon oxide or other suitable insulating materials.

In some embodiments, the control gate 140 may be a single-layer or multi-layer structure. For example, the control gate 140 may include a first control gate 142 and a second control gate 144. The first control gate 142 is located on the inter-gate dielectric layer 130, and its material includes polysilicon. The second control gate 144 is located on the first control gate 142, and the material of the second control gate 144 includes a metal, such as tungsten, copper, gold, alloys thereof, or other suitable metal materials. However, the present invention is not limited thereto, and the number of layers and materials of the control gate 140 can be selected according to actual needs.

In some embodiments, the second mask layer 160 ″ has a chamfered structure C. In some embodiments, a maximum width W2 of the second mask layer 160 ″ is greater than a maximum width W1 of the first mask layer 150 .

In some embodiments, each of the plurality of word line structures 100′ further includes a protection layer 170, which partially covers the sidewalls of the control gate 140. For example, the protection layer 170 covers the sidewalls of the first control gate 142, but does not cover the sidewalls of the second control gate 144. In some embodiments, the protection layer 170 also covers the sidewalls of the tunnel dielectric layer 110, the floating gate 120, and the inter-gate dielectric layer 130.

In some embodiments, the second control gate 144 directly contacts the air gap AG, and the protection layer 170 directly contacts the air gap AG.

In FIG. 1I , the space enclosed by the sidewalls of the word line structure 100′, the insulating structure 180, and the tunnel dielectric layer 110 is filled with air gaps AG, so that the air gaps AG between adjacent word line structures 100′ are maximized, thereby increasing the gate coupling ratio and thereby improving the performance of the semiconductor device 10 (including increasing the writing speed, durability, and improving the coupling interference between word line structures).

FIG. 3A to FIG. 3B are cross-sectional schematic diagrams of a method for manufacturing a semiconductor device according to another embodiment of the present invention. It must be noted that the embodiment of FIG. 3A to FIG. 3B uses the component numbers and part of the content of the embodiment of FIG. 1A to FIG. 1I, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can refer to the aforementioned embodiment, which will not be repeated here. FIG. 3A can be a process continuing FIG. 1A to FIG. 1F, and the relevant process description can refer to the aforementioned.

Please refer to FIG. 3A , continuing the step of FIG. 1F , an epitaxy growth process is performed on the second mask material layer 160. For ease of description, the second mask material layer before the epitaxy growth process is represented by symbol 160, and the second mask material layer after the epitaxy growth process is represented by symbol 160'. The second mask material layer 160' after the epitaxy growth process grows from the top and side walls of the second mask material layer 160 to the outside according to the lattice arrangement of the original second mask material layer 160 and the adjustment of process parameters. In this embodiment, the cross-sectional shape of the second mask material layer 160' is a pentagon, however, the present invention is not limited thereto, and the cross-sectional shape of the second mask material layer 160' may include an ellipse, a rectangle, a pentagon, a hexagon or other polygonal shapes.

In this embodiment, the second mask material layers 160' of adjacent stacking structures 100 are connected to each other, that is, there is no gap between the second mask material layers 160' of adjacent stacking structures 100. For example, a corner of the second mask material layer 160' of the stacked structure 100a just touches a corresponding corner of the second mask material layer 160' of the adjacent stacked structure 100b, and the second mask material layer 160' of the stacked structure 100a and the second mask material layer 160' of the stacked structure 100b do not overlap in the second direction D2, so that when a subsequent oxidation process is performed, the contacting portion of the second mask material layer 160' of the stacked structure 100a and the second mask material layer 160' of the stacked structure 100b is fully oxidized to electrically isolate the adjacent stacked structures 100. If the second mask material layer 160' of the stacked structure 100a and the second mask material layer 160' of the stacked structure 100b overlap excessively, the overlapping portions of the adjacent stacked structures 100 may not be effectively electrically isolated from each other during a subsequent oxidation process due to insufficient oxidation, thereby causing problems in subsequent device operation.

Referring to FIG. 3B , the second mask material layer 160′ that has undergone the epitaxial growth process is subjected to an oxidation process P, wherein the periphery of the second mask material layer 160′ is oxidized to form a cap layer 182, and the unoxidized portion of the second mask material layer 160′ is formed as a second mask layer 160″. Thus, the tunnel dielectric layer 110, the floating gate 120, the intergate dielectric layer 130, the control gate 140, the first mask layer 150, and the second mask layer 160″ can form a stacked structure 100′ or a word line structure 100′, and the cap layer 182 is disposed on the stacked structure 100′. In some embodiments, the oxidation process P may be similar to the above-mentioned plasma oxidation process, so that the second mask material layer 160' is oxidized from the outside to the inside. In some embodiments, the profile of the top cover layer 182 obtained after the oxidation process P is larger than the profile of the second mask material layer 160' before the oxidation process P. From another perspective, the sum of the volumes of the top cover layer 182 and the second mask layer 160'' obtained after the oxidation process P is larger than the volume of the second mask material layer 160' before the oxidation process P.

In some embodiments, the second mask layer 160'' has a chamfered structure C. Specifically, in FIG. 3B , the top surface 160a of the second mask layer 160'' is connected to the inclined surface 160b, wherein the angle θ between the top surface 160a and the inclined surface 160b is greater than 90 degrees. In some embodiments, the inclined surface 160b is connected to the side wall 160d, and the side wall 160d of the second mask layer 160'' is substantially aligned with the side wall 150a of the first mask layer 150. That is, the inclined surface 160b is connected between the top surface 160a and the side wall 160d, and the maximum width W2 of the second mask layer 160'' is substantially equal to the maximum width W1 of the first mask layer 150. In FIG. 3B , there is no protrusion on the side wall 160 d of the second mask layer 160 ″, but the present invention is not limited thereto. In other embodiments, the side wall 160 d of the second mask layer 160 ″ may also have a protrusion similar to that shown in FIG. 1H .

In some embodiments, the capping layers 182 of adjacent stacking structures 100 are laterally connected to each other, so that the space between the adjacent stacking structures 100 is sealed to form an air gap AG. In some embodiments, the air gap AG directly contacts the second control gate 144. In some embodiments, the maximum width W of the air gap AG in the first direction D1 is the shortest distance d2 between the adjacent second control gates 144 in the first direction D1. In this way, the gate coupling ratio can be improved by improving the air gap ratio.

In some embodiments, the tunnel dielectric layer 110, the floating gate 120, the intergate dielectric layer 130, the first control gate 142, and the first mask layer 150 may also be oxidized in the oxidation process P, so that the protective layer 170 is slightly thickened, but the present invention is not limited thereto. In some embodiments, the protective layer 170 still maintains the same thickness after the oxidation process P.

Then, a process similar to that of FIG. 1I may be continued to form an interlayer dielectric layer 184 (not shown) on the cap layer 182, and the interlayer dielectric layer 184 is laterally connected to the plurality of stacked structures 100 but will not be formed into the air gap AG.

The above process can substantially complete the manufacturing of the semiconductor device 20. Since the top cap layer 182 seals the space between adjacent stacked structures 100' during the oxidation process to maximize the air gap AG, the gate coupling rate can be significantly improved, thereby improving the performance of the semiconductor device 20 (including improving the writing speed, durability and improving the coupling interference between word line structures).

3B , the semiconductor device 20 of the present embodiment is different from the semiconductor device 10 of FIG. 1I in that the sidewall 160d of the second mask layer 160″ of the word line structure 100′ of the semiconductor device 20 is substantially aligned with the sidewall 150a of the first mask layer 150. The second mask layer 160″ has a chamfer structure C, that is, the second mask layer 160″ has an inclined surface 160b connected between the top surface 160a and the sidewall 160d.

FIG. 4A to FIG. 4C are cross-sectional schematic diagrams of a method for manufacturing a semiconductor device according to another embodiment of the present invention. It must be noted that the embodiment of FIG. 4A to FIG. 4C uses the component numbers and partial contents of the embodiment of FIG. 1A to FIG. 1I, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the aforementioned embodiment, which will not be repeated here. FIG. 4A can be a process continuing FIG. 1A to FIG. 1F, and the relevant process description can refer to the aforementioned.

Please refer to FIG. 4A , continuing the step of FIG. 1F , an epitaxy growth process is performed on the second mask material layer 160. For ease of description, the second mask material layer before the epitaxy growth process is represented by symbol 160, and the second mask material layer after the epitaxy growth process is represented by symbol 160'. The second mask material layer 160' after the epitaxy growth process grows from the top and side walls of the second mask material layer 160 to the outside according to the lattice arrangement of the original second mask material layer 160 and the adjustment of process parameters. In this embodiment, the cross-sectional shape of the second mask material layer 160' is a pentagon, however, the present invention is not limited thereto, and the cross-sectional shape of the second mask material layer 160' may include an ellipse, a rectangle, a pentagon, a hexagon or other polygonal shapes.

In the present embodiment, there is a gap g2 between the second mask material layers 160' of the adjacent stacked structures 100, that is, the adjacent second mask material layers 160' are not connected to each other. In some embodiments, the shortest distance d3 of the gap g2 (i.e., the shortest distance between the adjacent second mask material layers 160') is smaller than the shortest distance d2 between the adjacent second control gates 144. The shortest distance d2 between the adjacent second control gates 144 and the shortest distance d3 of the gap g2 can be adjusted according to actual needs, and the present invention is not limited thereto. For example, the shortest distance d3 of the gap g2 can be greater than 1/5 of the shortest distance d2 between the second control gates 144 (i.e., ) so that the gap g2 will not be sealed during the subsequent oxidation process.

Referring to FIG. 4B , the second mask material layer 160′ that has undergone the epitaxial growth process is subjected to an oxidation process P, wherein the periphery of the second mask material layer 160′ is oxidized to form a cap layer 182, and the unoxidized portion of the second mask material layer 160′ is formed as a second mask layer 160″. Thus, the tunnel dielectric layer 110, the floating gate 120, the intergate dielectric layer 130, the control gate 140, the first mask layer 150, and the second mask layer 160″ can form a stacked structure 100′ or a word line structure 100′, and the cap layer 182 is disposed on the stacked structure 100′. In some embodiments, the oxidation process P may be similar to the above-mentioned plasma oxidation process, so that the second mask material layer 160' is oxidized from the outside to the inside. In some embodiments, the profile of the top cover layer 182 obtained after the oxidation process P is larger than the profile of the second mask material layer 160' before the oxidation process P. From another perspective, the sum of the volumes of the top cover layer 182 and the second mask layer 160'' obtained after the oxidation process P is larger than the volume of the second mask material layer 160' before the oxidation process P.

In FIG4B , the second mask layer 160″ has a protruding portion (not marked) protruding from the side wall 150a of the first mask layer 150, which is similar to the protruding portion pr in FIG1H , so that the maximum width W2 of the second mask layer 160″ in the first direction D1 is greater than the maximum width W1 of the first mask layer 150 in the first direction D1. However, the present invention is not limited thereto, and in other embodiments, the second mask layer 160″ may be similar to the second mask layer in FIG3B , without the protruding portion, so that the side wall of the second mask layer 160″ is aligned with the side wall of the first mask layer 150. In some embodiments, the second mask layer 160″ has a chamfered structure C, which is similar to the chamfered structure C in FIG. 1H . The related description can be referred to above and will not be repeated here.

In some embodiments, the top capping layers 182 of adjacent stacking structures 100' are separated from each other in the first direction D1, that is, the top capping layers 182 of adjacent stacking structures 100 do not contact each other. In some embodiments, after the oxidation process P is performed, there is a gap g2' between the top capping layers 182 of adjacent stacking structures 100, and the shortest distance d3' of the gap g2' is smaller than the shortest distance d3 of the gap g2 before the oxidation process P is performed. At this time, the space between the adjacent stacking structures 100 has not been sealed.

In some embodiments, the tunnel dielectric layer 110, the floating gate 120, the intergate dielectric layer 130, the first control gate 142, and the first mask layer 150 may also be oxidized in the oxidation process P, so that the protective layer 170 is slightly thickened, but the present invention is not limited thereto. In some embodiments, the protective layer 170 still maintains the same thickness after the oxidation process P.

4C , an interlayer dielectric layer 184 is formed on the cap layer 182, and the interlayer dielectric layer 184 is laterally connected on the plurality of stacked structures 100′. The cap layer 182 and the interlayer dielectric layer 184 may constitute an insulating structure 180. In the present embodiment, the interlayer dielectric layer 184 seals the gap g2′ between the cap layers 182 of the plurality of stacked structures 100′, and forms an air gap AG between adjacent stacked structures 100′, wherein the air gap AG is embedded in the interlayer dielectric layer 184 located between the adjacent stacked structures 100′. Since there is an air gap AG between adjacent stacked structures 100', the gate coupling rate can be improved. In FIG4C, the interface between the top cap layer 182 and the interlayer dielectric layer 184 is represented by a dotted line for the convenience of explanation, but is not used to limit the present invention. It should be understood that if the top cap layer 182 and the interlayer dielectric layer 184 are made of the same material, the interface between the two may be difficult to distinguish in practice.

In some embodiments, the interlayer dielectric layer 184 is also formed on the sidewalls of the plurality of stacked structures 100' through the gaps g2' (as shown in FIG. 4B ) between the top capping layers 182 of the plurality of adjacent stacked structures 100' (also referred to as word line structures 100'), and the interlayer dielectric layer 184 is also formed on the tunneling dielectric layer 110 extending between the adjacent stacked structures 100'. Since the interlayer dielectric layer 184 is formed on the tunnel dielectric layer 110, the thickness of the insulating layer on the substrate 102 between adjacent stacked structures 100' (i.e., the sum of the thicknesses T of the interlayer dielectric layer 184 and the tunnel dielectric layer 110) is increased, which helps to increase the current and thus improve the program efficacy.

The size of the air gap AG, the thickness of the interlayer dielectric layer 184 on the sidewall of the stack structure 100', or the thickness of the interlayer dielectric layer 184 on the tunnel dielectric layer 110 between adjacent stack structures 100' can be adjusted by controlling the sizes of the gaps g2 and g2'. For example, the shortest distance d3′ of the gap g2 between adjacent second mask material layers 160′ can be controlled by an epitaxial growth process, and the shortest distance d3 of the gap g2′ between adjacent top cap layers 182 can be controlled by an oxidation process P. The shortest distance of the gap g2′ determines the thickness of the interlayer dielectric layer 184 formed on the sidewalls of the stacked structure 100′ and the tunnel dielectric layer 110, as well as the size of the air gap AG (e.g., the maximum width W′ of the air gap AG).

The above process can substantially complete the manufacturing of the semiconductor device 30. Since there is a gap g2' between adjacent top cap layers 182 after the oxidation process P, the interlayer dielectric layer 184 can be formed on the sidewalls of the stacked structure 100' and the tunnel dielectric layer 110, and the gap g2' is sealed to form an air gap AG between adjacent stacked structures 100', so that the gate coupling rate of the semiconductor device 30 can be improved, and at the same time, its programming efficiency can be improved.

Referring to FIG. 4C , the semiconductor device 30 of this embodiment is different from the semiconductor device 10 of FIG. 1I in that the insulating structure 180 of the semiconductor device 30 further extends to the sidewalls of the multiple word line structures 100′. In some embodiments, the insulating structure 180 further extends from the sidewalls of the multiple word line structures 100′ to the substrate 102 between the adjacent multiple word line structures 100′. This helps to improve the program efficacy of the semiconductor device 30.

In some embodiments, the air gap AG is surrounded by the insulating structure 180, that is, the maximum width W' of the air gap AG in the first direction D1 is smaller than the shortest distance d2 between the second control gates 144 in the first direction D1. Compared with the case where there is no air gap between adjacent word line structures, the air gap AG between adjacent word line structures 100' can improve the gate coupling ratio of the semiconductor device 30.

In summary, the semiconductor device of the present invention forms a partial insulating structure on the word line structure through an epitaxial growth process and an oxidation process, and connects the insulating structures to form an air gap between adjacent word line structures, thereby improving the gate coupling rate of the semiconductor device, thereby improving the writing speed and durability of the semiconductor device and improving the coupling interference between the word line structures. In addition, by controlling the epitaxial growth process and the oxidation process, the size of the air gap can be flexibly controlled to meet the process requirements.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

10, 20, 30: semiconductor device 100, 100a, 100b: stacked structure 100’: stacked structure/word line structure 102: substrate 109: sacrificial layer 110: tunnel dielectric layer 120: floating gate 130: inter-gate dielectric layer 140: control gate 142: first control gate 144: second control gate 150: first mask layer 150a, 160c, 160d: sidewall 160, 160’: second mask material layer 160’’: second mask layer 160a: top surface 160b: inclined surface 170: Protective layer 180: Insulation structure 182: Cap layer 184: Interlayer dielectric layer d1, d2, d3, d3’: Shortest distance g1, g2, g2’: Gap pr: Protrusion AG: Air gap C: Chamfer structure D1: First direction D2: Second direction P: Oxidation process T: Total thickness W, W’, W1, W2: Maximum width θ: Angle

Figures 1A to 1I are schematic cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 2A and 2B are schematic cross-sectional views of other embodiments of Figure 1G. Figures 3A to 3B are schematic cross-sectional views of a method for manufacturing a semiconductor device according to another embodiment of the present invention. Figures 4A to 4C are schematic cross-sectional views of a method for manufacturing a semiconductor device according to another embodiment of the present invention.

10: Semiconductor devices

100’: Stack structure/character line structure

102: Base

110: Tunneling dielectric layer

120: floating gate

130: Gate dielectric layer

140: Control gate

142: First control gate

144: Second control gate

150: First mask layer

160”: Second mask layer

170: Protective layer

180: Insulation structure

182: Top cover

184: Interlayer dielectric layer

AG: Air gap

C: Chamfer structure

D1: First direction

D2: Second direction

W1,W2: Maximum width

Claims (18)

A semiconductor device comprises: A plurality of word line structures disposed on a substrate, wherein each of the plurality of word line structures comprises: A floating gate; A control gate disposed on the floating gate; A first mask layer disposed on the control gate, wherein the material of the first mask layer comprises nitride; and A second mask layer disposed on the first mask layer, wherein the material of the second mask layer comprises a semiconductor; and An insulating structure disposed on the plurality of word line structures and covering the top surface and sidewalls of the second mask layer of the plurality of word line structures, wherein there is an air gap between adjacent plurality of word line structures. A semiconductor device as described in claim 1, wherein the insulating structure also extends to the side walls of the plurality of word line structures. A semiconductor device as described in claim 2, wherein the insulating structure further extends from the sidewalls of the plurality of word line structures to the substrate between adjacent plurality of word line structures. A semiconductor device as described in claim 3, wherein the air gap is surrounded by the insulating structure. A semiconductor device as described in claim 1, wherein each of the plurality of word line structures further includes a protection layer, wherein the protection layer partially covers a side wall of the control gate. A semiconductor device as described in claim 5, wherein the control gate comprises: a first control gate, wherein the material of the first control gate comprises polysilicon; and a second control gate disposed on the first control gate, wherein the material of the second control gate comprises metal, wherein the protective layer is located on the sidewall of the first control gate. A semiconductor device as described in claim 6, wherein the second control gate directly contacts the air gap. A semiconductor device as described in claim 1, wherein the second mask layer has a chamfered structure. A semiconductor device as described in claim 1, wherein the maximum width of the second mask layer is greater than the maximum width of the first mask layer. A semiconductor device as described in claim 1, wherein the side walls of the second mask layer are substantially aligned with the side walls of the first mask layer. A method for manufacturing a semiconductor device, comprising: forming a plurality of stacked structures separated from each other on a substrate, wherein each of the plurality of stacked structures comprises: a floating gate; a control gate disposed on the floating gate; a first mask layer disposed on the control gate, wherein the material of the first mask layer comprises nitride; and a second mask material layer disposed on the first mask layer, wherein the material of the second mask material layer comprises semiconductor; performing an epitaxial growth process on the second mask material layer; performing an oxidation process on the second mask material layer subjected to the epitaxial growth process, wherein the periphery of the second mask material layer is oxidized to form a cap layer, and the unoxidized portion of the second mask material layer forms a second mask layer. A method for manufacturing a semiconductor device as described in claim 11, wherein after the second mask material layer that has undergone the epitaxial growth process is subjected to the oxidation process, the top cover layers of the adjacent multiple stacking structures are laterally connected to each other, so that the space between the adjacent multiple stacking structures is sealed to form an air gap. The method for manufacturing a semiconductor device as described in claim 11, wherein before the oxidation process is performed on the second mask material layer that has undergone the epitaxial growth process, the second mask material layers of the plurality of adjacent stacked structures are connected to each other. A method for manufacturing a semiconductor device as described in claim 11, wherein the shortest distance between the top cover layers of the plurality of adjacent stack structures is smaller than the shortest distance between the control gates of the plurality of adjacent stack structures. The method for manufacturing a semiconductor device as described in claim 11 further includes: Forming an interlayer dielectric layer on the top cover layer, wherein the interlayer dielectric layer is laterally connected above the multiple stacked structures. A method for manufacturing a semiconductor device as described in claim 15, wherein the interlayer dielectric layer is formed on the sidewall of the stacked structure through the gaps between the top cap layers of the adjacent stacked structures. A method for manufacturing a semiconductor device as described in claim 16, wherein the interlayer dielectric layer seals the gap between the top cover layers of the plurality of stacked structures and forms an air gap between adjacent stacked structures. The method for manufacturing a semiconductor device as described in claim 11 further includes: Forming a protective layer on part of the side walls of the plurality of stacked structures through a plasma oxidation process.

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