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TWI869843B - Analog Digital Integrated System - Google Patents

Analog Digital Integrated System Download PDF

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TWI869843B
TWI869843B TW112116829A TW112116829A TWI869843B TW I869843 B TWI869843 B TW I869843B TW 112116829 A TW112116829 A TW 112116829A TW 112116829 A TW112116829 A TW 112116829A TW I869843 B TWI869843 B TW I869843B
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TW202445961A (en
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陳福元
李宇喬
王建民
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虹原科技股份有限公司
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Abstract

一種類比數位整合系統,係包含有一前饋電壓輸入器、一電壓補償器及一乘法器,該乘法器係由多個運算放大器及一解碼器所組成,用以將該前饋電壓輸入器輸入之第一輸入電位類比信號及該電壓補償器輸入之第二輸入電位類比信號,進行類比數位轉換並解碼後,取得一電位調整比例,並依據該電位調整比例對該第一輸入電位類比信號進行調整,以產生出一電流命令類比信號。An analog-digital integration system includes a feedforward voltage input device, a voltage compensator and a multiplier. The multiplier is composed of a plurality of operational amplifiers and a decoder. The multiplier is used to perform analog-to-digital conversion and decoding on a first input potential analog signal input by the feedforward voltage input device and a second input potential analog signal input by the voltage compensator, obtain a potential adjustment ratio, and adjust the first input potential analog signal according to the potential adjustment ratio to generate a current command analog signal.

Description

類比數位整合系統Analog Digital Integrated System

本發明是有關一種類比數位整合系統,特別是一種無需使用MCU(或DSP)且不需撰寫程式來執行數位功能之類比數位整合系統。The present invention relates to an analog digital integration system, in particular to an analog digital integration system that does not require the use of an MCU (or DSP) and does not require programming to execute digital functions.

一般的電源轉換器大多類比控制器或是數位控制器,但不論是皆會有一定的問題發生,以下針對類比控制器與數位控制器分別說明其問題。Most common power converters are either analog or digital controllers, but both types have certain problems. The following describes the problems of analog and digital controllers respectively.

類比控制器的電路設計會碰到問題如下: (1) 精確度差; (2) 功能太多,電路複雜; (3) 無法提供足夠的應用彈性; (4) 工程設計應用人員需要專業能力更強之工程師。 The circuit design of analog controllers may encounter the following problems: (1) Poor accuracy; (2) Too many functions and complex circuits; (3) Failure to provide sufficient application flexibility; (4) Engineering design application personnel need engineers with stronger professional capabilities.

數位控制器的應用與設計問題如下: (1) 成本高,一般要執行類比電路之動作,必須使用到高速運算之核心,如DSP等級; (2) 需要韌體人員之開發協助,同時類比應用之硬體人員協調開發; (3) 開發時程長,由於MCU/DSP都是低壓元件,如果應用於高壓大於5v以上,變成需要加入分壓元件電阻,同時避免干擾問題也要加入濾波電容,所以造成增加很多電阻電容。 The application and design issues of digital controllers are as follows: (1) High cost. Generally, to execute the actions of analog circuits, a high-speed computing core, such as DSP level, must be used; (2) Development assistance from firmware personnel is required, and the hardware personnel of analog applications need to coordinate the development; (3) The development process is long. Since MCU/DSP are both low-voltage components, if they are applied to high voltages greater than 5V, it becomes necessary to add voltage divider resistors. At the same time, to avoid interference problems, filter capacitors must also be added, resulting in a lot of additional resistors and capacitors.

因此不論是類比控制器或是數位控制器,皆由其缺點,但亦有其優點,以傳統PFC控制器來看,大多為類比設計,以設計應用的角度而言,適合大多數的工程師,尤其在調整補償器而言相當簡單容易。但近幾年由於網通相關產業發達,伺服器大量建置,造成對電源的要求越來越高,知名的外商紛紛提出數位化PFC來達成電源上的要求,也因此在電源控制的角色由類比轉為數位,幾乎所有設計工程師必須多一位韌體工程師協助完成控制上補償器的設定,無法由硬體工程師來完成。Therefore, both analog and digital controllers have their shortcomings, but also their advantages. From the perspective of traditional PFC controllers, most are analog designs. From the perspective of design application, they are suitable for most engineers, especially in terms of adjusting the compensator, which is quite simple and easy. However, in recent years, due to the development of network communication related industries and the large-scale construction of servers, the requirements for power supply have become higher and higher. Well-known foreign companies have proposed digital PFC to meet the power supply requirements. Therefore, the role of power control has changed from analog to digital. Almost all design engineers must have an additional firmware engineer to assist in completing the setting of the compensator on the control, which cannot be completed by hardware engineers.

進一步舉例說明控制器電路的特點與問題,由於主動式功率因數修正器,必須同時控制輸入電流與輸出電壓,而電流控制迴路的命令是由整流後的線電壓所決定,因此可以使轉換器的輸入阻抗呈現電阻性。而輸出電壓的控制是藉由改變電流命令的平均值大小來完成。To further illustrate the characteristics and problems of the controller circuit, an active power factor corrector must control both the input current and the output voltage, and the command of the current control loop is determined by the rectified line voltage, so the input impedance of the converter can be made resistive. The output voltage is controlled by changing the average value of the current command.

類比的乘法器將整流後的線電壓乘以電壓誤差放大器的輸出後,產生一個電流控制命令。也因此電流的控制命令與輸入電壓的形狀相同,同時其平均值代表輸出電壓的控制命令大小。The analog multiplier multiplies the rectified line voltage by the output of the voltage error amplifier to generate a current control command. Therefore, the current control command has the same shape as the input voltage, and its average value represents the output voltage control command size.

如第1圖所示,為主動式功率因數修正器(高功因交換式穩壓器31)所需要的基本控制器電路3,用以輸出功率至負載35,其中輸出電流乘法器的輸出稱之為Imo,而這個乘法器32的輸出即為輸入電流的控制命令。As shown in FIG. 1 , the basic controller circuit 3 required for the active power factor corrector (high power factor switching regulator 31) is used to output power to the load 35, wherein the output of the output current multiplier is called Imo, and the output of this multiplier 32 is the control command of the input current.

如第1圖所示,乘法器32的輸入端(輸入電壓整流後的電壓)是以電流的方式表示的,因為這就是UC3854/ML4812/CM6502S等等控制IC常用的基本概念。As shown in Figure 1, the input of the multiplier 32 (the voltage after the input voltage is rectified) is expressed in the form of current, because this is the basic concept commonly used in control ICs such as UC3854/ML4812/CM6502S.

除了乘法器32之外,還包括了平方器33與除法器34,這些電路主要的功能是將電壓誤差放大器的輸出除以輸入電壓的平均值取平方後的數值,最後得到的值再乘以整流後的電壓信號Iac,整流器輸出端經由一電阻接到乘法器的輸入端的電流Iac,為追蹤輸入電壓波形信號。In addition to the multiplier 32, it also includes a squarer 33 and a divider 34. The main function of these circuits is to divide the output of the voltage error amplifier by the average value of the input voltage and take the square of the value. The final value is multiplied by the rectified voltage signal Iac. The current Iac at the output of the rectifier is connected to the input of the multiplier via a resistor to track the input voltage waveform signal.

這個外加的電路將可使電壓回路的增益維持一個定值,沒有它的話電壓回路增益將會是平均輸入電壓的平方倍。輸入電壓的平均值稱為前饋電壓信號或是Vff,當前饋電壓信號被前饋到電壓回路增益時,此一數值提供了一個開回路的修正量,且這個值是需要取平方後用來作為電壓誤差放大器輸出電壓信號的除數。This additional circuit will keep the voltage loop gain constant. Without it, the voltage loop gain will be the square of the average input voltage. The average value of the input voltage is called the feedforward voltage signal or Vff. When the feedforward voltage signal is fed forward to the voltage loop gain, this value provides an open loop correction and this value needs to be squared and used as the divisor of the voltage error amplifier output voltage signal.

為了提高功因,電流命令必須緊緊追隨輸入電壓,假使電壓迴路頻寬太大,將造成輸入電流為了維持輸出電壓為定值,而嚴重失真。所以電壓迴路的頻寬必須小於輸入電源頻率,又基於暫態響應考量,電壓迴路頻寬應儘可能大。因此頻寬越接近電源頻率越好。而加上平均輸入電壓的平方目的是為保持電壓迴路增一為定值,而不隨平均輸入電壓而改變。此依特性另電壓誤差放大器傳送至負載的功率。In order to improve the power factor, the current command must closely follow the input voltage. If the voltage loop bandwidth is too large, the input current will be severely distorted in order to maintain the output voltage at a constant value. Therefore, the voltage loop bandwidth must be less than the input power frequency. Based on transient response considerations, the voltage loop bandwidth should be as large as possible. Therefore, the closer the bandwidth is to the power frequency, the better. The purpose of adding the square of the average input voltage is to keep the voltage loop constant without changing with the average input voltage. This characteristic controls the power delivered to the load by the voltage error amplifier.

而這一類傳統PFC控制電路,會產生以下問題: 1. 失真量大,一般為了動態響應造成乘法器的輸入端前饋電壓與電壓迴路補償漣波太大所造成。 2. 系統快速開關機時,乘法器之輸入端前饋電壓的信號變化無法同步造成乘法器輸出信號不正確進而使電流迴路追隨錯誤之電流,如此容易造成PFC主開關受損或炸毀。 3. 系統做市電快速高低壓變動時,乘法器之輸入端的信號變化無法同步造成乘法器輸出信號不正確進而使電流迴路追隨錯誤之電流命令,如此容易造成PFC主開關受損或炸毀。 4. 負載變動時,電壓迴路的信號因考慮電流失真把頻寬做的很小造成負載變化時輸出電壓變動會時間延遲才開始改變乘法器的輸入,因此輸出電壓會掉到太低使的下級電路無法穩壓。 5. 系統驗證時 SAGING時電流因迴授電路追隨錯誤電流命令變化造成電流過沖與震盪可能會造成PFC主開關炸毀。 This type of traditional PFC control circuit will produce the following problems: 1. Large distortion, generally caused by excessive ripple in the multiplier input feedforward voltage and voltage loop compensation for dynamic response. 2. When the system is turned on and off quickly, the signal change of the multiplier input feedforward voltage cannot be synchronized, resulting in incorrect multiplier output signal and causing the current loop to follow the wrong current, which can easily cause damage or explosion of the PFC main switch. 3. When the system is in a fast high or low voltage change, the signal change at the input of the multiplier cannot be synchronized, resulting in an incorrect output signal of the multiplier, which in turn causes the current loop to follow the wrong current command, which can easily cause damage or explosion of the PFC main switch. 4. When the load changes, the signal of the voltage loop has a very small bandwidth due to current distortion, causing the output voltage to change with a delay before the multiplier input is changed when the load changes. Therefore, the output voltage will drop too low, making it impossible for the downstream circuit to regulate the voltage. 5. During system verification, the current overshoot and oscillation caused by the feedback circuit following the wrong current command change during SAGING may cause the PFC main switch to explode.

相較於習用的傳統PFC控制電路,本案開發出類比數位混合型PFC控制器,利用數位ADC讀取輸入電壓信號與電壓迴路輸出信號,來決定電流命令的大小,所以可以看成整個數位核心為一個數位乘法器,本案利用數位高速計算的優勢,可以立即產生幾乎無失真之電流命令與CS比較,然後DAC輸出與內部之RAMP比較產生所需要的PWM,所以整體迴路才能達到低失真的高功率因數修正,因此,本案應為一最佳解決方案。Compared with the traditional PFC control circuit, this case develops an analog-digital hybrid PFC controller, which uses a digital ADC to read the input voltage signal and the voltage loop output signal to determine the size of the current command, so the entire digital core can be regarded as a digital multiplier. This case uses the advantages of digital high-speed calculation to immediately generate an almost distortion-free current command and compare it with CS, and then compare the DAC output with the internal RAMP to generate the required PWM, so that the overall loop can achieve low-distortion high power factor correction. Therefore, this case should be an optimal solution.

本發明類比數位整合系統,係至少包含:一前饋電壓輸入器,用以產生一第一輸入電位類比信號;一電壓補償器,用以產生一第二輸入電位類比信號;一乘法器,係至少包含有一第一輸入轉換單元,係與該前饋電壓輸入器電性連接,用以將該第一輸入電位類比信號轉換為一第一輸入電位數位信號;一第二輸入轉換單元,係與該電壓補償器電性連接,用以將該第二輸入電位類比信號轉換為一第二輸入電位數位信號;一數位信號解碼單元,係與該第一輸入轉換單元及該第二輸入轉換單元電性連接,用以依據該第一輸入電位類比信號及該第二輸入電位類比信號產生出一電位調整比例;以及一輸出電位調整單元,係與該數位信號解碼單元及該前饋電壓輸入器電性連接,用以依據該數位信號解碼單元產生之電位調整比例對該第一輸入電位類比信號進行調整,以產生出一電流命令類比信號。The analog-digital integration system of the present invention at least comprises: a feedforward voltage input device for generating a first input potential analog signal; a voltage compensator for generating a second input potential analog signal; a multiplier at least comprising a first input conversion unit electrically connected to the feedforward voltage input device for converting the first input potential analog signal into a first input potential digital signal; a second input conversion unit electrically connected to the voltage compensator for converting the second input potential analog signal into a first input potential digital signal. Two input potential digital signals; a digital signal decoding unit electrically connected to the first input conversion unit and the second input conversion unit, for generating a potential adjustment ratio according to the first input potential analog signal and the second input potential analog signal; and an output potential adjustment unit electrically connected to the digital signal decoding unit and the forward feed voltage input device, for adjusting the first input potential analog signal according to the potential adjustment ratio generated by the digital signal decoding unit to generate a current command analog signal.

更具體的說,所述第一輸入轉換單元、該第二輸入轉換單元及該輸出電位調整單元係為一運算放大器。More specifically, the first input conversion unit, the second input conversion unit and the output potential adjustment unit are an operational amplifier.

更具體的說,所述數位信號解碼單元係為一解碼器。More specifically, the digital signal decoding unit is a decoder.

更具體的說,所述第一輸入電位類比信號係為一參考電壓,該第二輸入電位類比信號係為一調節電壓,該調節電壓依據一輸出功率大小進行改變,而該參考電壓之改變大小用以定義該電位調整比例大小。More specifically, the first input potential analog signal is a reference voltage, and the second input potential analog signal is an adjustment voltage. The adjustment voltage changes according to an output power, and the change in the reference voltage is used to define the potential adjustment ratio.

有關於本發明其他技術內容、特點與功效,在以下配合參考圖式之較佳實施例的詳細說明中,將可清楚的呈現。Other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the drawings.

請參閱第2圖,為本發明類比數位整合系統之架構示意圖,其中類比數位整合系統係至少包含有一前饋電壓輸入器11、一電壓補償器12及一乘法器13。Please refer to FIG. 2 , which is a schematic diagram of the structure of the analog digital integration system of the present invention, wherein the analog digital integration system at least includes a feedforward voltage input device 11 , a voltage compensator 12 and a multiplier 13 .

本案類比數位整合系統用以串接一電源轉換電路2(例如功率因數修正電路(power factor correction, PFC)或其他類型的電源轉換電路),並能夠依據該電源轉換電路之類型改變該類比數位整合系統之架構。The analog-digital integration system of the present invention is used to connect in series a power conversion circuit 2 (such as a power factor correction circuit (PFC) or other types of power conversion circuits), and can change the structure of the analog-digital integration system according to the type of the power conversion circuit.

該前饋電壓輸入器11係與該電源轉換電路2電性連接,用以產生一第一輸入電位類比信號。The feedforward voltage input device 11 is electrically connected to the power conversion circuit 2 to generate a first input potential analog signal.

該電壓補償器12係與該電源轉換電路2電性連接,用以產生一第二輸入電位類比信號。The voltage compensator 12 is electrically connected to the power conversion circuit 2 to generate a second input potential analog signal.

該乘法器13係至少包含有一第一輸入轉換單元131、一第二輸入轉換單元132、一數位信號解碼單元133、一輸出電位調整單元134。The multiplier 13 at least includes a first input conversion unit 131 , a second input conversion unit 132 , a digital signal decoding unit 133 , and an output potential adjustment unit 134 .

該第一輸入轉換單元131係為一運算放大器(Analog-to-Digital Converter , ADC),該第一輸入轉換單元131係與該前饋電壓輸入器11電性連接,用以將該第一輸入電位類比信號轉換為一第一輸入電位數位信號。The first input conversion unit 131 is an operational amplifier (Analog-to-Digital Converter, ADC). The first input conversion unit 131 is electrically connected to the feedforward voltage input device 11 to convert the first input potential analog signal into a first input potential digital signal.

該第二輸入轉換單元132係為一運算放大器(Analog to Digital Converter , ADC),該第二輸入轉換單元132係與該電壓補償器12電性連接,用以將該第二輸入電位類比信號轉換為一第二輸入電位數位信號。The second input conversion unit 132 is an operational amplifier (Analog to Digital Converter, ADC). The second input conversion unit 132 is electrically connected to the voltage compensator 12 to convert the second input potential analog signal into a second input potential digital signal.

該數位信號解碼單元133係為一解碼器,該數位信號解碼單元133係與該第一輸入轉換單元131及該第二輸入轉換單元132電性連接,該數位信號解碼單元133用以依據該第一輸入電位類比信號及該第二輸入電位類比信號產生出一電位調整比例。The digital signal decoding unit 133 is a decoder. The digital signal decoding unit 133 is electrically connected to the first input conversion unit 131 and the second input conversion unit 132. The digital signal decoding unit 133 is used to generate a potential adjustment ratio according to the first input potential analog signal and the second input potential analog signal.

該輸出電位調整單元134係為一運算放大器(Digital to Analog Converter , DAC),該輸出電位調整單元134係與該數位信號解碼單元133及該前饋電壓輸入器11電性連接,用以依據該數位信號解碼單元133產生之電位調整比例對該第一輸入電位類比信號進行調整,以產生出一電流命令類比信號。The output potential adjustment unit 134 is an operational amplifier (Digital to Analog Converter, DAC), and the output potential adjustment unit 134 is electrically connected to the digital signal decoding unit 133 and the forward feed voltage input device 11, and is used to adjust the first input potential analog signal according to the potential adjustment ratio generated by the digital signal decoding unit 133 to generate a current command analog signal.

該第一輸入電位類比信號係為一參考電壓,該第二輸入電位類比信號係為一調節電壓,該調節電壓依據一輸出功率大小進行改變,而該參考電壓之改變大小用以定義該電位調整比例大小。The first input potential analog signal is a reference voltage, and the second input potential analog signal is an adjustment voltage. The adjustment voltage changes according to an output power, and the change of the reference voltage is used to define the potential adjustment ratio.

如第3A圖所示,係為一功率因數修正電路(power factor correction, PFC)的電源轉換電路示意圖,本案以PFC電路做為舉例,而第3B-1、3B-2、3B-2及3B-4圖則是本案類比數位整合系統之電路實施示意圖。As shown in FIG. 3A, it is a schematic diagram of a power conversion circuit of a power factor correction (PFC) circuit. This case uses the PFC circuit as an example, and FIGS. 3B-1, 3B-2, 3B-3 and 3B-4 are schematic diagrams of the circuit implementation of the analog digital integration system of this case.

如第3A圖所示,其中框選的A點係串接於該前饋電壓輸入器11的分壓電路,該前饋電壓輸入器11能夠透過一運算放大器做為緩衝器使用,用來解決負載效應,但本案亦能夠不使用緩衝器,而直接將A點電壓分壓後輸入,而該第一輸入轉換單元131能夠進行取樣,以取得第一輸入電位類比信號。As shown in FIG. 3A , the framed point A is connected in series to the voltage divider circuit of the feedforward voltage input 11. The feedforward voltage input 11 can be used as a buffer through an operational amplifier to solve the load effect. However, the present invention can also not use a buffer and directly divide the voltage at point A for input, and the first input conversion unit 131 can perform sampling to obtain a first input potential analog signal.

如第3A圖所示,其中框選的B點係串接於該電壓補償器12的分壓電路,再透過一運算放大器做為電壓補償器使用,用以決定輸出功率大小,做為調節功率之用;而該第二輸入轉換單元132能夠進行取樣,以取得並輸出第二輸入電位類比信號。As shown in FIG. 3A , the boxed point B is connected in series to the voltage divider circuit of the voltage compensator 12 and then used as a voltage compensator through an operational amplifier to determine the output power for power regulation. The second input conversion unit 132 can perform sampling to obtain and output a second input potential analog signal.

如第3A圖所示,其中框選的C點係串接於該電流補償器14,而輸出電位調整單元134輸出之電流命令類比信號則是用來控制該電流補償器14,並輸出至該PWM產生器來輸出一PWM信號給該電源轉換電路2的PWM接點處。As shown in FIG. 3A , the boxed point C is connected in series to the current compensator 14 , and the current command analog signal output by the output potential adjustment unit 134 is used to control the current compensator 14 , and is output to the PWM generator to output a PWM signal to the PWM contact of the power conversion circuit 2 .

如第3B-3圖所示,該時序控制器15是用以產生第一輸入轉換單元131(ADC1)、第二輸入轉換單元132(ADC2)、數位信號解碼單元133(DECODER1)、保護邏輯器16(DECODER2)及PWM產生器17所需要的時序。As shown in FIG. 3B-3 , the timing controller 15 is used to generate the timing required by the first input conversion unit 131 (ADC1), the second input conversion unit 132 (ADC2), the digital signal decoding unit 133 (DECODER1), the protection logic 16 (DECODER2) and the PWM generator 17.

如第3B-3圖所示,該保護邏輯器16是一種解碼器,用以來保護邏輯並判斷異常。As shown in FIG. 3B-3, the protection logic 16 is a decoder used to protect logic and judge abnormalities.

如第1圖及[0010]描述可知,傳統的控制器電路,是將放大器的輸出(第二輸入電位類比信號)除以輸入電壓的平均值取平方後的數值(輸入電壓的平均值稱之為前饋電壓信號或是Vff),最後得到的值再乘以整流後的電壓信號Iac,整流器輸出端經由一電阻接到乘法器的輸入端的電流Iac(第一輸入電位類比信號),為追蹤輸入電壓波形信號。As shown in Figure 1 and [0010], the traditional controller circuit divides the output of the amplifier (the second input potential analog signal) by the square of the average value of the input voltage (the average value of the input voltage is called the feedforward voltage signal or Vff), and then multiplies the final value by the rectified voltage signal Iac. The current Iac (the first input potential analog signal) at the output of the rectifier is connected to the input of the multiplier via a resistor to track the input voltage waveform signal.

由於整流後的電壓信號與輸入電壓的平均值取平方後的數值具有一定關聯性,故將「整流後的電壓信號」除以「輸入電壓的平均值取平方後的數值」定義為一X值。Since the rectified voltage signal and the value obtained by taking the square of the average value of the input voltage have a certain correlation, the "rectified voltage signal" divided by the "value obtained by taking the square of the average value of the input voltage" is defined as an X value.

因此,若要取得電流命令類比信號(Imo),傳統的方式就如上所述,如第1圖所示,例如當a點(整流後的電壓信號)為100V時,b點(放大器的輸出)為5V,c點(輸入電壓的平均值)則是(100 2),因此最後求得的電流則是0.05(0.01x5)。 Therefore, if you want to obtain the current command analog signal (Imo), the traditional method is as described above, as shown in Figure 1. For example, when point a (the rectified voltage signal) is 100V, point b (the output of the amplifier) is 5V, and point c (the average value of the input voltage) is (100 2 ), the final current obtained is 0.05 (0.01x5).

若是當a點為200V時,b點為5V,Vff則是(200 2),因此最後求得的電流則是0.025(0.005x5)。 If point a is 200V and point b is 5V, Vff is (200 2 ), so the final current is 0.025 (0.005x5).

然而上述這種傳統方式如前所述,具有很大問題,為了能夠及時反應,本案才提出以電位調整比例邏輯的概念來取代傳統的控制機制,由於市電會一直變化,故a點與輸入電壓平均值取平方後的比例則會改變,但由於a點與輸入電壓的平均值平方具有相關聯性,因此a點也就會與X值(「a點」除以「輸入電壓的平均值平方」)有相關聯性,故能夠將a點與X值的關係進行列表,以做為一電位調整比例邏輯表使用。However, as mentioned above, the traditional method has a big problem. In order to respond in time, this case proposes to replace the traditional control mechanism with the concept of potential adjustment ratio logic. Since the mains electricity will always change, the ratio of point a to the square of the average value of the input voltage will change. However, since point a is related to the square of the average value of the input voltage, point a will also be related to the X value ("point a" divided by "the square of the average value of the input voltage"). Therefore, the relationship between point a and the X value can be tabulated and used as a potential adjustment ratio logic table.

該電位調整比例邏輯表係內建於該數位信號解碼單元133內,因此當a點電壓一改變,則能夠依據a點信號進行查表取得要改變的比例。The potential adjustment ratio logic table is built into the digital signal decoding unit 133, so when the voltage at point a changes, the ratio to be changed can be obtained by looking up the table based on the signal at point a.

另外,當取得a點與X值的關係後,更能夠將b點加入擴充該電位調整比例邏輯表,以列出多種可能的組合,因此當取得a點與b點後,則能夠依據該a點與b點找出對應的電位調整比例,再由該輸出電位調整單元134依據該電位調整比例對該第一輸入電位類比信號進行調整,以產生出一電流命令類比信號。In addition, after obtaining the relationship between point a and the X value, point b can be added to expand the potential adjustment ratio logic table to list multiple possible combinations. Therefore, after obtaining point a and point b, the corresponding potential adjustment ratio can be found according to point a and point b, and then the output potential adjustment unit 134 adjusts the first input potential analog signal according to the potential adjustment ratio to generate a current command analog signal.

本發明所提供之類比數位整合系統,與其他習用技術相互比較時,其優點如下: 1. 本發明使用了多個運算放大器、一解碼器組成一乘法器,其中解碼器依據兩個位於輸入端之運算放大器的類比信號來決定控制機制的要求,並在透過位於輸出端之運算放大器來進行控制後續迴路。 2. 本發明之架構,將可以減少數位控制的複雜度,只要依據設計之需求,修改解碼器的內容便能完成一類比與數位混合控制之架構。 3. 本發明相對於使用高階MCU與設計其運算程式,本案直接設計解碼器內的解碼邏輯,故其設計非常簡便,同時能夠大幅節省成本。 4. 本發明針對不同的電源轉換電路,僅需更改解碼器內部的解碼邏輯,即可實施應用,故本發明之結構能夠適用於不同類型的電源轉換電路使用。 5. 本案利用數位控制的優勢,來解決傳統PFC常見之問題,而數位化的優勢如下: (1) 高速取樣,降低電流THD,提高動態響應。 (2) 精準的邏輯判斷: 系統快速開關機,市電快速高低壓變動。 (3) 穩定的時間與時序控制: 解決SAGING。 6. 本案具有類比控制之優點, 由於使用硬體工程簡易設定來採用類比補償器,因此不需要韌體人員協助,同時達到比數位化PFC更好的特性與更優的成本與更短的開發時間。 7. 一般傳統PFC的失真來源有輸入端的橋式整流器、乘法電路的輸出與以及輸出與前饋電壓中的漣波等;習知技術相較於本案,本案採用數位處理的高速,乘法電路的輸出與以及輸出的漣波,都可以將連波所造成乘法器的輸出失真降低到最低,同時電流迴路的放大器採用低於+/-1mV的轉導放大器,更進一步將失真降至2%,使的本案的特性可以超越目前常用於PFC的控制DSP(例如:UCD3138等) 。 8. 一般傳統PFC的失真來源有輸入端的橋式整流器、乘法電路的輸出與以及輸出與前饋電壓中的漣波等,為了解決失真問題,只能在輸出電壓與前饋電壓的迴路變慢,這樣卻造成輸入電壓與輸出電壓在動態響應時就反應不及;習知技術相較於本案,本案採用數位處理的高速特性同時結合多段式轉導放大器,所以無須傳統的前饋電壓便可產生乘法器輸出,並且在輸出電壓端可以利用數位取樣達成快速的動態響應。 9. 一般傳統PFC的失真來源有輸入端的橋式整流器、乘法電路的輸出與以及輸出與前饋電壓中的漣波等,為了解決失真問題,只能在輸出電壓與前饋電壓的迴路變慢,這樣卻造成輸入電壓與輸出電壓在動態響應時就反應不及;習知技術相較於本案,本案採用數位處理的高速特性同時結合多段式轉導放大器,所以無須傳統的前饋電壓便可產生乘法器輸出,這表示由於高速數位取樣可以立即反應輸入電壓的變化進而立即改變乘法器輸出,所以就避免了輸入電流因乘法器輸出錯誤造成電流異常進而造成PFC MOSFET燒毀。 10. 一般傳統PFC有兩種習知控制方式(CRM(PEAK CURRENT MODE+FM)及CCM(AVERAGE CURRENT MODE+FIX FREQUENCY)),而習知技術相較於本案,本案結合兩種控制合在一起,只要適當的設計PFC電感便可以提高效率同時兼顧電流失真。採用多模式操作便可以把傳統為提高PFC效率採用SIC DIODE與外商的COOLMOSFET改為一般的PFC二極體與台製的MOSFET,即可做到高效率低成本之設計。 The analog-digital integration system provided by the present invention has the following advantages when compared with other conventional technologies: 1. The present invention uses multiple operational amplifiers and a decoder to form a multiplier, wherein the decoder determines the requirements of the control mechanism based on the analog signals of the two operational amplifiers at the input end, and controls the subsequent loop through the operational amplifier at the output end. 2. The architecture of the present invention can reduce the complexity of digital control. As long as the content of the decoder is modified according to the design requirements, an analog and digital hybrid control architecture can be completed. 3. Compared with using a high-end MCU and designing its operation program, the present invention directly designs the decoding logic in the decoder, so its design is very simple and can greatly save costs. 4. The present invention can be applied to different power conversion circuits by simply changing the decoding logic inside the decoder. Therefore, the structure of the present invention can be applied to different types of power conversion circuits. 5. This case uses the advantages of digital control to solve the common problems of traditional PFC. The advantages of digitization are as follows: (1) High-speed sampling, reducing current THD, and improving dynamic response. (2) Accurate logic judgment: fast system startup and shutdown, fast high and low voltage changes of the mains. (3) Stable time and timing control: solve SAGING. 6. This solution has the advantages of analog control. Since the analog compensator is adopted by using simple hardware engineering settings, no firmware personnel assistance is required. At the same time, it achieves better characteristics, better costs and shorter development time than digital PFC. 7. The distortion sources of traditional PFC include the bridge rectifier at the input, the output of the multiplication circuit, and the ripples in the output and the forward feed voltage. Compared with the known technology, this case uses high-speed digital processing, the output of the multiplication circuit and the ripples in the output, which can reduce the output distortion of the multiplier caused by the continuous wave to the minimum. At the same time, the amplifier of the current loop uses a transconductance amplifier with a voltage lower than +/-1mV, which further reduces the distortion to 2%, making the characteristics of this case surpass the control DSP commonly used in PFC (such as: UCD3138, etc.). 8. The distortion sources of traditional PFC generally include the bridge rectifier at the input, the output of the multiplication circuit, and the ripples in the output and feedforward voltage. To solve the distortion problem, the output voltage and feedforward voltage loop can only be slowed down, which causes the input voltage and output voltage to fail to respond in dynamic response. Compared with the known technology, this case adopts the high-speed characteristics of digital processing and combines a multi-stage transconductance amplifier, so the multiplier output can be generated without the traditional feedforward voltage, and digital sampling can be used at the output voltage to achieve fast dynamic response. 9. The distortion sources of traditional PFC generally include the bridge rectifier at the input, the output of the multiplication circuit, and the ripples in the output and the feedforward voltage. To solve the distortion problem, the output voltage and the feedforward voltage loop can only be slowed down, which causes the input voltage and the output voltage to fail to respond in a dynamic response. Compared with the known technology, this case adopts the high-speed characteristics of digital processing and combines a multi-stage transconductance amplifier, so the multiplier output can be generated without the traditional feedforward voltage. This means that since high-speed digital sampling can immediately respond to changes in the input voltage and then immediately change the multiplier output, it avoids the input current being abnormal due to the multiplier output error, which in turn causes the PFC. MOSFET burns out. 10. There are two conventional PFC control methods (CRM (PEAK CURRENT MODE + FM) and CCM (AVERAGE CURRENT MODE + FIX FREQUENCY)). Compared with conventional PFC control methods, this case combines the two control methods. As long as the PFC inductor is properly designed, the efficiency can be improved while taking into account the current distortion. The use of multi-mode operation can change the traditional use of SIC DIODE and foreign COOLMOSFET to general PFC diodes and Taiwan-made MOSFETs to achieve high efficiency and low cost design.

本發明已透過上述之實施例揭露如上,然其並非用以限定本發明,任何熟悉此一技術領域具有通常知識者,在瞭解本發明前述的技術特徵及實施例,並在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之專利保護範圍須視本說明書所附之請求項所界定者為準。The present invention has been disclosed through the above-mentioned embodiments, but they are not used to limit the present invention. Anyone familiar with this technical field and having common knowledge can make some changes and modifications without departing from the spirit and scope of the present invention after understanding the above-mentioned technical features and embodiments of the present invention. Therefore, the scope of patent protection of the present invention shall be determined by the claim items attached to this specification.

11: 前饋電壓輸入器 12: 電壓補償器 13: 乘法器 131: 第一輸入轉換單元 132: 第二輸入轉換單元 133: 數位信號解碼單元 134: 輸出電位調整單元 14: 電流補償器 15: 時序控制器 16: 保護邏輯器 17: PWM產生器 2: 電源轉換電路 3: 基本控制器電路 31: 高功因交換式穩壓器 32: 乘法器 33: 平方器 34: 除法器 35: 負載 11: Feedforward voltage input 12: Voltage compensator 13: Multiplier 131: First input conversion unit 132: Second input conversion unit 133: Digital signal decoding unit 134: Output potential adjustment unit 14: Current compensator 15: Timing controller 16: Protection logic 17: PWM generator 2: Power conversion circuit 3: Basic controller circuit 31: High power factor switching regulator 32: Multiplier 33: Squarer 34: Divider 35: Load

[第1圖] 係為習用PFC之基本控制器電路之電路示意圖。 [第2圖] 係本發明類比數位整合系統之架構示意圖。 [第3A圖] 係本發明類比數位整合系統之PFC電路示意圖。 [第3B-1圖] 係本發明類比數位整合系統之部份電路實施示意圖。 [第3B-2圖] 係本發明類比數位整合系統之部份電路實施示意圖。 [第3B-3圖] 係本發明類比數位整合系統之部份電路實施示意圖。 [第3B-4圖] 係本發明類比數位整合系統之部份電路實施示意圖。 [Figure 1] is a circuit diagram of a basic controller circuit for conventional PFC. [Figure 2] is a schematic diagram of the architecture of the analog-digital integration system of the present invention. [Figure 3A] is a schematic diagram of the PFC circuit of the analog-digital integration system of the present invention. [Figure 3B-1] is a schematic diagram of a partial circuit implementation of the analog-digital integration system of the present invention. [Figure 3B-2] is a schematic diagram of a partial circuit implementation of the analog-digital integration system of the present invention. [Figure 3B-3] is a schematic diagram of a partial circuit implementation of the analog-digital integration system of the present invention. [Figure 3B-4] is a schematic diagram of a partial circuit implementation of the analog-digital integration system of the present invention.

11: 前饋電壓輸入器 12: 電壓補償器 13: 乘法器 131: 第一輸入轉換單元 132: 第二輸入轉換單元 133: 數位信號解碼單元 134: 輸出電位調整單元 2: 電源轉換電路 11: Feedforward voltage input 12: Voltage compensator 13: Multiplier 131: First input conversion unit 132: Second input conversion unit 133: Digital signal decoding unit 134: Output potential adjustment unit 2: Power conversion circuit

Claims (4)

一種類比數位整合系統,係至少包含: 一前饋電壓輸入器,用以產生一第一輸入電位類比信號; 一電壓補償器,用以產生一第二輸入電位類比信號; 一乘法器,係至少包含有: 一第一輸入轉換單元,係與該前饋電壓輸入器電性連接,用以將該第一輸入電位類比信號轉換為一第一輸入電位數位信號; 一第二輸入轉換單元,係與該電壓補償器電性連接,用以將該第二輸入電位類比信號轉換為一第二輸入電位數位信號; 一數位信號解碼單元,係與該第一輸入轉換單元及該第二輸入轉換單元電性連接,用以依據該第一輸入電位類比信號及該第二輸入電位類比信號產生出一電位調整比例;以及 一輸出電位調整單元,係與該數位信號解碼單元及該前饋電壓輸入器電性連接,用以依據該數位信號解碼單元產生之電位調整比例對該第一輸入電位類比信號進行調整,以產生出一電流命令類比信號。 An analog-digital integration system at least comprises: A feedforward voltage input device for generating a first input potential analog signal; A voltage compensator for generating a second input potential analog signal; A multiplier at least comprises: A first input conversion unit electrically connected to the feedforward voltage input device for converting the first input potential analog signal into a first input potential digital signal; A second input conversion unit electrically connected to the voltage compensator for converting the second input potential analog signal into a second input potential digital signal; A digital signal decoding unit is electrically connected to the first input conversion unit and the second input conversion unit to generate a potential adjustment ratio according to the first input potential analog signal and the second input potential analog signal; and an output potential adjustment unit is electrically connected to the digital signal decoding unit and the feedforward voltage input device to adjust the first input potential analog signal according to the potential adjustment ratio generated by the digital signal decoding unit to generate a current command analog signal. 如請求項1所述之類比數位整合系統,其中該第一輸入轉換單元、該第二輸入轉換單元及該輸出電位調整單元係為一運算放大器。The analog-digital integration system as described in claim 1, wherein the first input conversion unit, the second input conversion unit and the output potential adjustment unit are an operational amplifier. 如請求項1所述之類比數位整合系統,其中該數位信號解碼單元係為一解碼器。An analog-digital integration system as described in claim 1, wherein the digital signal decoding unit is a decoder. 如請求項1所述之類比數位整合系統,其中該第一輸入電位類比信號係為一參考電壓,該第二輸入電位類比信號係為一調節電壓,該調節電壓依據一輸出功率大小進行改變,而該參考電壓之改變大小用以定義該電位調整比例大小。An analog-digital integration system as described in claim 1, wherein the first input potential analog signal is a reference voltage, the second input potential analog signal is an adjustment voltage, the adjustment voltage changes according to an output power, and the change in the reference voltage is used to define the potential adjustment ratio.
TW112116829A 2023-05-05 2023-05-05 Analog Digital Integrated System TWI869843B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6262901B1 (en) * 2000-09-29 2001-07-17 Anastastios V. Simopoulos Adjustable DC-to-DC converter with synchronous rectification and digital current sharing
TW201407945A (en) * 2012-08-06 2014-02-16 Peter Oaklander Noise resistant regulator
TW202121162A (en) * 2019-09-27 2021-06-01 美商應用材料股份有限公司 Successive bit-ordered binary-weighted multiplier-accumulator
TW202308328A (en) * 2021-07-26 2023-02-16 美商高通公司 Analog-to-digital conversion

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6262901B1 (en) * 2000-09-29 2001-07-17 Anastastios V. Simopoulos Adjustable DC-to-DC converter with synchronous rectification and digital current sharing
TW201407945A (en) * 2012-08-06 2014-02-16 Peter Oaklander Noise resistant regulator
TW202121162A (en) * 2019-09-27 2021-06-01 美商應用材料股份有限公司 Successive bit-ordered binary-weighted multiplier-accumulator
TW202308328A (en) * 2021-07-26 2023-02-16 美商高通公司 Analog-to-digital conversion

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