TWI869112B - Jtag standard pin detection system - Google Patents

Abstract

A JTAG standard pin detection system is provided. Different to-be-tested series chains are formed by to-be-tested slots which are electrically connected to each other or different riser card series chains are formed by riser cards which are electrically connected to each other through first JTAG input interface and first JTAG output interface or second JTAG input interface and second JTAG output interface individually. Test signals in JTAG format are provided to correspondence different to-be-tested series chains or different riser card series chains by TAP controller and then JTAG standard pins are tested by test card. Therefore, the efficiency of providing JTAG standard pins test for multiple to-be-tested slots on different to-be-tested boards by testing machine may be achieved.

Description

JTAG Standard Pin Test System

A test system, in particular a JTAG standard pin test system.

The existing method for testing multiple slots to be tested on a board to be tested is to insert a corresponding test card into each slot to be tested, and then connect the test cards in series to perform a JTAG standard pin test.

However, the existing testing method is only suitable for testing multiple test slots of the same test board. That is, the number of test slots, configuration positions, etc. of different test boards are different, and the number of test cards used and the way the test cards are connected in series are also different. Therefore, it is impossible to use the same test machine to test multiple test slots of different test boards.

In summary, it can be seen that the problem that the test machine can only provide multiple test slots on the same test board for JTAG standard pin testing has long existed in the prior art. Therefore, it is necessary to propose improved technical means to solve this problem.

In view of the problem that the prior art has a test machine that can only provide multiple test slots on the same test board for JTAG standard pin testing, the present invention discloses a JTAG standard pin testing system, wherein: the first embodiment of the JTAG standard pin testing system disclosed in the present invention includes: a test board, multiple adapter cards, multiple test cards, a test access port (TAP) controller, and a test data generating device.

The board to be tested has multiple slots to be tested, and the multiple slots to be tested are electrically connected to each other to form different serial links to be tested.

Each adapter card has an adapter card plug-in interface, an adapter card gold finger interface, a first JTAG input interface, a first JTAG output interface, a second JTAG input interface, and a second JTAG output interface. The test data input (TDI) pins of the adapter card plug-in interface, the adapter card gold finger interface, the first JTAG input interface, the first JTAG output interface, the second JTAG input interface, and the second JTAG output interface are electrically connected to each other, the test data output (TDO) pins are electrically connected to each other, the test clock (TCK) pins are electrically connected to each other, the test mode select (TMS) pins are electrically connected to each other, and the test reset (TRST) pins are electrically connected to each other.

The adapter card gold finger interface of each adapter card is correspondingly plugged into each slot to be tested, so that the correspondingly plugged adapter card gold finger interface and each TDI pin of the slot to be tested are electrically connected to each other, each TDO pin is electrically connected to each other, each TCK pin is electrically connected to each other, each TMS pin is electrically connected to each other, and each TRST pin is electrically connected to each other.

Each test card has a boundary scanning component, a JTAG input interface, a JTAG output interface, and a gold finger interface. The TDI pins of the boundary scanning component, the JTAG input interface, the JTAG output interface, and the gold finger interface are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other.

The gold finger interface of each test card is correspondingly plugged into the adapter card plug-in interface of each adapter card, so that the TDI pins of the corresponding plug-in gold finger interface and the adapter card plug-in interface are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other; and the test card performs a JTAG standard pin test based on the JTAG format test signal provided by the corresponding plug-in slot to be tested and feeds back a JTAG format test result signal.

The TAP controller forms electrical connections with different serial links to be tested, converts different test data into corresponding test signals in JTAG format to provide to the corresponding serial links to be tested, receives the test result signals in JTAG format from the serial links to be tested and converts them into response data.

The test data generating device is electrically connected to the TAP controller, provides test data to the TAP controller, and receives response data corresponding to the adapter card from the TAP controller.

The second embodiment of the JTAG standard pin test system disclosed in the present invention includes: a board to be tested, multiple adapter cards, multiple test cards, a TAP controller, and a test data generation device.

The board to be tested has multiple slots to be tested.

Each adapter card has an adapter card plug-in interface, an adapter card gold finger interface, a first JTAG input interface, a first JTAG output interface, a second JTAG input interface, and a second JTAG output interface. The TDI pins of the adapter card plug-in interface, the adapter card gold finger interface, the first JTAG input interface, the first JTAG output interface, the second JTAG input interface, and the second JTAG output interface are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other.

The adapter card gold finger interface of each adapter card is correspondingly plugged into each slot to be tested, so that the correspondingly plugged adapter card gold finger interface and each TDI pin of the slot to be tested are electrically connected to each other, each TDO pin is electrically connected to each other, each TCK pin is electrically connected to each other, each TMS pin is electrically connected to each other, and each TRST pin is electrically connected to each other; and the adapter cards are electrically connected to each other through their respective first JTAG input interface and first JTAG output interface or second JTAG input interface and second JTAG output interface to form different adapter card serial chains.

Each test card has a boundary scanning component, a JTAG input interface, a JTAG output interface, and a gold finger interface. The TDI pins of the boundary scanning component, the JTAG input interface, the JTAG output interface, and the gold finger interface are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other.

The gold finger interface of each test card is correspondingly plugged into the adapter card plug-in interface of each adapter card, so that the TDI pins of the corresponding plug-in gold finger interface and the adapter card plug-in interface are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other; and the test card performs a JTAG standard pin test based on the JTAG format test signal provided by the corresponding plug-in adapter card and feeds back a JTAG format test result signal.

The TAP controller forms electrical connections with different adapter card serial links respectively, converts different test data into corresponding JTAG format test signals to provide to the corresponding adapter card serial links, receives the JTAG format test result signals from the adapter card serial links and converts them into response data.

The test data generating device is electrically connected to the TAP controller, provides test data to the TAP controller, and receives response data corresponding to the adapter card from the TAP controller.

The system disclosed in the present invention is as described above, where the tested sockets are electrically connected to form different tested serial chains, or the adapter cards are electrically connected to form different adapter card serial chains through their respective first JTAG input interface and first JTAG output interface or second JTAG input interface and second JTAG output interface, and the TAP controller provides a corresponding JTAG format test signal to the tested serial chain or adapter card serial chain so that the test card can perform a JTAG standard pin test.

Through the above-mentioned technical means, the present invention can achieve the technical effect of providing a test machine with multiple test slots on different test boards to perform JTAG standard pin testing.

10: Board to be tested

11: Slots to be tested

111: The first slot to be tested

112: The second slot to be tested

113: The third slot to be tested

114: The fourth slot to be tested

115: The fifth slot to be tested

116: The sixth slot to be tested

117: The seventh slot to be tested

118: The eighth slot to be tested

20: Adapter card

201: First adapter card

202: Second adapter card

203: Third adapter card

204: Fourth adapter card

205: Fifth adapter card

206: Sixth adapter card

207: Seventh adapter card

208: The eighth adapter card

21: Adapter card interface

22: Adapter card gold finger interface

23: First JTAG input interface

24: First JTAG output interface

25: Second JTAG input interface

26: Second JTAG output interface

30:Test Card

301: First test card

302: Second test card

303: The third test card

304: The fourth test card

305: Fifth Test Card

306: Sixth Test Card

307: Seventh Test Card

308: Test Card 8

31:Border scanning component

32: JTAG input interface

33:JTAG output interface

34: Goldfinger interface

40:TAP controller

50: Test data generation device

61:TDI pin

62: TDO pin

63: TCK pin

64:TMS pin

65:TRST pin

Figure 1 shows a system block diagram of the first implementation of the JTAG standard pin test of the present invention.

Figure 2 shows a block diagram of the adapter card for the first implementation of the JTAG standard pin test of the present invention.

Figure 3 shows a block diagram of the test card for the first implementation of the JTAG standard pin test of the present invention.

Figure 4 shows a system block diagram of the second implementation of the JTAG standard pin test of the present invention.

Figure 5 shows a block diagram of the adapter card of the second implementation of the JTAG standard pin test of the present invention.

Figure 6 shows a block diagram of a test card for the second implementation of the JTAG standard pin test of the present invention.

Figure 7 shows the test architecture diagram of the second implementation of the JTAG standard pin test of the present invention.

The following will be used in conjunction with diagrams and examples to explain in detail the implementation of the present invention, so that the process of how the present invention applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

The following describes the JTAG standard pin test system of the first embodiment disclosed in the present invention, and please refer to "Figure 1", which is a system block diagram of the first embodiment of the JTAG standard pin test of the present invention.

The first embodiment of the JTAG standard pin test system disclosed in the present invention includes: a board to be tested 10, a plurality of adapter cards 20, a plurality of test cards 30, a test access port (TAP) controller 40 and a test data generating device 50.

The board to be tested 10 has a plurality of slots to be tested 11, and the plurality of slots to be tested 11 are electrically connected to form different serial chains to be tested. Specifically, assuming that the board to be tested 10 has a first slot to be tested, a second slot to be tested, a third slot to be tested, and a fourth slot to be tested, the first slot to be tested and the second slot to be tested are electrically connected to form a first serial chain to be tested, and the third slot to be tested and the fourth slot to be tested are electrically connected to form a second serial chain to be tested; the first slot to be tested and the third slot to be tested are electrically connected to form a first serial chain to be tested, and the second slot to be tested and the fourth slot to be tested are electrically connected to form a second serial chain to be tested; this is only an example to illustrate, and the scope of application of the present invention is not limited thereto.

Please refer to "FIG. 2", which is a block diagram of an adapter card of the first embodiment of the JTAG standard pin test of the present invention. Each adapter card 20 has an adapter card plug-in interface 21, an adapter card gold finger interface 22, a first JTAG input interface 23, a first JTAG output interface 24, a second JTAG input interface 25, and a second JTAG output interface 26. The test data input (TDI) pins 61 of the adapter card plug-in interface 21, the adapter card gold finger interface 22, the first JTAG input interface 23, the first JTAG output interface 24, the second JTAG input interface 25, and the second JTAG output interface 26 are electrically connected to each other. Output (TDO) pins 62 are electrically connected to each other, each test clock (TCK) pin 63 is electrically connected to each other, each test mode select (TMS) pin 64 is electrically connected to each other, and each test reset (TRST) pin 65 is electrically connected to each other.

The adapter card gold finger interface 22 of each adapter card 20 is correspondingly plugged into each slot 11 to be tested, so that the correspondingly plugged adapter card gold finger interface 22 and each TDI pin 61 of the slot 11 to be tested are electrically connected to each other, each TDO pin 62 is electrically connected to each other, each TCK pin 63 is electrically connected to each other, each TMS pin 64 is electrically connected to each other, and each TRST pin 65 is electrically connected to each other.

Based on the above example, the first adapter card is plugged into the first slot to be tested, the second adapter card is plugged into the second slot to be tested, the third adapter card is plugged into the third slot to be tested, and the fourth adapter card is plugged into the fourth slot to be tested, that is, the adapter card gold finger interface of the first adapter card and the TDI pins of the first slot to be tested are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, and the The TMS pins are electrically connected to each other and the TRST pins are electrically connected to each other. The adapter card gold finger interface of the second adapter card and the TDI pins of the second test slot are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other. The rest is similar and will not be elaborated here.

Please refer to "Figure 3", which is a block diagram of a test card of the first embodiment of the JTAG standard pin test of the present invention. Each test card 30 has a boundary scanning element 31, a JTAG input interface 32, a JTAG output interface 33 and a gold finger interface 34. The TDI pins 61 of the boundary scanning element 31, the JTAG input interface 32, the JTAG output interface 33 and the gold finger interface 34 are electrically connected to each other, the TDO pins 62 are electrically connected to each other, the TCK pins 63 are electrically connected to each other, the TMS pins 64 are electrically connected to each other, and the TRST pins 65 are electrically connected to each other.

The gold finger interface 34 of each test card 30 is correspondingly connected to the adapter card plug-in interface 21 of each adapter card 20, so that the correspondingly connected gold finger interface 34 and the adapter card plug-in interface 21 form an electrical connection between each TDI pin 61, each TDO pin 62 forms an electrical connection between each other, each TCK pin 63 forms an electrical connection between each other, each TMS pin 64 forms an electrical connection between each other, and each TRST pin 65 forms an electrical connection between each other

Based on the above example, the first test card is plugged into the first adapter card, the second test card is plugged into the second adapter card, the third test card is plugged into the third adapter card, and the fourth test card is plugged into the fourth adapter card. That is, the TDI pins of the gold finger interface of the first test card and the adapter card plug-in interface of the first adapter card are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, and the TMS pins are electrically connected to each other. The pins are electrically connected to each other and the TRST pins are electrically connected to each other, the gold finger interface of the second test card and the adapter card plug-in interface of the second adapter card are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other, and the rest are similar, and will not be repeated here.

The test data generating device 50 is electrically connected to the TAP controller 40, and the test data generating device 50 provides test data to the TAP controller 40. The TAP controller 40 is electrically connected to different serial links to be tested, and converts different test data into corresponding test signals in JTAG format to provide to the corresponding serial links to be tested.

The test card 30 can test the JTAG standard pins from the JTAG format test signal provided by the corresponding plugged-in test slot 11 and feed back the JTAG format test result signal, so that the TAP controller 40 receives the JTAG format test result signal from the test serial link and converts it into response data. The test data generating device 50 receives the response data corresponding to the adapter card 20 from the TAP controller 40, thereby completing the entire test process.

It is worth noting that in the actual test state, if the first slot to be tested and the third slot to be tested are electrically connected to each other to form a first serial chain to be tested, and the second slot to be tested and the fourth slot to be tested are electrically connected to each other to form a second serial chain to be tested, only the first adapter card can be plugged into the first slot to be tested and the third adapter card can be plugged into the third slot to be tested, and the first test card can be plugged into the first adapter card and the third test card can be plugged into the third adapter card.

The test data generating device 50 can only provide the test data corresponding to the first serial link to be tested to the TAP controller 40. The TAP controller 40 converts the test data into a test signal in the JTAG format corresponding to the first serial link to be tested, and then provides it to the first serial link to be tested, so that the first test card and the third test card perform a JTAG standard pin test and feedback a JTAG format test result signal. This is only an example to illustrate, and the scope of application of the present invention is not limited to this.

Alternatively, only the second adapter card may be plugged into the second slot to be tested and the fourth adapter card may be plugged into the fourth slot to be tested, and the second test card may be plugged into the second adapter card and the fourth test card may be plugged into the fourth adapter card. The test data generating device 50 may only provide the test data corresponding to the second serial link to be tested to the TAP controller 40. The TAP controller 40 may provide the test data as a test signal in the JTAG format corresponding to the second serial link to be tested to the second serial link to be tested, so that the second test card and the fourth test card may test the JTAG standard pins and feedback the test result signal in the JTAG format. This is only an example to illustrate, and the scope of application of the present invention is not limited to this.

Alternatively, the first adapter card may be plugged into the first slot to be tested, the second adapter card may be plugged into the second slot to be tested, the third adapter card may be plugged into the third slot to be tested, and the fourth adapter card may be plugged into the fourth slot to be tested, and the first test card may be plugged into the first adapter card, the second test card may be plugged into the second adapter card, the third test card may be plugged into the third adapter card, and the fourth test card may be plugged into the fourth adapter card. The test data generating device 50 may only provide the first serial link to be tested or the second serial link to be tested. The corresponding test data is connected to the TAP controller 40, and the TAP controller 40 converts the test data into a JTAG format test signal corresponding to the first serial link to be tested or the second serial link to be tested, and then provides it to the first serial link to be tested or the second serial link to be tested, so that the first test card and the third test card or the second test card and the fourth test card perform a JTAG standard pin test and feedback a JTAG format test result signal. This is only an example to illustrate, and the scope of application of the present invention is not limited to this.

The following describes the JTAG standard pin test system of the second embodiment disclosed in the present invention, and please refer to "Figure 4", which is a system block diagram of the second embodiment of the JTAG standard pin test of the present invention.

The second embodiment of the JTAG standard pin test system disclosed in the present invention comprises: a board to be tested 10, a plurality of adapter cards 20, a plurality of test cards 30, a TAP controller 40 and a test data generating device 50, wherein the board to be tested 10 has a plurality of slots to be tested 11.

Please refer to "Figure 5", which is a block diagram of an adapter card of the second embodiment of the JTAG standard pin test of the present invention. Each adapter card 20 has an adapter card plug-in interface 21, an adapter card gold finger interface 22, a first JTAG input interface 23, a first JTAG output interface 24, a second JTAG input interface 25 and a second JTAG output interface 26. The TDI pins 61 of the interface 22, the first JTAG input interface 23, the first JTAG output interface 24, the second JTAG input interface 25 and the second JTAG output interface 26 are electrically connected to each other, the TDO pins 62 are electrically connected to each other, the TCK pins 63 are electrically connected to each other, the TMS pins 64 are electrically connected to each other, and the TRST pins 65 are electrically connected to each other.

The adapter card gold finger interface 22 of each adapter card 20 is correspondingly plugged into each slot 11 to be tested, so that the correspondingly plugged adapter card gold finger interface 22 and each TDI pin 61 of the slot 11 to be tested are electrically connected to each other, each TDO pin 62 is electrically connected to each other, each TCK pin 63 is electrically connected to each other, each TMS pin 64 is electrically connected to each other, and each TRST pin 65 is electrically connected to each other; and the adapter cards 20 are electrically connected to each other through their respective first JTAG input interface 23 and first JTAG output interface 24 or second JTAG input interface 25 and second JTAG output interface 26 to form different adapter card serial chains.

The first adapter card is plugged into the first slot to be tested, the second adapter card is plugged into the second slot to be tested, the third adapter card is plugged into the third slot to be tested, and the fourth adapter card is plugged into the fourth slot to be tested, that is, the adapter card gold finger interface of the first adapter card and the TDI pins of the first slot to be tested are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, and the TMS pins are electrically connected to each other. The pins are electrically connected to each other and the TRST pins are electrically connected to each other, the adapter card gold finger interface of the second adapter card and the TDI pins of the second test slot are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other, and the rest is similar, which will not be elaborated here.

The first JTAG output interface of the first adapter card and the first JTAG input interface of the second adapter card are electrically connected to form a first adapter card serial chain, and the first JTAG output interface of the third adapter card and the first JTAG input interface of the fourth adapter card are electrically connected to form a second adapter card serial chain; the first JTAG output interface of the first adapter card and the first JTAG input interface of the second adapter card are electrically connected to form a first adapter card serial chain, and the second JTAG output interface of the third adapter card and the second JTAG input interface of the fourth adapter card are electrically connected to form a second adapter card serial chain; the first JTAG output interface of the first adapter card and the first JTAG input interface of the third adapter card are electrically connected to form a second adapter card serial chain. The first JTAG output interface of the second adapter card and the first JTAG input interface of the fourth adapter card are electrically connected to form a first adapter card serial chain; the first JTAG output interface of the first adapter card and the first JTAG input interface of the third adapter card are electrically connected to form a first adapter card serial chain, and the second JTAG output interface of the second adapter card and the second JTAG input interface of the fourth adapter card are electrically connected to form a second adapter card serial chain; the adapter card serial chain described above is only an example, and the other combinations of forming the adapter card serial chain can be deduced accordingly, which will not be elaborated here and the scope of application of the present invention is not limited thereto.

Please refer to "Figure 6", which is a block diagram of a test card of the second embodiment of the JTAG standard pin test of the present invention. Each test card 30 has a boundary scanning element 31, a JTAG input interface 32, a JTAG output interface 33 and a gold finger interface 34. The TDI pins 61 of the boundary scanning element 31, the JTAG input interface 32, the JTAG output interface 33 and the gold finger interface 34 are electrically connected to each other, the TDO pins 62 are electrically connected to each other, the TCK pins 63 are electrically connected to each other, the TMS pins 64 are electrically connected to each other, and the TRST pins 65 are electrically connected to each other.

The gold finger interface 34 of each test card 30 is correspondingly connected to the adapter card plug-in interface 21 of each adapter card 20, so that the corresponding gold finger interface 34 and the adapter card plug-in interface 21 form an electrical connection with each other, the TDO pins 62 form an electrical connection with each other, the TCK pins 63 form an electrical connection with each other, the TMS pins 64 form an electrical connection with each other, and the TRST pins 65 form an electrical connection with each other; and the test card 30 performs a JTAG standard pin test based on the JTAG format test signal provided by the corresponding adapter card 20 and feeds back a JTAG format test result signal.

Based on the above example, the first test card is plugged into the first adapter card, the second test card is plugged into the second adapter card, the third test card is plugged into the third adapter card, and the fourth test card is plugged into the fourth adapter card. That is, the TDI pins of the gold finger interface of the first test card and the adapter card plug-in interface of the first adapter card are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, and the TMS pins are electrically connected to each other. The pins are electrically connected to each other and the TRST pins are electrically connected to each other, the gold finger interface of the second test card and the adapter card plug-in interface of the second adapter card are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other, and the rest are similar, and will not be repeated here.

The test data generating device 50 is electrically connected to the TAP controller 40, and the test data generating device 50 provides test data to the TAP controller 40. The TAP controller 40 is electrically connected to different adapter card serial links respectively, and converts different test data into corresponding JTAG format test signals to provide to the corresponding adapter card serial links.

The test card 30 can test the JTAG standard pins from the JTAG format test signal provided by the corresponding plug-in adapter card 20 and feed back the JTAG format test result signal, so that the TAP controller 40 receives the JTAG format test result signal from the adapter card serial link and converts it into response data. The test data generating device 50 receives the response data corresponding to the adapter card 20 from the TAP controller 40, thereby completing the entire test process.

Please refer to FIG. 7, which is a test architecture diagram of the second embodiment of the JTAG standard pin test of the present invention. The first JTAG output interface of the first adapter card 201 is electrically connected to the first JTAG input interface of the third adapter card 203, the first JTAG output interface of the third adapter card 203 is electrically connected to the first JTAG input interface of the fifth adapter card 205, and the first JTAG output interface of the fifth adapter card 205 is electrically connected to the first JTAG input interface of the seventh adapter card 207. The AG input interface forms an electrical connection to form a first adapter card serial chain, the second JTAG output interface of the second adapter card 202 forms an electrical connection with the second JTAG input interface of the fourth adapter card 204, the second JTAG output interface of the fourth adapter card 204 forms an electrical connection with the second JTAG input interface of the sixth adapter card 204, and the second JTAG output interface of the sixth adapter card 206 forms an electrical connection with the second JTAG input interface of the eighth adapter card 208 to form a second adapter card serial chain.

The first test card 301 is electrically connected to the first adapter card 201, the second test card 302 is electrically connected to the second adapter card 202, the third test card 303 is electrically connected to the third adapter card 203, the fourth test card 304 is electrically connected to the fourth adapter card 204, the fifth test card 305 is electrically connected to the fifth adapter card 205, the sixth test card 306 is electrically connected to the sixth adapter card 206, the seventh test card 307 is electrically connected to the seventh adapter card 207, and the eighth test card 308 is electrically connected to the eighth adapter card 208.

In the actual testing process, only the first riser card 201 can be plugged into the first slot to be tested 111, the third riser card 203 can be plugged into the third slot to be tested 113, the fifth riser card 205 can be plugged into the fifth slot to be tested 115, and the seventh riser card 207 can be plugged into the seventh slot to be tested 117.

The test data generating device 50 provides the test data corresponding to the first adapter card serial link to the TAP controller 40. The TAP controller 40 converts the test data into a test signal in the JTAG format corresponding to the first adapter card serial link, and then provides it to the first adapter card serial link, so that the first test card 201, the third test card 203, the fifth test card 205 and the seventh test card 207 perform the JTAG standard pin test and feedback the test result signal in the JTAG format.

In the actual testing process, only the second riser card 202 may be plugged into the second slot to be tested 112, the fourth riser card 204 may be plugged into the fourth slot to be tested 114, the sixth riser card 206 may be plugged into the sixth slot to be tested 116, and the eighth riser card 208 may be plugged into the eighth slot to be tested 118.

The test data generating device 50 provides the test data corresponding to the second adapter card serial link to the TAP controller 40. The TAP controller 40 converts the test data into a JTAG format test signal corresponding to the second adapter card serial link, and then provides it to the second adapter card serial link, so that the second test card 202, the fourth test card 204, the sixth test card 206 and the eighth test card 208 perform a JTAG standard pin test and feedback a JTAG format test result signal.

In the actual testing process, the first riser card 201 can be plugged into the first slot to be tested 111, the second riser card 202 can be plugged into the second slot to be tested 112, the third riser card 203 can be plugged into the third slot to be tested 113, the fourth riser card 204 can be plugged into the fourth slot to be tested 114, the fifth riser card 205 can be plugged into the fifth slot to be tested 115, the sixth riser card 206 can be plugged into the sixth slot to be tested 116, the seventh riser card 207 can be plugged into the seventh slot to be tested 117, and the eighth riser card 208 can be plugged into the eighth slot to be tested 118.

The test data generating device 50 can only provide the test data corresponding to the first adapter card serial chain or the second adapter card serial chain to the TAP controller 40. The TAP controller 40 converts the test data into a test signal in the JTAG format corresponding to the first adapter card serial chain or the second adapter card serial chain, and then provides it to the first adapter card serial chain or the second adapter card serial chain, so that the first test card 201, the third test card 203, the fifth test card 205 and the seventh test card 207 or the second test card 202, the fourth test card 204, the sixth test card 206 and the eighth test card 208 perform the JTAG standard pin test and feedback the test result signal in the JTAG format.

The test data generating device 50 can simultaneously provide the test data corresponding to the first adapter card serial chain and the second adapter card serial chain to the TAP controller 40. The TAP controller 40 converts the test data into a JTAG format test signal corresponding to the first adapter card serial chain and the second adapter card serial chain, and then provides it to the first adapter card serial chain and the second adapter card serial chain respectively, so that the first test card 201, the second test card 202, the third test card 203, the fourth test card 204, the fifth test card 205, the sixth test card 206, the seventh test card 207 and the eighth test card 208 can simultaneously perform the JTAG standard pin test and feedback the JTAG format test result signal.

The above detection processes are only used as examples for illustration, and the present invention is not limited thereto. A person skilled in the art can realize different combinations of adapter card cascade chains based on the above detection processes, and will not be elaborated here.

In summary, the sockets to be tested are electrically connected to form different serial chains to be tested, or the adapter cards are electrically connected to form different adapter card serial chains through their respective first JTAG input interface and first JTAG output interface or second JTAG input interface and second JTAG output interface. The TAP controller provides a corresponding JTAG format test signal to the serial chain to be tested or the adapter card serial chain so that the test card can perform a JTAG standard pin test.

This technical means can solve the problem of the previous technology that the test machine can only provide multiple test slots on the same test board for JTAG standard pin testing, thereby achieving the technical effect of the test machine providing multiple test slots on different test boards for JTAG standard pin testing.

Although the implementation method disclosed in the present invention is as above, the content described is not used to directly limit the scope of patent protection of the present invention. Anyone with common knowledge in the technical field to which the present invention belongs can make slight changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention. The scope of patent protection of the present invention shall still be defined by the scope of the attached patent application.

10: Board to be tested

11: Slots to be tested

20: Adapter card

21: Adapter card interface

22: Adapter card gold finger interface

23: First JTAG input interface

24: First JTAG output interface

25: Second JTAG input interface

26: Second JTAG output interface

30: Test Card

34: Goldfinger interface

40:TAP controller

50: Test data generation device

Claims (9)

A JTAG standard pin test system comprises: a test board having a plurality of test slots, wherein the plurality of test slots are electrically connected to each other to form different test serial chains; a plurality of adapter cards, each adapter card having an adapter card plug-in interface, an adapter card gold finger interface, a first JTAG input interface, a first JTAG output interface, a second JTAG input interface and a second JTAG output interface, wherein each test data input (Test Data Input, TDI) pin of the adapter card plug-in interface, the adapter card gold finger interface, the first JTAG input interface, the first JTAG output interface, the second JTAG input interface and the second JTAG output interface are electrically connected to each other, each test data output (Test Data Output, TDO) pin is electrically connected to each other, each test clock (Test Clock) The test clock (TCK) pins are electrically connected to each other, the test mode select (TMS) pins are electrically connected to each other, and the test initialization (Test Reset, TRST) pins are electrically connected to each other; wherein the adapter card gold finger interface of each adapter card is correspondingly plugged into each slot to be tested, so that the correspondingly plugged adapter card gold finger interface and each TDI pin of the slot to be tested are electrically connected to each other, each TDO pin is electrically connected to each other, each TCK pin is electrically connected to each other, each TMS pin is electrically connected to each other, and each TRST pin is electrically connected to each other; multiple test cards, each test card has a boundary scanning element, a JTAG input interface, a JTAG output interface and a gold finger interface, the boundary scanning element, the JTAG input interface, the JTAG output interface and each TDI pin of the gold finger interface are electrically connected to each other, each TDO pin is electrically connected to each other The test card is electrically connected to the test slot to be tested by the test card, wherein the gold finger interface of each test card is correspondingly connected to the adapter card plug-in interface of each adapter card, so that the TDI pins of the correspondingly plugged gold finger interface and the adapter card plug-in interface are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other; and the test card performs a test on the JTAG standard pins based on a test signal in the JTAG format provided by the correspondingly plugged test slot and feeds back a test result signal in the JTAG format; a test access port (Test Access Port) Access Port (TAP) controller, which is electrically connected to different serial links to be tested, converts different test data into the corresponding test signals in JTAG format to provide to the corresponding serial links to be tested, receives the test result signals in JTAG format from the serial links to be tested and converts them into response data; and a test data generating device, which is electrically connected to the TAP controller, provides the test data to the TAP controller, and receives the response data corresponding to the adapter card from the TAP controller. A JTAG standard pin test system as described in claim 1, wherein the test data generation device provides test data of a single serial link to be tested to the TAP controller, and the TAP controller converts the test data into the corresponding test signal in the JTAG format to provide to the single serial link to be tested. The JTAG standard pin test system as described in claim 1, wherein the adapter card and the test card are plugged into each other according to a single serial link to be tested, the test data generation device provides the test data of the single serial link to be tested to the TAP controller, and the TAP controller converts the test data into the corresponding test signal in the JTAG format to provide it to the single serial link to be tested. A JTAG standard pin test system comprises: a test board with multiple test slots; multiple adapter cards, each adapter card having an adapter card plug-in interface, an adapter card gold finger interface, a first JTAG input interface, a first JTAG output interface, a second JTAG input interface and a second JTAG output interface, wherein each TDI pin of the adapter card plug-in interface, the adapter card gold finger interface, the first JTAG input interface, the first JTAG output interface, the second JTAG input interface and the second JTAG output interface is electrically connected to each other, each TDO pin is electrically connected to each other, each TCK pin is electrically connected to each other, each TMS pin is electrically connected to each other, and each TRST pin is electrically connected to each other. The adapter card gold finger interface of each adapter card is correspondingly plugged into each slot to be tested, so that the correspondingly plugged adapter card gold finger interface and each TDI pin of the slot to be tested are electrically connected to each other, each TDO pin is electrically connected to each other, each TCK pin is electrically connected to each other, each TMS pin is electrically connected to each other, and each TRST pin is electrically connected to each other; and the adapter cards are electrically connected to each other through the first JTAG input interface and the first JTAG output interface or the second JTAG input interface and the second JTAG output interface to form different adapter card serial chains; multiple test cards, each test card has a boundary scanning element, a JTAG input interface, a JTAG output interface and a gold finger interface, the boundary scanning element, the JTAG input interface, the JTAG output interface and the gold finger interface each TDI pin is electrically connected to each other, each TDO pin is electrically connected to each other, each TCK pin is electrically connected to each other, each TMS pin is electrically connected to each other, and each TRST pin is electrically connected to each other; wherein the gold finger interface of each test card is correspondingly plugged with the adapter card plug-in interface of each adapter card, so that the correspondingly plugged gold finger interface and the adapter card plug-in interface each TDI pin is electrically connected to each other, each TDO pin is electrically connected to each other, each TCK pin is electrically connected to each other, each TMS pin is electrically connected to each other The test card tests the JTAG standard pins using a test signal in JTAG format provided by the corresponding adapter card and feeds back a test result signal in JTAG format; a TAP controller is electrically connected to different adapter card serial links, converts different test data into the corresponding test signals in JTAG format to provide to the corresponding adapter card serial links, receives the test result signal in JTAG format from the adapter card serial links and converts it into response data; and a test data generating device is electrically connected to the TAP controller, provides the test data to the TAP controller, and receives the response data corresponding to the adapter card from the TAP controller. A JTAG standard pin test system as described in claim 4, wherein the test data generation device provides the test data of a single adapter card serial link to the TAP controller, and the TAP controller converts the test data into the corresponding test signal in the JTAG format to provide it to the single adapter card serial link. The JTAG standard pin test system as described in claim 4, wherein the adapter card and the test card are plugged into each other according to a single adapter card serial link, the test data generation device provides the test data of the single adapter card serial link to the TAP controller, and the TAP controller converts the test data into the corresponding test signal in the JTAG format to provide it to the single adapter card serial link. A JTAG standard pin test system as described in claim 4, wherein the adapter card only uses the first JTAG input interface and the first JTAG output interface to form an electrical connection with each other to form a serial chain of different adapter cards. A JTAG standard pin test system as described in claim 4, wherein the adapter card only uses the second JTAG input interface and the second JTAG output interface to form an electrical connection with each other to form a serial chain of different adapter cards. The JTAG standard pin test system as described in claim 4, wherein the adapter card uses the first JTAG input interface and the first JTAG output interface to form an electrical connection with the second JTAG input interface and the second JTAG output interface to form different adapter card serial chains.

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