TWI869110B - Fan-out type stacked packaging body preparation method and equipment thereof - Google Patents

Abstract

The invention relates to a fan-out stacked packaging body, a preparation method and equipment thereof. The fan-out stacked packaged body comprises at least two pre-packaged bodies; each pre-packaged body at least comprises a chip, a first redistribution layer and a first interconnect; the pre-packaged bodies are interconnected in a stacked manner, and the first interconnect of one pre-packaged body of two adjacent pre-packaged bodies is electrically connected with the first redistribution layer of the other pre-packaged body; the first redistribution layer is located on active side of the chip, and the first interconnect and the chip are located on the same side of the first redistribution layer; in the first preset direction, the first interconnect is located on at least one side of the chip; the pre-packaged body comprises a first pre-packaged body and at least one second pre-packaged body; the first pre-packaged body is located on the outermost side of the fan-out type stacked packaged body; in the first preset direction, the length of the first pre-packaged body is greater than that of the second pre-packaged body. Therefore, the length of electrical interconnection is shortened, the electrical performance is much batter, no through-silicon via (TSV) and substrate are needed, thus the cost is reduced.

Description

Fan-out type stacked package, preparation method and equipment thereof

The present invention relates to the field of semiconductor technology, and in particular to a fan-out type stacked package, a preparation method and equipment thereof.

In the field of logic circuit and memory integration, package on package (PoP) has become the industry's first choice, mainly used to manufacture advanced mobile communication platforms used in high-end portable devices and smartphones. Low-power memory memory packaging consists of multiple memory chips stacked together and interconnected by wire bonding (WB). It is mainly used in the upper layer of the package stack in smartphones, or directly soldered to the motherboard of laptops.

Among the related technologies, low-power memory storage technology is the fifth-generation low-power double data rate memory standard (Low Power Double Data Rate 5X, LPDDR5X), with a maximum memory speed of 8.5 Gbps; the future sixth-generation low-power double data rate memory standard (Low Power Double Data Rate 6X, LPDDR6X), is expected to have a maximum memory speed of 17.0 Gbps. At this 17.0 Gbps memory high-speed operation speed, due to the consideration of signal integrity (SI) and power integrity (PI), the wire bonding (Wire bonding) is used. Bonding (WB) as the interconnection of memory stack is not sustainable. Since the metal lead is long and has a small diameter, its impedance is also high, resulting in poor electrical performance, easy signal distortion and long transmission time. Through-Silicon-Via (TSV) technology reduces the interconnection length and signal delay through vertical interconnection, has good electrical performance, reduces capacitance/inductance, achieves low power consumption and high-speed communication between chips, has greater space efficiency and higher interconnection density, but has a high process cost.

Similarly, in the field of computer servers, with the improvement of computing power, the demand for memory capacity is also increasing. The fourth/fifth generation double data rate synchronous dynamic random access memory (Double Data Rate Fourth/Fifth Generation Synchronous Dynamic Random Access Memory, DDR4/5 SDRAM) stacking is a way to solve the memory capacity demand. There are two solutions: one is that the DDR4/5 memory package consists of multiple memory chips stacked and interconnected through lead bonding; the other is that the DDR4/5 memory package consists of multiple memory chips stacked and interconnected through silicon via technology. These two solutions also have the same technical problems as mentioned above, that is, the wire bonding has poor electrical performance and the through silicon via has the technical problem of high process cost.

In order to solve the above technical problem or at least partially solve the above technical problem, the present invention provides a fan-out type stacked package, a preparation method and an apparatus thereof.

In a first aspect, the present invention provides a fan-out stacked package, comprising: at least two pre-packages; each of the pre-packages at least comprises a chip, a first redistribution layer and a first connector;

The at least two pre-package stacks are interconnected, the active surface of one of the two adjacent pre-packages is opposite to the passive surface of the other pre-package, and the first connector of one of the pre-packages is electrically connected to the first redistribution layer of the other pre-package;

Wherein, in the stacking interconnection direction, the first redistribution wiring layer is located on one side of the active surface of the chip, and the first connector and the chip are located on the same side of the first redistribution wiring layer; in the first preset direction, the first connector is located on at least one side of the chip, and the first connector is electrically connected to the chip through the first redistribution wiring layer;

The pre-package body includes a first pre-package body and at least one second pre-package body;

The first pre-package is located at the outermost side of the fan-out stack package and is used to be electrically connected to other components; in a first preset direction, the length of the first pre-package is greater than the length of the second pre-package, and the first preset direction is any direction perpendicular to the stack interconnection direction.

Optionally, the pre-package further comprises: a pre-package layer, the pre-package layer covers the chip and the first connector; the first connector comprises a first conductive column;

The first conductive column fills and penetrates the pre-package layer and is connected to the first redistribution layer of the pre-package body.

Optionally, the first connector of the second pre-package further comprises a metal bump;

The metal bump is electrically connected to the first conductive column and exposed outside the surface of the pre-package layer; the metal bump is electrically connected to the first redistribution layer of the adjacent pre-package body.

Optionally, the first pre-package further comprises a second redistribution layer and a second connector;

The second redistribution wiring layer is located on a side of the chip and the first conductive column away from the first redistribution wiring layer, the second connector is located on a side of the second redistribution wiring layer away from the chip and the first conductive column, the second redistribution wiring layer is electrically connected to the first conductive column and the second connector, and the second connector is used to connect other components externally.

Optionally, the second connecting body is configured as at least one of a second conductive column and a solder ball.

Optionally, the fan-out stacked package further comprises: a packaging layer,

The packaging layer is located on a side of the first pre-package body facing the second pre-package body, and the packaging layer covers the surface of the first pre-package body facing the second pre-package body and the second pre-package body.

Optionally, the pre-package further comprises: a bonding pad;

The bonding pad is located on one side of the active surface of the chip. The bonding pad is distributed in a region of the chip close to the first connector. The bonding pad is electrically connected to the first connector through the first redistribution layer.

Optionally, the chip includes at least one of a storage chip, a computing chip, a communication chip, a sensing chip and an energy chip.

Optionally, the first connectors in two adjacent pre-packaged packages are disposed at the same position.

In a second aspect, the present invention also provides a method for preparing a fan-out stacked package, comprising:

Forming at least two pre-packages; the pre-packages include a chip, a first redistribution layer and a first connector;

The pre-package stacks are interconnected, wherein the active surface of one of the two adjacent pre-packages faces the passive surface of the other pre-package, and the first connector of one of the pre-packages is electrically connected to the first redistribution layer of the other pre-package;

Wherein, in the stacking interconnection direction, the first redistribution wiring layer is located on one side of the active surface of the chip, and the first connector and the chip are located on the same side of the first redistribution wiring layer; in the first preset direction, the first connector is located on at least one side of the chip, and the first connector is electrically connected to the chip through the first redistribution wiring layer;

The pre-package includes a first pre-package and at least one second pre-package; the first pre-package is located at the outermost side of the fan-out stack package and is used to be electrically connected to other components; in a first preset direction, the length of the first pre-package is greater than the length of the second pre-package, and the first preset direction is any direction perpendicular to the stack interconnection direction.

Optionally, forming the pre-package includes:

Providing a first carrier board;

forming a first conductive column on one side of the first carrier;

Providing at least one chip;

The active surface of the chip is attached to the first carrier; the chip and the first conductive pillar are located on the same side of the first carrier;

forming a pre-packaging layer, wherein the pre-packaging layer covers the chip, the first conductive pillar, and the surface of the first carrier facing the chip and the first conductive pillar, and the first conductive pillar fills and penetrates the pre-packaging layer;

Providing a second carrier and attaching the second carrier to a side of the pre-packaging layer facing away from the first carrier;

The first carrier is removed, and a first redistribution wiring layer is formed on a side of the chip and the first conductive column facing away from the second carrier, wherein the first redistribution wiring layer is electrically connected to the chip and the first conductive column.

Optionally, forming the second pre-package further comprises:

Providing a third carrier and attaching the third carrier to a side of the first redistribution layer away from the chip and the first conductive column;

The second carrier is removed, and a metal bump is formed on a side of the first conductor column away from the third carrier. The metal bump is electrically connected to the first conductor column and exposed outside the surface of the pre-packaging layer.

Optionally, after interconnecting the pre-package stacks, the preparation method further comprises:

A packaging layer is formed on a side of the first pre-package body facing the second pre-package body; the packaging layer covers the surface of the first pre-package body facing the second pre-package body and the second pre-package body.

Optionally, the preparation method further comprises:

removing the second carrier board on a side of the first pre-package body away from the second pre-package body;

forming a second redistribution layer on a side of the chip and the first conductive pillar away from the first redistribution layer;

forming a second connector on a side of the second redistribution layer away from the chip and the first conductive column;

The second redistribution layer is electrically connected to the first connector and the second connector, and the second connector is used to connect to other components.

In a third aspect, the present invention further provides an electronic device, comprising: any one of the above-mentioned fan-out stacked packages.

The technical solution provided by the present invention has the following advantages compared with the prior art:

The fan-out type stacked package, its preparation method and equipment provided by the present invention, the fan-out type stacked package comprises: at least two pre-packages; each pre-package comprises a chip, a first redistribution layer and a first connector; the pre-package stacks are interconnected, the active surface of one pre-package and the passive surface of the other pre-package of the two adjacent pre-packages are opposite, and the first connector of one pre-package is electrically connected to the first redistribution layer of the other pre-package; wherein, in the direction of stack interconnection, the first redistribution layer is located on the active surface side of the chip, and the first connector is located on the passive surface side of the chip. A connector and a chip are located on the same side of a first redistribution layer; in a first preset direction, the first connector is located on at least one side of the chip, and the first connector is electrically connected to the chip through the first redistribution layer; the pre-package includes a first pre-package and at least one second pre-package; the first pre-package is located at the outermost side of the fan-out stacked package, and is used to be electrically connected to other components; in the first preset direction, the length of the first pre-package is greater than the length of the second pre-package, and the first preset direction is any direction perpendicular to the stacked interconnection direction. Thus, the stacked interconnection of the chip is realized through the first connector and the first redistribution layer, the length of the electrical interconnection is shortened, the electrical performance is higher, the connection reliability and the signal transmission rate are improved, and no perforation and substrate connection are required, which is conducive to reducing costs.

In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the scheme of the present invention will be further described below. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

In the following description, many specific details are described to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present invention, rather than all the embodiments.

In view of the problems raised in the background technology section, the embodiments of the present invention provide a fan-out type stacked package, a preparation method and an apparatus thereof, wherein the fan-out type stacked package comprises: at least two pre-packages; each pre-package comprises a chip, a first redistribution layer and a first connector; the pre-package stacks are interconnected, the active surface of one pre-package and the passive surface of the other pre-package of the two adjacent pre-packages are opposite, the first connector of one pre-package is electrically connected to the first redistribution layer of the other pre-package; wherein, in the direction of stack interconnection, the first redistribution layer is located at the chip; The first connector and the chip are located on the same side of the first redistribution layer on the active surface side of the chip; in a first preset direction, the first connector is located on at least one side of the chip, and the first connector is electrically connected to the chip through the first redistribution layer; the pre-package includes a first pre-package and at least one second pre-package; the first pre-package is located at the outermost side of the fan-out stacked package, and is used to be electrically connected to other components; in the first preset direction, the length of the first pre-package is greater than the length of the second pre-package, and the first preset direction is any direction perpendicular to the stacking interconnection direction. Thus, the stacked interconnection of the chips is realized through the first connector and the first redistribution layer, the length of the electrical interconnection is shortened, higher electrical performance is achieved, connection reliability and signal transmission rate are improved, and no perforation and connection substrate are required, which is conducive to reducing costs.

The fan-out stacked package, its preparation method and equipment provided by the embodiment of the present invention are exemplarily described below with reference to FIGS. 1 to 19 .

An embodiment of the present invention provides a stacked package, as shown in FIGS. 1-2 , wherein FIG. 1 is a schematic diagram of the structure of a stacked package provided by an embodiment of the present invention, and FIG. 2 is a schematic diagram of the structure of another stacked package provided by an embodiment of the present invention. 1-2, the fan-out stacked package 100 includes: at least two pre-packages 10; each pre-package 10 includes at least a chip 11, a first redistribution layer 12 and a first connector 13; at least two pre-packages 10 are stacked and interconnected, and the active surface of one pre-package 10 and the passive surface of the other pre-package 10 of the two adjacent pre-packages 10 are opposite, and the first connector 13 of one pre-package 10 is electrically connected to the first redistribution layer 12 of the other pre-package 10; wherein, in the stacked interconnection direction, the first redistribution layer 12 is located on the active surface side of the chip 11, The first connector 13 and the chip 11 are located on the same side of the first redistribution layer 12; in the first preset direction X, the first connector 13 is located on at least one side of the chip 11, and the first connector 13 is electrically connected to the chip 11 through the first redistribution layer 12; the pre-package 10 includes a first pre-package and at least one second pre-package; the first pre-package is located at the outermost side of the fan-out stacked package, and is used to be electrically connected to other components; in the first preset direction X, the length of the first pre-package is greater than the length of the second pre-package, and the first preset direction X is any direction perpendicular to the stacking interconnection direction.

Among them, the chip 11 includes but is not limited to a storage chip, a computing chip, a sensing chip, a communication chip, a sensing chip and an energy chip, for example, a dynamic random access memory (DRAM) chip or a double data rate dynamic random access memory (DDR DRAM).

The first redistribution layer 12 is a metal film layer, which can be prepared by electroplating or deposition process; the metal material can be selected from at least one of copper, aluminum, silver, gold and titanium. The height of the first connector 13 in the stacking interconnection direction is equal to or greater than the height of the chip 11. This arrangement enables the first connector 13 of the pre-package 10 located on the upper layer to contact the first redistribution layer 12 of the pre-package 10 located on the lower layer, ensuring reliable connection. The first connector 13 can be provided with a metal column or metal block formed by a metal material, such as a copper column, an aluminum column and a silver column, etc., or a columnar body formed by other conductive materials, which is not limited here. The first connector 13 and the first redistribution layer 12 may be made of the same material, or may be made of different materials, which is not limited here.

The first pre-package is the bottommost pre-package in the fan-out stacked package 100, and the remaining pre-packages are second pre-packages; as shown in FIG1-2, the first preset direction X is perpendicular to the stacked interconnection direction, and the length of the first pre-package is greater than the length of the second pre-package; in this way, when the fan-out stacked package is packaged as a whole, the side of the first pre-package facing the second pre-package can be used as a backing to provide support for the package layer without the need for a connection substrate. By forming a second redistribution layer 15 and a second connector 13 on the side of the first pre-package facing away from the second pre-package, the fan-out stacked package 100 can be electrically connected to other components.

Exemplarily, as shown in FIG1 , the fan-out type stacked package 100 includes four stacked interconnected pre-packages 10, wherein the pre-package 10 located at the bottom layer of the fan-out type stacked package 100 is a first pre-package, and the remaining pre-packages 10 are second pre-packages; each pre-package 10 includes two chips 11, a first redistribution wiring layer 12 and a first connector 13; in the stacked interconnection direction, the active surface of the chip 11 is electrically connected to the first redistribution wiring layer 12, and in the first preset direction X, the first connector 13 is located on one side of the chip 11, and the first connector 13 is electrically connected to the chip 11 through the first redistribution wiring layer 12; the first connector 13 is distributed in the area between the two chips 11. In the stacking interconnection direction, the first connector 13 of the upper pre-package 10 of the two adjacent pre-packages 10 is electrically connected to the first redistribution layer 12 of the lower pre-package 10. The side of the chip 11 in the pre-package 10 facing the first redistribution layer 12 is the active side, and the side away from the redistribution layer is the passive side. The passive side of the upper pre-package 10 is connected to the lower pre-package 10. The active surfaces of the package 10 are opposite to each other; the stacking interconnection of the chips is realized through the first connector 13 and the first redistribution layer 12, thereby shortening the length of the electrical interconnection; in the first preset direction X, the length of the first pre-package body is greater than the length of the second pre-package body, and the first pre-package body can be used as a substrate to form a packaging layer on a side of the first pre-package body facing the second pre-package body without the need for connecting the substrate, which is conducive to reducing costs.

Exemplarily, as shown in FIG2 , the fan-out type stacked package 100 includes four stacked interconnected pre-packages 10, wherein the pre-package 10 located at the bottom layer of the fan-out type stacked package 100 is a first pre-package, and the remaining pre-packages 10 are second pre-packages; each pre-package 10 includes a chip 11, a first redistribution wiring layer 12 and a first connector 13; in the stacked interconnection direction, the active surface of the chip 11 is electrically connected to the first redistribution wiring layer 12, and in the first preset direction X, the first connector 13 is located on both sides of the chip 11, and the first connector 13 is electrically connected to the chip 11 through the first redistribution wiring layer 12; the first connector 13 is distributed in the two side areas of the chip 11. In the stacking interconnection direction, the first connector 13 of the upper pre-package 10 of the two adjacent pre-packages 10 is electrically connected to the first redistribution layer 12 of the lower pre-package 10. The side of the chip 11 in the pre-package 10 facing the first redistribution layer 12 is the active side, and the side away from the redistribution layer is the passive side. The passive side of the upper pre-package 10 is connected to the lower pre-package 10. The active surfaces of the package 10 are opposite to each other; the stacking interconnection of the chips is realized through the first connector 13 and the first redistribution layer 12, thereby shortening the length of the electrical interconnection; in the first preset direction X, the length of the first pre-package body is greater than the length of the second pre-package body, and the first pre-package body can be used as a substrate to form a packaging layer on a side of the first pre-package body facing the second pre-package body without the need for connecting the substrate, which is conducive to reducing costs.

Among them, the first connector 13 of the pre-package 10 located on the upper layer is electrically connected to the first redistribution layer 12 of the pre-package 10 located on the lower layer thereof, and all metal connection processes known to technicians in this field can be used for connection, such as pressure welding, arc welding, argon arc welding, gas shielded arc welding and laser welding, which are not limited here.

It should be noted that FIGS. 1-2 only exemplarily show that the stacked package 100 includes four pre-packages 10, and each pre-package 10 in FIG. 1 includes two chips 11 and the first connector 13 is distributed in the area between the two chips 11; each pre-package 10 in FIG. 2 includes one chip 11 and the first connector 13 is distributed on both sides of the chip 11, but the above contents do not constitute a limitation on the stacked package provided by the embodiment of the present invention. In other embodiments, the number of pre-packages 10, the number of chips 11 in each pre-package 10, and the distribution area of the first connector 13 can be set according to the requirements of the stacked package, and are not limited here.

For example, as shown in Fig. 3-4, Fig. 3 is a schematic diagram of the structure of a second pre-package provided by an embodiment of the present invention, and Fig. 4 is a schematic diagram of the structure of a first pre-package provided by an embodiment of the present invention; wherein the first preset direction X and the second preset direction Y are both perpendicular to the stacking interconnection direction. Referring to Fig. 3-4, in the first preset direction X and the second preset direction Y, the length of the first pre-package is greater than the length of the second pre-package; in this way, when the fan-out stacking package is packaged as a whole, the side of the first pre-package facing the second pre-package can be used as a backing to provide support for the package layer without the need for a connection substrate. In any direction perpendicular to the interconnection of the stacked layers, the length of the first pre-package is equal to the length of the packaging layer; for example, the length of the first pre-package in the first preset direction X is 14 mm, and the length in the second preset direction Y is 12.4 mm.

It can be understood that FIG. 4 only shows that the size of the first pre-package is 14 mm×12.4 mm by way of example, but does not constitute a limitation on the embodiments of the present invention. In other embodiments, the size of the first pre-package layer is set according to the requirements of the removable stacking package, for example, for a single DDR4 DRAM chip, the size of the first pre-package is 7.5 mm×11 mm, and for a single DDR5 DRAM chip, the size of the first pre-package is 9 mm×11 mm, which is not limited here.

The present invention provides a fan-out stacked package 100, comprising: at least two pre-packages 10; each pre-package 10 comprises a chip 11, a first redistribution layer 12 and a first connector 13; the pre-packages 10 are stacked and interconnected, the active surface of one pre-package 10 and the passive surface of the other pre-package 10 of the two adjacent pre-packages 10 are opposite, and the first connector 13 of one pre-package 10 is electrically connected to the first redistribution layer 12 of the other pre-package 10; wherein, in the stacked interconnection direction, the first redistribution layer 12 is located on one side of the active surface of the chip 11, and the first connector 13 is located on the other side of the active surface of the chip 11. A connector 13 and a chip 11 are located on the same side of a first redistribution layer 12; in a first preset direction, the first connector 13 is located on at least one side of the chip 11, and the first connector 13 is electrically connected to the chip 11 through the first redistribution layer 12; the pre-package 10 includes a first pre-package and at least one second pre-package; the first pre-package is located at the outermost side of the fan-out stacked package, and is used to be electrically connected to other components; in a first preset direction X, the length of the first pre-package is greater than the length of the second pre-package, and the first preset direction X is any direction perpendicular to the stacking interconnection direction. Thus, the stacked interconnection of the chips is realized through the first connector 13 and the first redistribution layer 12, the length of the electrical interconnection is shortened, higher electrical performance is achieved, connection reliability and signal transmission rate are improved, and no perforation and connection substrate are required, which is conducive to reducing costs.

In some embodiments, as shown in Fig. 1-2 and Fig. 5-6, Fig. 5 is a schematic diagram of the structure of another second pre-package provided by the embodiment of the present invention, and Fig. 6 is a schematic diagram of the structure of yet another second pre-package provided by the embodiment of the present invention. Referring to Fig. 1-2 and Fig. 5-6, the pre-package further includes: a pre-package layer 14, the pre-package layer 14 covers the chip 11 and the first connector 13; the first connector 13 includes a first conductive column 131; the first conductive column 131 fills and penetrates the pre-package layer 14, and connects the first redistribution layer 12 of the pre-package.

The pre-packaging layer 14 may be a resin layer, and the material may be one or more of epoxy molding compound (EMC), polyethylene, polypropylene, polyolefin, polyamide, polyurethane, etc. The pre-packaging layer 14 covers the chip 11 and the first connector 13 and the surface of the first redistribution layer 12 facing the chip 11 and the first connector 13, and fills the gap between the chip 11 and the first connector 13; the surface of the first redistribution layer 12 facing away from the chip 11 and the first connector 13 is exposed on the surface of the pre-packaging layer 14, and the surface of the first redistribution layer 12 facing away from the chip 11 and the first connector 13 may be flush with or protrude from the surface of the pre-packaging layer 14.

The first conductive column 131 of the first connector 13 is located in the pre-package layer 14 and penetrates the pre-package layer 14. One end of the first conductive column 131 is connected to the first redistribution layer of the pre-package.

In some embodiments, as shown in FIGS. 5-6 , the first connector 13 of the second pre-package further includes a metal bump 132; the metal bump 132 is electrically connected to the first conductive column 131 and exposed on the outer surface of the pre-package layer 14; the metal bump 132 is electrically connected to the first redistribution layer 12 of the adjacent pre-package.

The metal bump 132 is electrically connected to the end of the first conductive column 131 facing away from the first redistribution wiring layer 12, and protrudes from the surface of the pre-package layer 14 on the side facing away from the first redistribution wiring layer 12, and is electrically connected to the first redistribution wiring layer 12 of the adjacent pre-package body 10. The first conductive column 131 and the metal bump 132 can be made of the same metal material or different metal materials, which is not limited here.

Exemplarily, as shown in FIGS. 1-2 , in a top-down order, the second pre-package is applicable to the 1st to 3rd pre-packages, i.e., pre-packages other than the bottommost pre-package in the fan-out stacked package; in the first preset direction X, the length of the metal bump 132 is greater than the length of the first conductive column 131. This arrangement increases the contact area between the metal bump 132 and the first redistribution layer 12 of the adjacent pre-package, thereby improving the connection reliability and reducing the difficulty of the connection process; wherein the first preset direction X is any direction perpendicular to the stacked interconnection direction.

In some embodiments, the first connector 13 further includes a welding block, which is located at one end of the metal bump 132 away from the first conductive column 131 and forms a cap-shaped bump. The welding block is made of a conductive metal, such as tin.

In some embodiments, as shown in FIGS. 1-2 , the first pre-package further includes a second redistribution layer 15 and a second connector 16; the second redistribution layer 15 is located on a side of the chip 11 and the first conductor post 131 away from the first redistribution layer 12, and the second connector 16 is located on a side of the second redistribution layer 15 away from the chip 11 and the first conductor post 131, the second redistribution layer 15 is electrically connected to the first conductor post 131 and the second connector 16, and the second connector 16 is used to connect to other components externally.

Among them, the first pre-package body refers to the pre-package body 10 located at the bottom of the fan-out type stacked package body in the stacking interconnection direction, and the remaining other pre-package bodies 10 are second pre-package bodies, and the second pre-package bodies are stacked on the top of the first pre-package body; the second redistribution layer 15 and the second connector 16 are sequentially arranged on the side of the first pre-package body away from the second pre-package body, and the second connector 16 is used for external connection with other components, such as substrates, printed circuit boards (Printed Circuit Boards, PCB) or processors. The processor can be a central processing unit (Central Processing Unit, CPU) or other forms of processing units with data processing capabilities and/or instruction execution capabilities.

Since the bottom of the first pre-package is no longer stacked and connected to other pre-packages 10, the first connector 13 of the first pre-package only includes the first conductive column 131 that penetrates the pre-package layer 14, and the metal bump 132 is no longer provided; the second redistribution layer 15 is formed on the side of the first pre-package away from the first redistribution layer 12, the first connector 13 is electrically connected to the second redistribution layer 15, and the second redistribution layer 15 is electrically connected to the second connector 16, and through the first connector 13, the second redistribution layer 15 and the second connector 16, all pre-packages 10 in the stacked package 100 are interconnected with a base (such as a substrate, PCB or CPU).

The second redistribution layer 15 is a metal thin film layer, which can be prepared by electroplating or deposition process; the metal material can be at least one of copper, aluminum, silver, gold, and titanium.

The second connector 16 is configured in a columnar, block or spherical shape, and is made of a conductive material, including a metal material (such as at least one of copper, aluminum, silver, gold and titanium) and a conductive non-metal material. The number and arrangement of the second connectors 16 need to be flexibly configured according to the external components, and are not limited here.

In some embodiments, the second connector is configured as at least one of a second conductive column and a solder ball.

Exemplarily, as shown in FIG. 1 , the second connector 13 is configured as a solder ball, and the solder ball pitch is 0.4 mm; the actual number of the solder balls is 496.

Exemplarily, as shown in FIG. 2 , the second connector is configured as a solder ball, and the solder ball pitch is 0.8 mm; for a DDR4 DRAM chip, the actual number of solder balls is 78; and for a DDR5 DRAM chip, the actual number of solder balls is 82.

It can be understood that FIG. 1-2 only exemplarily shows that the second connector 16 is set as a solder ball, but does not constitute a limitation on the fan-out stacked package provided by the embodiment of the present invention. In other embodiments, the second connector 16 can also be set in other forms known to those skilled in the art, such as a column or a block; the number of the second connectors needs to be set according to the requirements of the fan-out stacked package, which is not limited here.

In some embodiments, as shown in FIGS. 1-2 , the fan-out stacked package 100 further includes: a packaging layer 20, the packaging layer 20 is located on a side of the first pre-package facing the second pre-package, and the packaging layer 20 covers the surface of the first pre-package facing the second pre-package and the second pre-package.

The packaging layer 20 may be made of a prepreg to cover all the second prepackages and the surface of the first prepackage facing the second prepackage, and the prepreg includes one or more combinations of epoxy, polyethylene, polypropylene, polyolefin, polyamide, polyurethane, etc. The packaging layer 20 may also be made of liquid or powder epoxy and other materials, not only covering all the second prepackages and the surface of the first prepackage facing the second prepackage, but also filling all the gaps between the prepackages.

With such a configuration, the fan-out stacked package 100 is packaged and protected to avoid damage caused by external factors (such as liquids and metals), and all pre-packaged packages are fixed to prevent the pre-packaged packages from moving and causing disconnection of the connection circuit.

In some embodiments, as shown in FIGS. 7-11 , the pre-package further includes: a bonding pad 17; the bonding pad 17 is located on the active surface side of the chip 11, the bonding pad 17 is distributed in an area of the chip 11 close to the first connector 13, and the bonding pad 17 is electrically connected to the first connector 13 through the first redistribution layer 12.

In the prior art, the bonding pad 17 is usually arranged at the edge of the chip 11 (as shown in FIG. 3 or 4). If it is applied to the present invention, the vertical interconnection length between the pre-package layers is shortened; however, since the arrangement direction of the bonding pad 17 is perpendicular to the overall arrangement direction of the first connector 13, there is a problem that the length of the first redistribution layer 12 is relatively long. The solution can be further optimized by adjusting the distribution position of the bonding pad 17. The embodiment of the present invention sets the distribution position of the bonding pad 17 according to the distribution position of the first connector 13, so that the bonding pad 17 is distributed in the area of the chip 11 close to the first connector 13, so as to shorten the length of the first redistribution layer 12, that is, shorten the electrical interconnection length, reduce capacitance and inductance, and further improve electrical performance.

Exemplarily, as shown in FIGS. 7-8 , the first connector 13 is distributed in the gap between the two chips 11; the bonding pad 17 is located in the middle area of the chip and arranged in a direction parallel to the two chips 11; such a configuration shortens the length of the first redistribution layer 12.

Exemplarily, as shown in FIG. 9 , the first connector 13 is distributed in the gap between the two chips 11; the bonding pad 17 is located in the middle area of the chip, and gradually approaches the first connector from the inside to the outside along the direction parallel to the two chips 11, gradually shortening the length of the first redistribution layer 12.

Exemplarily, as shown in FIG. 10 , the first connector 13 is distributed in the gap between the two chips 11; the bonding pad 17 is located in the middle area of the chip, and is arranged in parallel to the two chips 11 as a whole. The bonding pad 17 is not aligned, and the length of the first redistribution layer 12 is also shortened.

Exemplarily, as shown in FIG. 11 , the first connector 13 is distributed outside the chip 11; the bonding pad 17 is located in the middle area of the chip and arranged in a direction parallel to the two chips 11; such a configuration shortens the length of the first redistribution layer 12.

Taking the pre-packaged packages shown in FIGS. 7-11 as an example, each pre-packaged package includes two 32-bit dynamic random access memories (DRAMs), the number of bonding pads 17 arranged on the active surface of the chip 11, the number of first redistribution wiring layers 12, and the number of first connectors 13 (i.e., first conductive pillars 131) are all equal, and approximately 400 are required; the diameter of the first conductive pillars 131 is greater than or equal to 25μm, and the spacing is greater than or equal to 40μm; the minimum line width/line spacing of the first redistribution wiring layer 12 is 5μm.

It can be understood that FIGS. 7-11 only exemplarily show the distribution position of the bonding pads 17 on the active side of the chip 11 and the number of the bonding pads 17 being 8, but do not constitute a limitation on the stacked package provided by the embodiment of the present invention. In other embodiments, the distribution position and number of the bonding pads can be flexibly set according to the requirements of the stacked package, which is not limited here.

As shown in Fig. 12, it is a schematic diagram of the structure of another second pre-package provided by an embodiment of the present invention. Referring to Fig. 12, the second pre-package includes a chip 11, and the first connector 13 is located on two opposite sides of the chip 11; 16 bonding pads 17 are arranged on one side of the active surface of the chip 11, and the bonding pads 17 are arranged in two rows along a direction parallel to the side; the bonding pads 17 and the first connector 13 are electrically connected through the first redistribution layer 12. The chip 11 is a double data rate dynamic random access memory (DDR DRAM). The number of bonding pads 17, the number of first redistribution wiring layers 12, and the number of first connectors 13 (i.e., first conductive pillars 131) arranged on the active surface of the chip 11 are all equal. The bottommost pre-packaged package in the stacked package needs to be approximately 400, and the non-bottommost pre-packaged package needs to be approximately 100. The diameter of the first conductive pillar 131 is greater than or equal to 25 μm, and the spacing is greater than or equal to 40 μm. The minimum line width/line spacing of the first redistribution wiring layer 12 is 5 μm.

In some embodiments, the chip includes at least one of a storage chip, a computing chip, a communication chip, a sensing chip, and an energy chip.

For example, as shown in FIGS. 7-11 , the chip 11 in the pre-package is two dynamic random access memory (DRAM); as shown in FIG. 12 , the chip 11 in the pre-package is a double data rate dynamic random access memory (DDR DRAM); the embodiment of the present invention does not limit the type, quantity, and capacity of the packaged chips, and is applicable to all chips in the present technical field.

In some embodiments, as shown in FIGS. 1-2 , the first connectors in two adjacent pre-packaged packages are disposed at the same position.

Exemplarily, as shown in FIGS. 1-2 , in the stacking interconnection direction, the first connectors 13 of two adjacent pre-packaged packages 10 are arranged at the same position, both of which are arranged in the gap between the two chips 11. With this arrangement, the two pre-packaged packages 10 can be interconnected through their respective first redistribution layers 12 and the first connectors 13 therebetween. Compared with a solution in which the first connectors 13 in two adjacent pre-packaged packages 10 are arranged at inconsistent positions, this is conducive to further shortening the length of the first redistribution layer 12, thereby improving the electrical performance.

On the basis of the above-mentioned implementation manner, the embodiment of the present invention also provides a method for preparing a fan-out type stacked package, which is used to prepare any of the above-mentioned fan-out type stacked package and has corresponding beneficial effects. To avoid repeated description, it will not be repeated here.

FIG13 is a schematic diagram of a process of preparing a fan-out type stacked package provided by an embodiment of the present invention. Referring to FIG13 , the method for preparing the fan-out type stacked package includes:

S101, forming at least two pre-packaged bodies.

In combination with Figures 1-2, each pre-package 10 includes a chip 11, a first redistribution layer 12 and a first connector 13; in the stacking interconnection direction, the first redistribution layer 12 is located on one side of the active surface of the chip 11, and the first connector 13 and the chip 11 are located on the same side of the first redistribution layer 12; in the first preset direction X, the first connector 13 is located on at least one side of the chip 11, and the first connector 13 is electrically connected to the first redistribution layer 12.

Among them, the chip 11 includes but is not limited to storage chips, computing chips, sensing chips, communication chips, sensing chips and energy chips. The first redistribution layer 12 is prepared by electroplating or deposition process, and the material of the first redistribution layer 12 can be selected from at least one of copper, aluminum, silver, gold and titanium. The first connector 13 can be set as a metal column or metal block formed by a metal material, such as a copper column, an aluminum column and a silver column, etc., or it can be a columnar body formed by other conductive materials. The first connector 13 and the first redistribution layer 12 can be set to the same material, or the two can be set to different materials.

S102, interconnecting the pre-packaged body stacks.

In which, in combination with Figures 1-2, the active surface of one pre-package 10 of two adjacent pre-packages 10 is opposite to the passive surface of the other pre-package 10, and the first connector 13 of one pre-package 10 is electrically connected to the first redistribution layer 12 of the other pre-package 10; the pre-package 10 includes a first pre-package and at least one second pre-package; the first pre-package is located at the outermost side of the fan-out stack package and is used to be electrically connected to other components; in a first preset direction X, the length of the first pre-package is greater than the length of the second pre-package, and the first preset direction X is any direction perpendicular to the stack interconnection direction. With such arrangement, when the fan-out type stacked package is packaged as a whole, the side of the first pre-package body facing the second pre-package body can be used as a base to provide support for the package layer without the need for a connecting substrate; in any direction perpendicular to the stacked layer interconnection, the length of the first pre-package body is equal to the length of the package layer.

In some embodiments, as shown in FIGS. 14-15 , FIG. 14 is a detailed flow diagram of “forming a pre-package” provided by an embodiment of the present invention, and FIG. 15 is a structural diagram corresponding to each step of “forming a pre-package”. Referring to FIGS. 14 and 15 , “forming a pre-package” includes:

S201, providing a first carrier board.

S202, forming a first conductive column on one side of the first carrier.

The first conductive column 131 can be prepared by electroplating process, or by any process known to those skilled in the art, which is not limited here. The first conductive column 131 can be made of at least one of copper, aluminum, silver, gold, and titanium.

Exemplarily, the first conductive pillar is prepared by an electroplating process, specifically, a light to heat conversion layer (Light To Heat Conversion Release Coating (LTHC) Ink), a polymer layer (such as polyimide), a seed layer (including at least one of copper and titanium) and a photoresist layer are sequentially deposited on one side of a first carrier, a first mask layer for patterning the photoresist layer is placed above the photoresist layer to form a blind hole penetrating the photoresist layer, a first conductive pillar is formed in the blind hole by an electroplating process, and finally the photoresist layer is removed, and then the residual seed layer is removed by etching.

S203, providing at least one chip.

Among them, FIG. 15 only shows two chips 11 by way of example, and the chip type is a dynamic random access memory (DRAM), but it does not constitute a limitation on the method for preparing the stacked package provided by the embodiment of the present invention. In other embodiments, the number and type of chips can be flexibly set according to needs, which is not limited here.

S204, attaching the active surface of the chip to the first carrier board.

Specifically, the chip 11 is attached to the first carrier by using an adhesive, and the active surface of the chip 11 faces the first carrier; the chip 11 and the first conductive pillar 131 are located on the same side of the first carrier.

S205, forming a pre-packaging layer.

Specifically, the chip 11 and the first conductive pillar 131 are plastic-encapsulated with an insulating material (such as epoxy resin) to form a pre-encapsulation layer 14; the pre-encapsulation layer 14 covers the chip 11, the first conductive pillar 131 and the surface of the first carrier facing the chip 11 and the first conductive pillar 131; then the pre-encapsulation layer 14 is thinned by grinding until the first conductive pillar 131 is exposed on the surface of the pre-encapsulation layer 14 on the side away from the first carrier; in this way, the first conductive pillar 131 fills and penetrates the pre-encapsulation layer 14.

S206, providing a second carrier and attaching the second carrier to a side of the pre-packaging layer facing away from the first carrier.

S207, removing the first carrier, and forming a first redistribution layer on a side of the chip and the first conductive pillar facing away from the second carrier.

The first redistribution layer 12 is electrically connected to the chip and the first conductive pillar 131 , that is, the first conductive pillar 131 is electrically connected to the chip 11 through the first redistribution layer 12 .

Specifically, when the first carrier is removed, the light-to-heat conversion layer and the polymer layer deposited on the first carrier when preparing the first conductive pillar 131 and the adhesive used when attaching the chip 11 are removed together. After removing the first carrier, the pre-package is turned upside down, and a first redistribution layer 12 is formed on one side of the active surface of the chip 11 by electroplating or deposition process. The first redistribution layer 12 is electrically connected to the bonding pad of the chip 11 and the first conductive pillar 131.

In some embodiments, as shown in FIGS. 16-17 , FIG. 16 is a detailed flow diagram of “forming a second pre-package” provided by an embodiment of the present invention, and FIG. 17 is a structural diagram corresponding to each step of “forming a second pre-package”. Referring to FIGS. 16 and 17 , “forming a second pre-package” includes:

S308, providing a third carrier and attaching the third carrier to a side of the first redistribution layer away from the chip and the first conductive pillar.

Specifically, the third carrier is attached to the side where the first redistribution layer 12 is located.

S309, removing the second carrier board, and forming a metal bump on a side of the first conductive column away from the third carrier board.

The metal bump 132 is electrically connected to the first conductive column 131 and is exposed outside the surface of the pre-packaging layer 14.

Specifically, after removing the second carrier, a metal bump 132 is formed at one end of the first conductive column 131 away from the first redistribution wiring layer 12 by electroplating; the metal bump 132 can be made of at least one of copper, aluminum, silver, gold, and titanium. Preferably, copper is used for both the first conductive column 131 and the metal bump 132. A cap-shaped solder block is formed at one end of the metal bump 132 away from the first conductive column 131, and the solder block is made of solder.

The pre-package formed by the method of this embodiment is applicable to pre-packages other than the bottom pre-package in the fan-out type stacked package; in conjunction with Figures 1-2, the pre-package formed is three pre-packages located at the top and middle layers of the fan-out type stacked package.

In some embodiments, as shown in FIGS. 18-19, FIG. 18 is a schematic diagram of a process of another method for preparing a fan-out type stacked package provided by an embodiment of the present invention, and FIG. 19 is a schematic diagram of a structure corresponding to S403 to S406 in the method for preparing a fan-out type stacked package shown in FIG. 18. Referring to FIGS. 18-19, after interconnecting the pre-packaged stacks, the preparation method further includes:

S403, forming a packaging layer on a side of the first pre-package body facing the second pre-package body.

The packaging layer 20 covers the surface of the first pre-package body facing the second pre-package body and the second pre-package body. The packaging layer 20 can be made of a prepreg to cover all the second pre-package bodies and the surface of the first pre-package body facing the second pre-package body. The prepreg includes one or more combinations of epoxy resin, polyethylene, polypropylene, polyolefin, polyamide, polyurethane, etc. The packaging layer 20 can also be made of liquid or powder epoxy resin and other materials, which not only covers all the first pre-package bodies and the surface of the first pre-package body facing the second pre-package body, but also fills all the gaps between the pre-package bodies.

In some embodiments, as shown in Figures 18-19, the preparation method further includes:

S404, removing the second carrier board on a side of the first pre-package body away from the second pre-package body.

S405, forming a second redistribution layer on a side of the chip and the first conductive pillar away from the first redistribution layer.

Specifically, after removing the second carrier, a second redistribution layer 15 is formed on a side of the pre-package away from the first redistribution layer 12 by electroplating or deposition process, and the second redistribution layer 15 is electrically connected to the first conductive column 131 of the pre-package; the second redistribution layer 15 can be made of at least one of copper, aluminum, silver, gold, and titanium.

S406, forming a second connector on a side of the second redistribution layer away from the chip and the first conductive pillar.

The second redistribution layer 15 is electrically connected to the first connector 13 and the second connector 16, and the second connector 16 is used to connect to other components.

Specifically, the second connector 16 is prepared by electroplating process, and the second connector 16 can be set to be one of a column, a block or a ball. For example, the second connector 16 in FIG. 18 is set to be a solder ball; the second connector 16 is made of conductive materials, including metal materials (such as at least one of copper, aluminum, silver, gold, and titanium) and conductive non-metallic materials. The number and arrangement of the second connectors 16 need to be flexibly set according to the external components, and are not limited here.

Based on the above implementation, the present invention also provides an electronic device. The electronic device includes: any of the above fan-out stacked packages, which have corresponding beneficial effects and are not limited here to avoid repeated description.

The electronic device includes but is not limited to portable devices (such as laptops), mobile communication devices (such as smart phones and tablets) and computer servers.

It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or apparatus. In the absence of further restrictions, an element defined by the phrase "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or apparatus including the element.

The above is only a specific implementation of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments described herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

100: fan-out stack package 10: pre-package 11: chip 12: first redistribution layer 13: first connector 131: first conductor column 132: metal bump 14: pre-package layer 15: second redistribution layer 16: second connector 17: bonding pad 20: package layer S101: forming at least two pre-packages S102: interconnecting the pre-package stack S201: providing a first carrier S202: forming a first conductor column on one side of the first carrier S203: providing at least one chip S204: attaching the active surface of the chip to the first carrier S205: forming a pre-package layer S206: Provide a second carrier and attach the second carrier to the side of the pre-package layer facing away from the first carrier S207: Remove the first carrier, and form a first redistribution layer on the side of the chip and the first conductor column facing away from the second carrier S308: Provide a third carrier and attach the third carrier to the side of the first redistribution layer facing away from the chip and the first conductor column S309: Remove the second carrier, and form a metal bump on the side of the first conductor column facing away from the third carrier S403: Form a packaging layer on the side of the first pre-package body facing the second pre-package body S404: Remove the second carrier on the side of the first pre-package body facing away from the second pre-package body S405: Form a second redistribution layer on the side of the chip and the first conductor column facing away from the first redistribution layer S406: Form a second connector on the side of the second redistribution layer away from the chip and the first conductor column

[Figure 1] is a schematic diagram of the structure of a fan-out type stacked package provided in an embodiment of the present invention; [Figure 2] is a schematic diagram of the structure of another fan-out type stacked package provided in an embodiment of the present invention; [Figure 3] is a schematic diagram of the structure of a second pre-package provided in an embodiment of the present invention; [Figure 4] is a schematic diagram of the structure of a first pre-package provided in an embodiment of the present invention; [Figure 5] is a schematic diagram of the structure of another second pre-package provided in an embodiment of the present invention; [Figure 6] is a schematic diagram of the structure of another second pre-package provided in an embodiment of the present invention; [Figure 7] is a schematic diagram of the structure of another second pre-package provided in an embodiment of the present invention; [Figure 8] is a schematic diagram of the structure of another first pre-package provided in an embodiment of the present invention; [Figure 9] is a schematic diagram of the structure of another second pre-package provided in an embodiment of the present invention; [Figure 10] is a schematic diagram of the structure of another second pre-package provided in an embodiment of the present invention; [Figure 11] is a schematic diagram of the structure of another second pre-package provided in an embodiment of the present invention; [Figure 12] is a schematic diagram of the structure of another second pre-package provided in an embodiment of the present invention; [Figure 13] is a schematic diagram of the process of preparing a fan-out type stacked package provided in an embodiment of the present invention; [Figure 14] is a detailed schematic diagram of the process of "forming a pre-package" provided in an embodiment of the present invention; [Figure 15] is a schematic diagram of the structure corresponding to each step of "forming a pre-package" in the present invention; [Figure 16] is a detailed schematic diagram of the process of "forming a second pre-package" provided in an embodiment of the present invention; [Figure 17] is a schematic diagram of the structures corresponding to each step of "forming a second pre-package" of the present invention; [Figure 18] is a schematic diagram of the process of another method for preparing a fan-out type stacked package provided by an embodiment of the present invention; [Figure 19] is a schematic diagram of the structures corresponding to S403~S406 in the method for preparing a fan-out type stacked package shown in Figure 18 of the present invention.

100: Fan-out stacked package

10: Pre-packaged

11: Chip

12: First redistribution layer

13: First connector

131: First conductor column

132: Metal bump

14: Pre-packaging layer

15: Second redistribution layer

16: Second connector

20: Packaging layer

Claims (14)

A fan-out stacked package, comprising: at least two pre-packages; each of the pre-packages at least comprises a chip, a first redistribution layer, a first connector and a pre-package layer, the pre-package layer covers the chip and the first connector, the first connector comprises a first conductor column; the at least two pre-packages are stacked and interconnected, the active surface of one of the two adjacent pre-packages is opposite to the passive surface of the other pre-package, the first connector of one of the pre-packages is electrically connected to the first redistribution layer of the other pre-package; in the stacking interconnection direction, the first redistribution layer is located on one side of the active surface of the chip, and the first connector and the chip are located on the same side of the first redistribution layer; In the first preset direction, the first connector is located on at least one side of the chip, and the first connector is electrically connected to the chip through the first redistribution layer; the pre-package includes a first pre-package and at least one second pre-package; the first pre-package is located at the outermost side of the fan-out stacked package, and is used to be electrically connected to other electronic components; in the first preset direction, the length of the first pre-package is greater than the length of the second pre-package, and the first preset direction is any direction perpendicular to the stacking interconnection direction, and the first connector of the second pre-package also includes a metal bump; the metal bump is electrically connected to the first conductor column and exposed on the outer surface of the pre-package layer; the metal bump is electrically connected to the first redistribution layer of the adjacent pre-package. A fan-out stacked package as described in claim 1, wherein the first conductive column fills and penetrates the pre-package layer to connect the first redistribution layer of the pre-package. The fan-out stacked package as described in claim 2, wherein the first pre-package further includes a second redistribution layer and a second connector; the second redistribution layer is located on a side of the chip and the first conductive column away from the first redistribution layer, the second connector is located on a side of the second redistribution layer away from the chip and the first conductive column, the second redistribution layer is electrically connected to the first conductive column and the second connector, and the second connector is used to connect other electronic components. A fan-out stacked package as described in claim 3, wherein the second connector is configured as at least one of a second conductive column and a solder ball. The fan-out stacked package as described in claim 1, further comprising: a packaging layer, the packaging layer is located on the side of the first pre-package body facing the second pre-package body, and the packaging layer covers the surface of the first pre-package body facing the second pre-package body and the second pre-package body. A fan-out stacked package as described in any one of claim items 1 to 5, wherein the pre-package further comprises: a bonding pad; the bonding pad is located on the active side of the chip, the bonding pad is distributed in the area of the chip close to the first connector, and the bonding pad is electrically connected to the first connector through the first redistribution layer. A fan-out stacked package as described in claim 1, wherein the chip includes at least one of a storage chip, a computing chip, a communication chip, a sensing chip, and an energy chip. A fan-out stacked package as described in claim 1, wherein the first connectors in two adjacent pre-packages are arranged at the same position. A method for preparing a fan-out stacked package, comprising: forming at least two pre-packages; the pre-packages at least comprising a chip, a first redistribution layer and a first connector; interconnecting the pre-packages, wherein the active surface of one of the two adjacent pre-packages faces the passive surface of the other pre-package, wherein the first connector of one pre-package is electrically connected to the first redistribution layer of the other pre-package; wherein in the stacked interconnection direction, the first redistribution layer is located on one side of the active surface of the chip, and the first connector is electrically connected to the first redistribution layer of the other pre-package. The chip is located on the same side of the first redistribution layer; in a first preset direction, the first connector is located on at least one side of the chip, and the first connector is electrically connected to the chip through the first redistribution layer; the pre-package includes a first pre-package and at least one second pre-package; the first pre-package is located at the outermost side of the fan-out stacked package, and is used to be electrically connected to other electronic components; in the first preset direction, the length of the first pre-package is greater than the length of the second pre-package, and the first preset direction is any direction perpendicular to the stacking interconnection direction. The preparation method as described in claim 9, wherein forming the pre-package body comprises: providing a first carrier; forming a first conductive column on one side of the first carrier; providing at least one chip; attaching the active surface of the chip to the first carrier; the chip and the first conductive column are located on the same side of the first carrier; forming a pre-package layer, the pre-package layer covers the chip, the first conductive column and the surface of the first carrier facing the chip and the first conductive column, the first conductive column fills and penetrates the pre-package layer; providing a second carrier and attaching the second carrier to the side of the pre-package layer away from the first carrier; removing the first carrier, and forming a first redistribution layer on the side of the chip and the first conductive column away from the second carrier, the first redistribution layer is electrically connected to the chip and the first conductive column. The preparation method as described in claim 10, wherein forming the second pre-package further comprises: providing a third carrier and attaching the third carrier to a side of the first redistribution layer away from the chip and the first conductive column; removing the second carrier, and forming a metal bump on a side of the first conductive column away from the third carrier, wherein the metal bump is electrically connected to the first conductive column and exposed outside the surface of the pre-package layer. The preparation method as described in claim 11, wherein after the pre-packaged bodies are stacked and interconnected, the preparation method further comprises: forming a packaging layer on the side of the first pre-packaged body facing the second pre-packaged body; the packaging layer covers the surface of the first pre-packaged body facing the second pre-packaged body and the second pre-packaged body. The preparation method as described in claim 12, further comprising: removing the second carrier on the side of the first pre-package body away from the second pre-package body; forming a second redistribution layer on the side of the chip and the first conductive column away from the first redistribution layer; forming a second connector on the side of the second redistribution layer away from the chip and the first conductive column; wherein the second redistribution layer is electrically connected to the first connector and the second connector, and the second connector is used to connect other electronic components. An electronic device, comprising: a fan-out stacked package as described in any one of claim items 1-8.

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