TWI869032B - Three-dimensional semiconductor storage device and method for forming the same - Google Patents

Abstract

The present disclosure provides a three-dimensional semiconductor storage device and a method for forming the same, the method comprising: forming a stacking structure on a substrate, and forming an isolation structure in the stacking structure; the isolation structure separates the stacking structure into a conductive line region and a storage region; etching the isolation structure to form a plurality of first openings exposing a capacitor region in the storage region and the substrate; the bottom surface of the first opening is lower than the top surface of the substrate; forming capacitor structures arranged in an array along a first direction and a second direction in the capacitor region; the first electrode of the capacitor structure is exposed in the first opening; and forming a common terminal lead-out structure in the first opening to electrically connect the first electrode of the capacitor structure to the substrate. The present invention forms a common terminal lead-out structure to electrically connect the common electrode of the capacitor structure in the three-dimensional semiconductor storage device to the substrate, and provides a common power supply to the capacitor structure through the substrate, which can reduce the number of power supply pads required for the key interface and effectively improve the integration of the three-dimensional semiconductor storage device.

Description

Three-dimensional semiconductor storage device and method for forming the same

The present disclosure relates to the field of semiconductor technology, and more particularly to a three-dimensional semiconductor storage device and a method for forming the same.

The integration level of a two-dimensional semiconductor storage device is mainly determined by the area occupied by the storage unit, and therefore its integration level is largely affected by the level of fine pattern formation technology. In order to overcome the limitation of the fine pattern technology level on the integration level of semiconductor storage devices, a three-dimensional semiconductor storage device including three-dimensionally arranged storage units has recently been proposed.

However, traditional three-dimensional semiconductor storage devices and their formation methods still have certain defects. How to further improve the integration and reliability of three-dimensional semiconductor storage devices has become a problem that urgently needs to be solved.

In view of this, the present disclosure provides a three-dimensional semiconductor storage device and a method for forming the same to solve at least one problem existing in the prior art.

To achieve the above purpose, the technical solution of the disclosed embodiment is implemented as follows:

In a first aspect, the disclosed embodiment provides a method for forming a three-dimensional semiconductor storage device, the method comprising:

A storage stack structure is formed on a substrate, and an isolation structure is formed in the storage stack structure; the isolation structure separates the storage stack structure into a conductive line region and a storage region;

Etching the isolation structure to form a plurality of first openings exposing the capacitor region in the storage region and the substrate; the bottom surface of the first opening is lower than the top surface of the substrate;

A capacitor structure arranged in an array along a first direction and a second direction is formed in the capacitor region; a first electrode of the capacitor structure is exposed in the first opening; and the capacitor structure extends along a third direction;

A common terminal lead-out structure is formed in the first opening to electrically connect the first electrode of the capacitor structure to the substrate.

In an optional implementation manner, before the capacitor region forms the capacitor structure arranged in array along the first direction and the second direction, the method further includes:

An active structure arranged in an array along the first direction and the second direction is formed in the transistor region in the storage region; the active structure extends along a third direction, and the active structure includes a first source/drain region, a channel region and a second source/drain region; the second electrode of the capacitor structure is electrically connected to the first source/drain region in the active structure.

In an optional implementation, the method for forming the three-dimensional semiconductor storage device further comprises:

The isolation structure is etched to form a second opening exposing the channel region; the isolation structure between the bottom of the second opening and the substrate forms a shallow trench isolation structure; the thickness of the shallow trench isolation structure in the first direction is greater than the thickness of the initial oxide layer between the substrate and the storage stack structure;

forming a word line structure extending along the first direction in the second opening;

A bit line structure is formed in the conductive line region, which is arranged along the first direction, extends along the second direction, and is electrically connected to the second source/drain region.

In an optional implementation, the method for forming the three-dimensional semiconductor storage device further comprises:

The isolation structure is etched to form a third opening exposing the second source/drain region; the isolation structure between the bottom of the third opening and the substrate forms a shallow trench isolation structure; the thickness of the shallow trench isolation structure in the first direction is greater than the thickness of the initial oxide layer between the substrate and the storage stack structure;

forming a plurality of bit line structures extending along the first direction in the third opening, wherein the bit line structures are electrically connected to the second source/drain region;

A word line structure is formed in the conductive line region, which is arranged along the first direction, extends along the second direction, and is located on both sides of the channel region.

In an optional implementation manner, the capacitor structure is symmetrically distributed on both sides of the bit line structure along the third direction; or, the capacitor structure is distributed on one side of the bit line structure.

In an optional implementation manner, the common terminal lead-out structure formed in the first opening to electrically connect the first electrode of the capacitor structure to the substrate includes:

forming a metal silicide layer and an adhesive layer in sequence on the surface of the substrate exposed by the first opening;

The conductive material is deposited on the adhesive layer to fill the first opening; the conductive material includes polysilicon.

In an optional implementation, the forming of an isolation structure in the storage stack structure includes:

Etching the initial stacking structure in the first direction to form a plurality of isolation trenches penetrating the initial stacking structure and exposing the substrate;

The isolation trench is filled with an insulating material to form the isolation structure.

In an optional implementation, the storage stack structure includes dielectric layers and semiconductor layers alternately stacked along the first direction; the capacitor structure arranged in array along the first direction and the second direction formed in the capacitor region includes:

Etching the dielectric layer in the third direction to form a fourth opening of the semiconductor layer exposing the capacitor region, wherein the fourth opening is connected to the first opening;

The second electrode, the capacitor dielectric layer and the first electrode of the capacitor structure are sequentially formed on the surface of the semiconductor layer exposed by the first opening and the fourth opening.

In an optional implementation manner, forming a common terminal lead-out structure in the first opening to electrically connect the first electrode of the capacitor structure to the substrate includes:

The conductive material is filled in the first opening and between the capacitor structures to form the common terminal lead-out structure.

In a second aspect, the disclosed embodiment provides a three-dimensional semiconductor storage device, the three-dimensional semiconductor storage device comprising:

lining;

a storage structure located on the liner;

The storage structure includes capacitor structures arranged in an array along a first direction and a second direction; the capacitor structures extend along a third direction; the first direction is a thickness direction of the substrate, and the second direction and the third direction are both perpendicular to the first direction;

A common terminal lead-out structure, the bottom surface of which is lower than the top surface of the substrate; the common terminal lead-out structure is electrically connected to the first electrode of the capacitor structure and the substrate.

In an optional implementation, the storage structure further includes:

An active structure extending along the third direction; the active structure comprises a first source/drain region, a channel region and a second source/drain region arranged in sequence along the third direction; the second electrode of the capacitor structure is electrically connected to the first source/drain region.

In an optional implementation, the three-dimensional semiconductor storage device further comprises:

A word line structure extending along the first direction; the word line structure is located on two opposite sides of the channel region along the second direction;

A shallow trench isolation structure is located between the word line structure and the substrate; the thickness of the shallow trench isolation structure in the first direction is greater than the thickness of the initial oxide layer; the initial oxide layer is located between the substrate and the storage structure;

The bit line structure is arranged along the first direction, extends along the second direction, and is electrically connected to the second source/drain region.

In an optional implementation, the three-dimensional semiconductor storage device further comprises:

A bit line structure extending along the first direction; the bit line structure is electrically connected to the second source/drain region;

A shallow trench isolation structure is located between the bottom of the bit line structure and the substrate; the thickness of the shallow trench isolation structure in the first direction is greater than the thickness of the initial oxide layer; the initial oxide layer is located between the substrate and the storage structure;

The word line structure is arranged along the first direction, extends along the second direction, and is located at both sides of the channel region.

In an optional implementation manner, the capacitor structure is symmetrically distributed on both sides of the bit line structure along the third direction; or, the capacitor structure is located on one side of the bit line structure.

In an optional implementation, the three-dimensional semiconductor storage device further comprises:

A metal silicide layer is located between the common terminal lead structure and the substrate;

The bonding layer is located between the common terminal lead-out structure and the metal silicide layer; the material of the common terminal lead-out structure includes polysilicon.

In the technical solution provided in the present disclosure, the common electrode of the capacitor structure in the three-dimensional semiconductor storage device is electrically connected to the substrate by forming a common terminal lead-out structure, so that a common voltage can be provided to the capacitor structure through the substrate, thereby reducing the number of power supply pads required for the key interface and effectively improving the integration of the three-dimensional semiconductor storage device.

The following will describe in more detail exemplary embodiments of the present disclosure with reference to the attached drawings. Although exemplary embodiments of the present disclosure are shown in the attached drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those of ordinary skill in the art.

In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those of ordinary skill in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

In the accompanying drawings, the sizes of layers, regions, and components as well as their relative sizes may be exaggerated for clarity. The same accompanying drawing reference numerals throughout represent the same components.

It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the attached figures is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

The terms used herein are intended only to describe specific embodiments and are not intended to be limiting of the present disclosure. When used herein, the singular forms "a", "an", and "said/the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and/or "comprising", when used in this specification, identify the presence of the features, integers, steps, operations, elements, and/or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups. When used herein, the term "and/or" includes any and all combinations of the relevant listed items.

In order to improve the storage capacity of semiconductor storage devices, three-dimensional semiconductor storage devices including three-dimensionally arranged storage units have been proposed. The storage array and peripheral circuit of the three-dimensional semiconductor storage device can be formed in different wafers respectively, and a wafer bonding structure is formed through wafer bonding technology, thereby effectively improving the integration of the semiconductor storage device. In the currently proposed wafer bonding structure, the bonding interface on the storage array wafer includes a plurality of bonding pads for wafer bonding and a plurality of power supply pads for providing a common voltage to a common electrode of a capacitor structure. As the number of capacitor structures in the storage array increases, the density of pads set on the bonding interface also increases, resulting in a larger parasitic capacitance of the bonding interface, which will have a negative impact on the signal transmission between the storage array and the peripheral circuit. At the same time, due to the limited area of the bonding interface, the number of pads set on the bonding interface is also limited, which limits the improvement of the integration of three-dimensional semiconductor storage devices.

In addition, in the currently proposed three-dimensional semiconductor storage device formation method, a word line structure or a bit line structure perpendicular to the substrate is usually formed by forming a word line opening or a bit line opening in a stacked structure and then filling the opening with a conductive material. However, since the thickness of the initial oxide layer between the stacked structure and the substrate is relatively small, this formation method has the risk of penetrating the initial oxide layer and causing leakage between the word line structure or the bit line structure and the substrate.

Therefore, it is necessary to further improve the integration and reliability of three-dimensional semiconductor storage devices. In this regard, the present disclosure proposes the following implementation methods.

The disclosed embodiment provides a method for forming a three-dimensional semiconductor storage device. FIG. 1 is a schematic flow chart of the method for forming a three-dimensional semiconductor storage device provided by the disclosed embodiment. As shown in FIG. 1 , the method for forming a three-dimensional semiconductor storage device includes the following steps:

Step 101: forming a storage stack structure on a substrate, and forming an isolation structure in the storage stack structure; the isolation structure separates the storage stack structure into a conductive line region and a storage region;

Step 102: etching the isolation structure to form a plurality of first openings exposing the capacitor region in the storage region and the substrate; the bottom surface of the first opening is lower than the top surface of the substrate;

Step 103: forming capacitor structures arranged in an array along a first direction and a second direction in the capacitor region; a first electrode of the capacitor structure is exposed in the first opening; and the capacitor structure extends along a third direction;

Step 104: forming a common terminal lead structure in the first opening to electrically connect the first electrode of the capacitor structure to the substrate.

Figures 2a to 2r are schematic diagrams of the structure of the three-dimensional semiconductor storage device forming process provided by the disclosed embodiment. Next, the method for forming the three-dimensional semiconductor storage device provided by the disclosed embodiment will be described in detail in conjunction with Figures 1 and 2a to 2r.

In some embodiments, referring to FIG. 2a , a method for forming a three-dimensional semiconductor storage device includes: forming an initial stacking structure on a substrate 201 .

In some embodiments, the substrate 201 may be a single semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

In some embodiments, the substrate 201 is a P-type substrate or an N-type substrate.

In the disclosed embodiment, before forming the storage stack structure on the substrate 201, an initial oxide layer 202 is first formed on the substrate 201, and then an initial stack structure is formed on the initial oxide layer 202. The initial stack structure includes semiconductor layers 203 and sacrificial layers 204 alternately stacked in a first direction. The semiconductor layer 203 can be formed of semiconductor materials such as silicon, germanium, or indium gallium zinc oxide, and the sacrificial layer 204 can be formed of a material having a higher etching selectivity ratio relative to the semiconductor layer 203, for example, the sacrificial layer 203 can be formed of germanium silicon.

In some embodiments, after forming the storage stack structure on the substrate 201, the initial stack structure includes semiconductor layers 203 and sacrificial layers 204 alternately stacked in a first direction, including removing the sacrificial layer 204 to expose the surface of the substrate 201, and then forming an initial oxide layer 202 on the surface of the substrate 201.

In the disclosed embodiment, the first direction is the thickness direction of the substrate 201, i.e., the Z direction, the second direction is the Y direction, and the third direction is the X direction. Both the second direction and the third direction are perpendicular to the first direction, and the second direction and the third direction are parallel to the top surface of the substrate.

In some embodiments, in combination with FIG. 2a and FIG. 2b , the method for forming a three-dimensional semiconductor storage device further includes: etching the initial stacking structure and the substrate 201 in a first direction to form a plurality of isolation trenches 205 penetrating the initial stacking structure and extending into the substrate 201 .

It should be noted that FIG2b only takes the formation of four isolation trenches 205 in the initial stacking structure as an example, but the disclosed embodiment is not limited thereto. For example, it is also possible to form multiple isolation trenches 205 on only one side. The structure in FIG2c is a portion of the structure in FIG2b. In order to facilitate observation of the structure formed by subsequent steps, the subsequent steps are described below based on the structure in FIG2c.

In some embodiments, in combination with FIG. 2c and FIG. 2d, the method for forming a three-dimensional semiconductor storage device further includes: after forming a plurality of isolation trenches 205 in the initial stacking structure, replacing the sacrificial layer 204 with a dielectric material to form a storage stacking structure in which semiconductor layers 203 and dielectric layers 206 are alternately stacked in a first direction. As shown in FIG. 2d, the isolation trenches 205 separate the storage stacking structure into a conductive line region and a storage region, the conductive line region extends along the second direction, and the storage region is located on opposite sides of the conductive line region along the third direction. The conductive line region is a region where the bit line structure is formed, and the storage region is a region where the storage unit is formed. The storage unit includes a transistor structure and a capacitor structure. The storage region includes two parts that are symmetrically distributed relative to the conductive line region, and each part includes a transistor region connected to the conductive line region and a capacitor region far away from the conductive line region.

In some embodiments, the method for forming a three-dimensional semiconductor storage device further includes: forming an active structure in the semiconductor layer 203 extending along the third direction in the transistor region by ion implantation, each active structure including a first source/drain region 207, a channel region 208, and a second source/drain region 209. The first source/drain region 207 is used as one of the source region or the drain region, and the second source/drain region 209 is used as the other of the source region or the drain region. As shown in FIG. 2d, the active structure is arranged symmetrically relative to the conductive line region extending along the second direction, wherein the active structure located on one side of the conductive line region includes a first source/drain region 207, a channel region 208, and a second source/drain region 209 arranged in sequence along the third direction, and the active structure located on the other side of the conductive line region includes a second source/drain region 209, a channel region 208, and a first source/drain region 207 arranged in sequence along the third direction.

In one specific example, the first source/drain region 207 and the second source/drain region 209 in the active structure are N-type doped, and the channel region 208 is P-type doped. In another specific example, the first source/drain region 207 and the second source/drain region 209 in the active structure are P-type doped, and the channel region 208 is N-type doped.

In some embodiments, in combination with FIG. 2d and FIG. 2e , the method for forming a three-dimensional semiconductor storage device further includes: filling the plurality of isolation trenches 205 with an insulating material to form a plurality of isolation structures 210 .

In some other embodiments, the substrate exposed by the isolation trench 205 may be oxidized by a thermal oxidation process, and then the remaining portion of the isolation trench 205 may be filled with an insulating material to form a plurality of isolation structures 210.

It should be noted that one of the four isolation structures 210 shown in the figure is a see-through effect, which is convenient for observing the structure formed through subsequent steps.

In one specific example, an insulating material may be deposited in the isolation trench 205 by low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) to form the isolation structure 210, and the insulating material includes silicon oxide. In another specific example, after the substrate 201 exposed by the isolation trench 205 is oxidized by a thermal oxidation process, the remaining portion of the isolation trench 205 may be filled with an insulating material to form the isolation structure 210.

In some embodiments, in combination with FIG. 2e and FIG. 2f, the method for forming a three-dimensional semiconductor storage device further includes: etching each isolation structure 210 in the first direction and stopping in the isolation structure 210 to form a second opening 211 exposing a plurality of channel regions 208 in the transistor region, the bottom surface of the second opening 211 may be lower than the bottom surface of the bottommost semiconductor layer 203, and the bottom surface of the second opening 211 may also be higher than the top surface of the substrate 201. Referring to FIG. 2f, two rows of active structures arranged in the first direction are formed in the three-dimensional semiconductor storage device, and in the second direction, the second opening 211 is located on both sides of the channel region 208 in each row of active structures.

FIG2g is a cross-sectional view of FIG2f along line AA′. As shown in FIG2g, after etching the isolation structure 210 in the first direction, the remaining isolation structure between the bottom of the second opening 211 and the substrate 201 forms a shallow trench isolation structure 212. The thickness T1 of the shallow trench isolation structure 212 in the first direction is greater than the thickness T2 of the initial oxide layer 202 between the substrate and the storage stack structure.

In some embodiments, in combination with FIG. 2f and FIG. 2h, the method for forming a three-dimensional semiconductor storage device further includes: filling the second opening 211 with a conductive material to form a word line structure 213 extending along the first direction on the shallow trench isolation structure 212. FIG. 2i is a cross-sectional view of FIG. 2h along line AA′. As shown in FIG. 2i, in a specific example, a gate dielectric layer 214 is first formed in the second opening 211 near one side of the channel region 208, and then a conductive material is filled in the second opening 211 to form the word line structure 213. A shallow trench isolation structure 212 is formed between the bottom of the word line structure 213 and the substrate 201, and its thickness T1 in the first direction is greater than the thickness T2 of the initial oxide layer 202. In one specific example, the thickness T1 of the shallow trench isolation structure 212 in the first direction is three times the thickness T2 of the initial oxide layer 202. In another specific example, the thickness T1 of the shallow trench isolation structure 212 in the first direction is six times the thickness T2 of the initial oxide layer 202.

In some embodiments, the method for forming a three-dimensional semiconductor storage device further includes: removing the dielectric layer 206 of the channel region 208 exposed by the second opening 211 to obtain a suspended semiconductor layer 203, forming a gate dielectric layer 214 on the periphery of the channel region 208 exposed by the semiconductor layer 203, and then filling a conductive material to form a word line structure 213. The word line structure 213 can also be located between the semiconductor layers 203 in the first direction.

In the present disclosed embodiment, an active structure is formed in the semiconductor layer 203 in the transistor region, and the active structure includes a first source/drain region 207, a channel region 208, and a second source/drain region 209. A word line structure 213 extending along a first direction is formed next to the channel region 208 as a gate of the transistor structure. Thus, a transistor structure is formed in the transistor region, and multiple transistor structures with the same word line structure 213 as a gate are arranged along the first direction.

In the currently proposed method for forming a three-dimensional semiconductor storage device, a method of etching a stacked structure is usually adopted to form a word line opening. However, since the thickness of the initial oxide layer on the substrate is relatively small, the initial oxide layer may be penetrated during the etching process of the stacked structure, thereby causing leakage between the word line structure and the substrate.

In the disclosed embodiment, an isolation structure 210 extending into the substrate 201 is first formed in the storage stack structure, and then the isolation structure 210 is etched in the first direction to form a second opening 211. The isolation structure between the bottom of the second opening 211 and the substrate 201 forms a shallow trench isolation structure 212. The thickness T1 of the shallow trench isolation structure 212 in the first direction is greater than the thickness T2 of the initial oxide layer 201. 02, and then fill the second opening 211 with a conductive material to form a word line structure 213 on the shallow trench isolation structure 212. As a result, the shallow trench isolation structure 212 between the bottom of the word line structure 213 and the substrate 201 has a greater thickness, thereby preventing leakage between the word line structure 213 and the substrate 201, thereby effectively improving the reliability of the three-dimensional semiconductor storage device.

In some embodiments, the conductive material forming the word line structure 213 may be one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). The gate dielectric layer 214 may be formed of or include at least one of a high dielectric constant material, silicon oxide, silicon nitride, and silicon oxynitride. Among them, the high dielectric constant material may include at least one of tantalum oxide, tantalum oxide silicon, tantalum oxide, zirconia, zirconia silicon, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead tantalum oxide and lead zinc niobate.

In some embodiments, as shown in FIG. 2j, the method for forming a three-dimensional semiconductor storage device further includes: forming a plurality of bit line structures 220 in the conductive line region extending along the second direction. The bit line structures 220 extend along the second direction, are alternately arranged with the dielectric layer 206 in the first direction, and are electrically connected to the drain regions 209 on both sides of the conductive line region. The extending directions of the bit line structures 220 and the word line structures 213 are perpendicular to each other. For an active structure, its channel region 208 is connected to a word line structure 213 extending along the first direction, and its drain region 209 is connected to a bit line structure 220 extending along the second direction.

In a specific example, in combination with FIG. 2h and FIG. 2j, the step of forming the bit line structure 220 includes: etching the conductive line region along the second direction to remove the semiconductor layer 203 extending along the second direction in the conductive line region, and filling the openings produced by etching with a conductive material to form a plurality of bit line structures 220 extending along the second direction.

In the disclosed embodiment, an isotropic etching process is used to form an opening extending along a certain direction in an isolation structure or a stacking structure.

In some embodiments, in combination with FIG. 2j and FIG. 2k , the method for forming a three-dimensional semiconductor storage device further includes: etching the isolation structure 210 in a first direction to form a plurality of first openings 240 exposing the capacitor region and the substrate 201 in the storage region, wherein the bottom surface of the first opening 240 is lower than the top surface of the substrate 201 below the isolation structure 210; etching the dielectric layer 206 extending along the third direction in the capacitor region through the first openings 240 to form a plurality of fourth openings 230, wherein the fourth openings 230 are connected to the first openings 240.

In some embodiments, as shown in FIG. 21 , the method for forming a three-dimensional semiconductor storage device further includes: after forming the fourth opening 230 and the first opening 240, forming a capacitor structure 231 on the surface of the semiconductor layer 203 exposed by the fourth opening 230 and the first opening 240, and the capacitor structure 231 is symmetrically distributed on both sides of the bit line structure 220 along the third direction.

It should be noted that the disclosed embodiment is only described by taking the capacitor structure 231 as being electrically connected to the first source/drain region 207 and the bit line structure 220 as being electrically connected to the second source/drain region 209. In some embodiments, the second source/drain region may be electrically connected to the capacitor structure and the first source/drain region may be electrically connected to the bit line structure.

In a specific example, the cross section of the capacitor structure 231 shown in FIG21 is shown in FIG2m, and the step of forming the capacitor structure 231 includes: the first source/drain region 207 surrounding the end of the semiconductor layer sequentially forms the second electrode 2311, the capacitor dielectric layer 2312 and the first electrode 2313 of the capacitor structure 231. The second electrode 2311 is electrically connected to the first source/drain region 207. In another specific example, the cross section of the capacitor structure 231 is shown in FIG. 2n , and the steps of forming the capacitor structure 231 include: etching the semiconductor material layer 203 extending along the third direction in the capacitor region to form a plurality of capacitor openings; sequentially forming the second electrode 2314, the capacitor dielectric layer 2315 and the first electrode 2316 of the capacitor structure 231 in the capacitor openings; the second electrode 2314 is electrically connected to the first source/drain region 207. After the capacitor structure 231 is formed, the isolation structure 210 is etched in the first direction to form a first opening exposing the capacitor structure 231 and the substrate 201.

It should be noted that in the embodiments of the present disclosure, the fourth opening 230 and the first opening 240 may be formed first, and then the capacitor structure shown in FIG. 2m may be formed, or the capacitor opening and the capacitor structure shown in FIG. 2n may be formed first, and then the first opening 240 may be formed. The present disclosure does not limit this. In the following embodiments, the subsequent steps are described by taking the formation of the capacitor structure shown in FIG. 2m as an example.

In the disclosed embodiment, a capacitor structure 231 is formed in the capacitor region in the storage region, and the second electrode 2311 of the capacitor structure 231 is electrically connected to the first source/drain region 207 of the transistor structure located in the same semiconductor layer 203. Thus, one capacitor structure 231 corresponds to one transistor structure electrically connected thereto, thereby forming a storage unit. The storage units are arranged in an array along the first direction and the second direction, and together form a storage structure in a three-dimensional semiconductor storage device.

In some embodiments, in combination with FIG. 21 and FIG. 20 , the method for forming a three-dimensional semiconductor storage device further includes: filling a plurality of first openings 240 with a conductive material to form a common terminal lead-out structure 241, wherein the common terminal lead-out structure 241 electrically connects the first electrode of the capacitor structure 231 to the substrate 201. The bottom surface of the common terminal lead-out structure 241 may be flush with the bottom surfaces of the isolation structure 210 and the shallow trench isolation structure 212.

In a specific example, Figure 2p is a cross-sectional view of Figure 2o along line BB′. As shown in Figure 2p, the step of forming a common end lead-out structure 241 also includes: while filling the plurality of first openings 240 with a conductive material, filling the remaining portions of the plurality of fourth openings 230 with a conductive material, thereby, the common end lead-out structure 241 also includes a portion 241′ located between the two capacitor structures 231 in the first direction and extending along the third direction.

In a specific example, in combination with FIG. 21 and FIG. 2q, the step of forming the common terminal lead-out structure 241 further includes: forming a metal silicide layer 242 and an adhesive layer 243 in sequence on the substrate surface exposed by the first opening 240, and depositing a conductive material on the adhesive layer 243 to fill the first opening 240. The metal silicide layer 242 and the adhesive layer 243 can effectively reduce the contact resistance between the common terminal lead-out structure 241 and the substrate 201. The bottom surface of the metal silicide layer 242 can be flush with the bottom surfaces of the isolation structure 210 and the shallow trench isolation structure 212.

In the disclosed embodiment, the conductive material forming the common terminal lead-out structure 241 may be a doped semiconductor material (e.g., doped polysilicon, doped germanium silicon, etc.); the material of the metal silicide layer 242 may be tungsten silicide, cobalt silicide, titanium silicide, etc.; the material of the adhesive layer 243 may be a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

In the disclosed embodiment, the common electrode of the capacitor structure is electrically connected to the substrate by forming a common terminal lead-out structure, so that a common voltage can be provided to the common electrode of the capacitor structure through the substrate. Therefore, in the process of forming the back-end interconnect layer, it is not necessary to set a power supply pad for providing a common voltage to the common electrode of the capacitor structure in the bonding interface on the storage array wafer, so that the density of the pads in the bonding interface can be reduced and the parasitic capacitance between the pads can be reduced. In addition, when the pad density in the bonding interface remains unchanged, the density of the capacitor structure in the storage array can be further increased, thereby improving the integration of the three-dimensional semiconductor storage device.

In the disclosed embodiment, the common voltage may be half of the power voltage, that is, VCC/2.

In some embodiments, the three-dimensional semiconductor storage device finally formed by the above method is shown in FIG. 2r. The three-dimensional semiconductor storage device includes a plurality of three-dimensional structures shown in FIG. 2o. The storage structures are symmetrically distributed on both sides of the bit line structure 220. The storage structure includes storage units composed of a transistor structure and a capacitor structure 231. The storage units are arranged in an array along a first direction and a second direction. A shallow trench isolation structure 212 is formed between the word line structure 213 and the substrate 201. The thickness T1 of the trench isolation structure 212 in the first direction is greater than the thickness T2 of the initial oxide layer 202. The common terminal lead-out structure 241 electrically connects the first electrodes 2313 of the plurality of capacitor structures 231 to the substrate 201.

In some embodiments, the thickness T1 of the shallow trench isolation structure 212 between the bottom of the word line structure 213 and the substrate 201 in the first direction is greater than the maximum distance between the storage structure and the substrate 201. Here, the maximum distance between the storage structure and the substrate 201 may be the distance between the bottom of the active structure closest to the substrate 201 and the substrate 201. Thus, leakage between the word line structure 213 and the substrate 201 can be effectively prevented.

In some embodiments, a three-dimensional semiconductor storage device as shown in FIG3 can also be formed by a method similar to the above-mentioned method for forming the three-dimensional semiconductor storage device. In the process of forming the three-dimensional semiconductor storage device, a storage unit including a transistor structure and a capacitor structure 331 is formed on the same side of the bit line structure 320, and the active structure in the transistor structure includes a second source/drain region 309, a channel region 308, and a first source/drain region 307 arranged in sequence along the third direction. The process of forming the three-dimensional semiconductor storage device is similar to the process of forming the three-dimensional semiconductor storage device shown in FIG2q, so the process of forming the three-dimensional semiconductor storage device will not be described in detail.

4a to 4j are schematic diagrams of the structure of the three-dimensional semiconductor storage device forming process provided by another embodiment of the present disclosure. Next, the differences between the three-dimensional semiconductor storage device forming method provided by another embodiment of the present disclosure and the three-dimensional semiconductor storage device forming method shown in FIGS. 2a to 2r will be described in conjunction with FIGS. 1 and 4a to 4j.

It should be noted that, in order to facilitate observation of the formation process of the three-dimensional semiconductor storage device, the structures shown in FIG. 4a to FIG. 4j are only partial structures of the three-dimensional semiconductor storage device.

In some embodiments, referring to FIG. 4a, a method for forming a three-dimensional semiconductor storage device includes: forming an initial stacking structure on a substrate 401; forming a plurality of isolation trenches 405 and 405′ penetrating the initial stacking structure and extending into the substrate 401; and replacing the sacrificial layer in the initial stacking structure with a dielectric layer 406 to form a storage stacking structure. The isolation trenches 405 and 405′ extend into the substrate 401, separating the storage stacking structure into two mutually symmetrical parts, each of which includes a storage region and a conductive line region. The conductive line region extends in the second direction and is a region for forming a word line structure; the storage region is a region for forming a storage unit, the storage unit includes a transistor structure and a capacitor structure, and the storage region includes a transistor region cross-connected with the conductive line region and a capacitor region away from the conductive line region in the third direction.

In the disclosed embodiment, the first direction is the thickness direction of the substrate 401, ie, the Z direction, the second direction is the Y direction, and the third direction is the X direction. Both the second direction and the third direction are perpendicular to the first direction.

In some embodiments, referring to FIG. 4a, the method for forming a three-dimensional semiconductor storage device further includes: forming an active structure in each semiconductor layer 403 extending along a third direction in the transistor region; the active structure includes a first source/drain region 407, a channel region 408, and a second source/drain region 409 arranged in sequence in the third direction, and the channel region 408 is located at the intersection of the conductive line region and the storage region.

In some embodiments, in combination with FIG. 4a and FIG. 4b , the method for forming a three-dimensional semiconductor storage device further includes: filling a plurality of isolation trenches 405 and 405′ with an insulating material to form a plurality of isolation structures 410 and 410′; or first oxidizing the substrate 401 exposed by the isolation trenches 405 and 405′ through a thermal oxidation process, and then filling the remaining portions of the isolation trenches 405 and 405′ with an insulating material to form a plurality of isolation structures 410 and 410′.

It should be noted that the isolation structure 410' shown in the figure is a transparent effect, which is convenient for observing the structure formed through subsequent steps.

In some embodiments, in combination with FIG. 4b to FIG. 4d, wherein FIG. 4d is a cross-sectional view of FIG. 4c along line AA′, the method for forming a three-dimensional semiconductor storage device further includes: etching an isolation structure 410′ in a first direction to form a third opening 420 exposing the second source/drain region 409, the isolation structure between the bottom of the third opening 420 and the substrate 401 constitutes a shallow trench isolation structure 412; the thickness T3 of the shallow trench isolation structure 412 in the first direction is greater than the thickness T4 of the initial oxide layer 402 between the substrate and the storage stack structure. In a specific example, the thickness T3 of the shallow trench isolation structure 412 in the first direction is 3 times the thickness T4 of the initial oxide layer 402. In another specific example, the thickness T3 of the shallow trench isolation structure 412 in the first direction is 6 times the thickness T4 of the initial oxide layer 402 .

In some embodiments, in combination with FIG. 4c and FIG. 4e, the method for forming a three-dimensional semiconductor storage device further includes: filling the third opening 420 with a conductive material to form a bit line structure 421 extending along the first direction on the shallow trench isolation structure 412. As shown in FIG. 4e, the bit line structure 421 is electrically connected to the second source/drain regions 409 located on opposite sides thereof in the third direction. In some embodiments, the conductive material forming the bit line structure 421 can be one of a doped semiconductor material (e.g., doped polysilicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

In some embodiments, in combination with FIG. 4e and FIG. 4f, the method for forming a three-dimensional semiconductor storage device further includes: forming a plurality of word line structures 413 arranged along the first direction, extending along the second direction, and located on both sides of the channel region 408 in the conductive line region extending along the second direction, and the word line structure 413 and the bit line structure 421 extend in directions perpendicular to each other. It should be noted that the specific structure of the word line structure 413 can refer to FIG. 4j, in the first direction, a gate dielectric layer 414 is formed between the word line structure 413 and the channel region 408, and an insulating material is filled between two adjacent word line structures 413.

In the present disclosed embodiment, an active structure is formed in a semiconductor layer 403 in a transistor region in a storage region, the active structure including a first source/drain region 407, a channel region 408 and a second source/drain region 409, and a word line structure 413 is formed in a conductive line region extending along a second direction on opposite sides of the channel region 408 in the active structure along the first direction as a gate of the transistor structure. Thus, a transistor structure is formed in the transistor region, and a plurality of transistor structures with the same word line structure 413 as a gate are arranged along the second direction.

In some embodiments, in combination with FIG. 4f and FIG. 4g , the method for forming a three-dimensional semiconductor storage device further includes: etching a plurality of isolation structures 410 in a first direction to form a plurality of first openings 440 exposing the capacitor region and the substrate 401, wherein the bottom surface of the first opening is lower than the top surface of the substrate 401 in the storage region; etching the dielectric layer 406 extending along the third direction of the capacitor region through the first openings 440 to form a plurality of fourth openings 430, wherein the fourth openings 430 are connected to the first openings 440.

In some embodiments, in combination with FIG. 4g and FIG. 4h, the method for forming a three-dimensional semiconductor storage device further includes: forming a capacitor structure 431 on the surface of the semiconductor layer 406 exposed by the fourth opening 430 and the first opening 440, and the capacitor structure 431 is symmetrically distributed on both sides of the bit line structure 421 along the third direction. Here, the capacitor structure 431 is similar to the capacitor structure shown in FIG. 2m, including a second electrode, a capacitor dielectric layer and a first electrode formed in sequence around the end of the semiconductor layer 406, wherein the first electrode is located at the outermost layer. It should be noted that the disclosed embodiment is only described by taking the capacitor structure 431 being electrically connected to the source region and the bit line structure 421 being electrically connected to the drain region as an example. In some embodiments, the drain region may be electrically connected to the capacitor structure, and the source region may be electrically connected to the bit line structure.

In some embodiments, the step of forming the capacitor structure 431 includes: etching the semiconductor material layer 403 extending along the third direction in the capacitor region to form a plurality of capacitor openings; and forming the capacitor structure 431 in the capacitor openings. Here, the capacitor structure 431 is similar to the capacitor structure shown in FIG. 2n. After forming the capacitor structure 431, etching the isolation structure 410 in the first direction to form a first opening exposing the capacitor structure 431 and the substrate 201.

It should be noted that in the embodiments of the present disclosure, the fourth opening 430 and the first opening 440 may be formed first, and then the capacitor structure shown in FIG. 2m may be formed, or the capacitor opening and the capacitor structure shown in FIG. 2n may be formed first, and then the first opening 440 may be formed. The present disclosure does not limit this. In the following embodiments, the formation of the capacitor structure shown in FIG. 2m is used as an example to explain the subsequent steps.

In the disclosed embodiment, a capacitor structure 431 is formed in the capacitor region in the storage region, and a second electrode 4311 of the capacitor structure 431 is electrically connected to a first source/drain region 407 of a transistor structure in the same semiconductor layer 403, so that one capacitor structure 431 corresponds to one transistor structure electrically connected thereto, thereby forming a storage unit. The storage units are arranged in an array along the first direction and the second direction, and together form a storage structure of a three-dimensional semiconductor storage device.

In some embodiments, in combination with FIG. 4h and FIG. 4i , the method for forming a three-dimensional semiconductor storage device further includes: filling the remaining portions of the plurality of first openings 440 and the fourth openings 430 with a conductive material to form a common terminal lead-out structure 441 that electrically connects the first electrodes of the plurality of capacitor structures 431 to the substrate 401 .

In some embodiments, the three-dimensional semiconductor storage device finally formed by the above method is shown in FIG. 4j. In the three-dimensional semiconductor storage device, the storage structure is symmetrically distributed on both sides of the bit line structure 421 along the third direction. The storage structure includes a plurality of storage units composed of transistor structures and capacitor structures and arranged in an array along the first direction and the second direction. A shallow trench isolation structure 412 is formed between the bottom of the bit line structure 421 and the substrate 401, and its thickness T3 in the first direction is greater than the thickness T4 of the initial oxide layer 402. The common terminal lead-out structure 441 electrically connects the first electrodes 4313 of the plurality of capacitor structures 431 to the substrate 401.

In the process of forming the above-mentioned three-dimensional semiconductor storage device, a bit line opening (i.e., the third opening 420) exposing the second source/drain region 409 is formed in the isolation structure 410′, and a shallow trench isolation structure 412 is formed between the bottom of the bit line opening and the substrate 401, wherein the thickness T3 of the trench isolation structure 412 in the first direction is greater than the thickness T4 of the initial oxide layer. Then, the bit line opening is filled with a conductive material to form a bit line structure 421 extending along the first direction. Compared with the method of forming a bit line opening in a stacked structure, this method forms a bit line structure 421 on a shallow trench isolation structure 412 with a greater thickness, which can effectively prevent leakage between the bit line structure 421 and the substrate 401, thereby improving the reliability of the three-dimensional semiconductor storage device.

In some embodiments, the thickness T3 of the shallow trench isolation structure between the bottom of the bit line structure 421 and the substrate 401 in the first direction is greater than the distance between the bottom of the active structure closest to the substrate 401 and the substrate 401. Thus, leakage between the bit line structure 421 and the substrate 401 can be effectively prevented.

In addition, through the above-mentioned method for forming a three-dimensional semiconductor storage device, a common terminal lead-out structure 441 is formed to electrically connect the first electrodes 4313 of the plurality of capacitor structures 431 to the substrate 401, so that a common voltage can be provided to the common electrode of the capacitor structure 431 through the substrate 401. Therefore, in the process of forming the back-end interconnect layer, it is not necessary to set a power supply pad for providing a common voltage to the common electrode of the capacitor structure 431 in the bonding interface on the storage array wafer, so that the density of the pads in the bonding interface can be reduced, and the parasitic capacitance between the pads can be reduced. Furthermore, when the pad density in the bonding interface remains unchanged, the density of the capacitor structure in the storage array can be further increased, thereby improving the integration of the three-dimensional semiconductor storage device.

In the disclosed embodiment, the common voltage may be half of the power voltage, that is, VCC/2.

Based on the same technical concept as the aforementioned method for forming a three-dimensional semiconductor storage device, the disclosed embodiment provides a three-dimensional semiconductor storage device. FIG. 2r is a three-dimensional diagram of the three-dimensional semiconductor storage device provided by the disclosed embodiment. As shown in FIG. 2r, the three-dimensional semiconductor storage device includes: a substrate 201; a storage structure located on the substrate 201; the storage structure includes capacitor structures 231 arranged in an array along a first direction and a second direction; the capacitor structures 231 all extend along a third direction; a common end lead-out structure 241, the bottom surface of the common end lead-out structure 241 is lower than the top surface of the substrate 201, and the common end lead-out structure 241 is electrically connected to the first electrode 2313 of the capacitor structure 231 and the substrate 201.

In the disclosed embodiment, the first direction is the thickness direction of the substrate 201, ie, the Z direction, the second direction is the Y direction, and the third direction is the X direction. Both the second direction and the third direction are perpendicular to the first direction.

In some embodiments, the three-dimensional semiconductor storage device includes: a substrate 201; an isolation structure 210 and a common terminal lead-out structure 241 located on the substrate 201; the isolation structure 210 and the common terminal lead-out structure 241 are arranged along a third direction;

Storage structure; the storage structure includes a transistor structure located in the isolation structure 210 and a capacitor structure 231 located in the common terminal lead structure 241; the transistor structure and the capacitor structure 231 constitute a storage unit;

The storage units are arranged in an array along a first direction and a second direction;

The transistor structure and the capacitor structure 231 both extend along the third direction;

The common terminal lead structure 241 is electrically connected to the first electrode 2313 of the capacitor structure 231 and the substrate 201 .

In some embodiments, the transistor structure includes an active structure extending along a third direction, the active structure including a first source/drain region 207, a channel region 208, and a second source/drain region 209 arranged along the third direction. The second electrode 2311 of the capacitor structure 231 is electrically connected to the first source/drain region 207.

In some embodiments, the three-dimensional semiconductor storage device further includes: a word line structure 213 extending along the first direction and located on two opposite sides of the channel region 208 along the second direction; a shallow trench isolation structure 212 located between the bottom of the word line structure 213 and the substrate 201, and its thickness T1 in the first direction is greater than the thickness T2 of the initial oxide layer 202; a bit line structure 220 extending along the second direction and alternately arranged with the dielectric layer 206 in the first direction, and the bit line structure 220 is electrically connected to the second source/drain regions 209 on both sides.

In the disclosed embodiment, the word line structure 213 serves as a gate of the transistor structure, and together with the active structure, constitutes a transistor structure, and the transistor structure with the same word line structure 213 as a gate is arranged along the first direction. In the third direction, the first source/drain region 207 of a transistor structure is electrically connected to the second electrode 2311 of a capacitor structure 231, thereby constituting a storage unit. The storage units are arranged in an array along the first direction and the second direction, and together constitute a storage structure of a three-dimensional semiconductor storage device.

In one specific example, the thickness T1 of the shallow trench isolation structure 212 in the first direction is three times the thickness T2 of the initial oxide layer 202. In another specific example, the thickness T1 of the shallow trench isolation structure 212 in the first direction is six times the thickness T2 of the initial oxide layer 202.

In some embodiments, the capacitor structure 231 is symmetrically distributed on both sides of the bit line structure 220 along the third direction.

In some embodiments, the three-dimensional semiconductor storage device further includes: a metal silicide layer 242 and an adhesive layer 243 located between the common terminal lead-out structure 241 and the substrate 201 , wherein the adhesive layer 243 is located between the common terminal lead-out structure 241 and the metal silicide layer 242 .

In the disclosed embodiment, the material of the common terminal lead-out structure 241 includes a doped semiconductor material (e.g., doped polysilicon, doped germanium, etc.); the material of the metal silicide layer 242 can be tungsten silicide, cobalt silicide, titanium silicide, etc.; the material of the adhesive layer 243 can be a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). The metal silicide layer 242 and the adhesive layer 243 can effectively reduce the contact resistance between the common terminal lead-out structure 241 and the substrate 201.

In the disclosed embodiment, the three-dimensional semiconductor storage device includes electrically connecting the first electrodes 2313 of a plurality of capacitor structures 231 arrayed in a first direction and a second direction to a common lead-out structure 241 of a substrate 201 at the same time, so that the common electrode (i.e., the first electrode 2313) of the capacitor structure 231 can be connected to a common voltage through the substrate 201. In the process of forming a rear-end interconnection layer, the provision of a power supply pad for providing a common voltage to the common electrode of the capacitor structure can be omitted, thereby reducing the density of the pads in the bonding interface and reducing the parasitic capacitance between the pads. In addition, when the pad density in the bonding interface remains unchanged, the density of the capacitor structure in the storage array can be further increased, thereby improving the integration of the three-dimensional semiconductor storage device.

In the disclosed embodiment, the common voltage may be half of the power voltage, that is, VCC/2.

In the three-dimensional semiconductor storage device shown in FIG. 2r , a shallow trench isolation structure 212 is formed between the bottom of the word line structure 213 and the substrate 201, and its thickness T1 in the first direction is greater than the thickness T2 of the initial oxide layer 202. Thus, leakage between the word line structure 213 and the substrate 201 can be prevented, thereby effectively improving the reliability of the three-dimensional semiconductor storage device.

In some embodiments, the thickness T1 of the shallow trench isolation structure between the bottom of the word line structure 213 and the substrate 201 in the first direction is greater than the maximum distance between the storage structure and the substrate 201. Here, the maximum distance between the storage structure and the substrate 201 may be the distance between the bottom of the active structure closest to the substrate 201 and the substrate 201. Thus, leakage between the word line structure 213 and the substrate 201 can be effectively prevented.

FIG3 is a perspective view of another three-dimensional semiconductor storage device provided by the disclosed embodiment. The difference between the three-dimensional semiconductor storage device and the three-dimensional semiconductor storage device shown in FIG2q is that the capacitor structure 331 of the semiconductor storage device is distributed on the same side of the bit line structure 320.

FIG4j is a three-dimensional diagram of a three-dimensional semiconductor storage device provided by another embodiment of the present disclosure. As shown in FIG4j, the three-dimensional semiconductor storage device includes: a substrate 401; a storage structure located on the substrate 401; the storage structure includes a plurality of capacitor structures 431 arranged in an array along a first direction and a second direction; the capacitor structures 431 all extend along a third direction, including a second electrode 4311, a capacitor dielectric layer 4312, and a first electrode 4313 that sequentially surround the end of the semiconductor layer; a common terminal lead-out structure 441, the bottom surface of the common terminal lead-out structure 441 is lower than the top surface of the substrate 401, and the common terminal lead-out structure 441 is electrically connected to the first electrode 4313 of the capacitor structure 431 and the substrate 401.

In the disclosed embodiment, the first direction is the thickness direction of the substrate 401, ie, the Z direction, the second direction is the Y direction, and the third direction is the X direction. Both the second direction and the third direction are perpendicular to the first direction.

In some embodiments, the storage structure further includes an active structure extending along a third direction, the active structure including a first source/drain region 407, a channel region 408, and a second source/drain region 409 arranged along the third direction. The second electrode 4311 of the capacitor structure 431 is electrically connected to the first source/drain region 407.

In some embodiments, the three-dimensional semiconductor storage device further includes: a bit line structure 421 extending along the first direction and electrically connected to the second source/drain region 409; a shallow trench isolation structure 412 located between the bottom of the bit line structure 421 and the substrate 401, and having a thickness T3 in the first direction greater than a thickness T4 of the initial oxide layer 402; and a word line structure 413 extending along the second direction, the word line structure 413 being arranged in the first direction and located on two opposite sides of the channel region 408 along the first direction.

In the disclosed embodiment, the word line structure 413 serves as a gate of the transistor structure, and together with the active structure, constitutes a transistor structure, and the transistor structure with the same word line structure 413 as a gate is arranged along the second direction. In the third direction, the first source/drain region 407 of a transistor structure is electrically connected to the second electrode 4311 of a capacitor structure 431, thereby constituting a storage unit. The storage units are arranged in an array along the first direction and the second direction, and together constitute a storage structure of a three-dimensional semiconductor storage device.

In one specific example, the thickness T3 of the shallow trench isolation structure 412 in the first direction is 3 times the thickness T4 of the initial oxide layer 402. In another specific example, the thickness T3 of the shallow trench isolation structure 412 in the first direction is 6 times the thickness T4 of the initial oxide layer 402.

In some embodiments, a thickness T3 of the shallow trench isolation structure 412 in the first direction is greater than a distance between the bottom of the active structure closest to the substrate 401 and the substrate 401 .

In some embodiments, the three-dimensional semiconductor storage device further includes: a gate dielectric layer 414 located between the word line structure 413 and the channel region 408.

In some embodiments, the capacitor structure 431 is symmetrically distributed on both sides of the bit line structure 421 along the third direction.

In some embodiments, the three-dimensional semiconductor storage device further includes: a metal silicide layer 442 and an adhesive layer 443 located between the common terminal lead-out structure 441 and the substrate 401 , wherein the adhesive layer 443 is located between the common terminal lead-out structure 441 and the metal silicide layer 442 .

In the disclosed embodiment, the material of the common terminal lead-out structure 441 includes a doped semiconductor material (e.g., doped polysilicon, doped germanium, etc.); the material of the metal silicide layer 442 may be tungsten silicide, cobalt silicide, titanium silicide, etc.; the material of the adhesive layer 443 may be a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). The metal silicide layer 442 and the adhesive layer 443 may effectively reduce the contact resistance between the common terminal lead-out structure 441 and the substrate 401.

In the disclosed embodiment, the three-dimensional semiconductor storage device includes electrically connecting the first electrodes 4313 of a plurality of capacitor structures 431 arranged in an array along a first direction and a second direction to a common terminal lead-out structure 441 of a substrate 401 at the same time, so that the common electrode of the capacitor structure 431 can be connected to a common voltage through the substrate 401. In the process of forming a rear-end interconnection layer, the provision of a power supply pad for providing a common voltage to the common electrode of the capacitor structure can be omitted, thereby reducing the density of the pads in the bonding interface and reducing the parasitic capacitance between the pads.

In the three-dimensional semiconductor storage device shown in FIG4j, a shallow trench isolation structure 412 is formed between the bottom of the bit line structure 421 and the substrate 401, and its thickness T3 in the first direction is greater than the thickness T4 of the initial oxide layer 402. Thus, leakage between the bit line structure 421 and the substrate 401 can be prevented, thereby effectively improving the reliability of the three-dimensional semiconductor storage device.

In some embodiments, the three-dimensional semiconductor storage device is a three-dimensional dynamic random access memory (DRAM).

In some embodiments, the common voltage may be half of the power voltage, i.e., VCC/2.

In the disclosed embodiment, since the three-dimensional semiconductor storage device does not need to be grounded using a substrate, the common electrode of the arrayed capacitor structure can be electrically connected to the substrate by forming a common terminal lead-out structure, and a common voltage can be provided to the capacitor structure through the substrate. Therefore, in the process of forming the back-end interconnect layer, the provision of a power supply pad for providing a common voltage to the common electrode of the capacitor structure can be omitted, thereby reducing the density of the pads in the bonding interface and reducing the parasitic capacitance between the pads. In addition, when the pad density in the bonding interface remains unchanged, the density of the capacitor structure in the storage array can be further increased, thereby improving the integration of the three-dimensional semiconductor storage device.

In the disclosed embodiment, the three-dimensional semiconductor storage device has a word line structure or a bit line structure perpendicular to the substrate, and a word line opening or a bit line opening is formed in the isolation structure to form a shallow trench isolation structure between the word line structure and the substrate or between the bit line structure and the substrate, and the thickness of the shallow trench isolation structure is greater than the thickness of the initial oxide layer between the substrate and the stacking structure. Therefore, compared with the method of forming a word line opening or a bit line opening in the stacking structure, the method of forming the three-dimensional semiconductor storage device in the disclosed embodiment can effectively avoid leakage between the word line structure or the bit line structure and the substrate, and significantly improve the reliability of the three-dimensional semiconductor storage device.

The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

The features disclosed in several device embodiments provided in this disclosure can be arbitrarily combined to obtain new device embodiments without conflict.

The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person with ordinary knowledge in the technical field within the technical scope disclosed in the present disclosure should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be based on the protection scope of the claim.

101,102,103,104: Steps 201,301,401: Substrate 202,302,402: Initial oxide layer 203: Semiconductor layer 204: Sacrificial layer 205: Isolation trench 206: Dielectric layer 207: First source/drain region 208: Channel region 209: Second source/drain region 210: Isolation structure 211: Second opening 212: Shallow trench isolation structure 213,313,413: Word line structure 214: Gate dielectric layer 220: Bit line structure 230: fourth opening 231: capacitor structure 2311: second electrode 2312: capacitor dielectric layer 2313: first electrode 2314: second electrode 2315: capacitor dielectric layer 2316: first electrode 240: first opening 241,241′,341,441,441′: common terminal lead structure 242,342,442: metal silicide layer 243,343,443: bonding layer 307: first source/drain region 308: channel region 309: second source/drain region 320: bit line structure 331: capacitor structure 403: semiconductor layer 405,405′: isolation trench 406: dielectric layer 407: first source/drain region 408: channel region 409: second source/drain region 410,410′: isolation structure 412: shallow trench isolation structure 414: gate dielectric layer 420: third opening 421: bit line structure 430: fourth opening 431: capacitor structure 4311: second electrode 4312: capacitor dielectric layer 4313: first electrode 440: first opening AA′,BB′: line T1, T2, T3, T4: thickness

FIG1 is a schematic diagram of a process for forming a three-dimensional semiconductor storage device according to an embodiment of the present disclosure;

2a to 2r are schematic structural diagrams of the process of forming a three-dimensional semiconductor storage device provided by an embodiment of the present disclosure;

FIG3 is a schematic structural diagram of a three-dimensional semiconductor storage device provided by another embodiment of the present disclosure;

4a to 4j are schematic structural diagrams of a three-dimensional semiconductor storage device formation process provided by another embodiment of the present disclosure.

101,102,103,104: Steps

Claims (11)

A method for forming a three-dimensional semiconductor storage device, characterized in that it includes: forming a storage stack structure on a substrate, and forming an isolation structure in the storage stack structure; the isolation structure separates the storage stack structure into a conductive line region and a storage region; etching the isolation structure to form a plurality of first openings exposing a capacitor region in the storage region and the substrate; the bottom surface of the first opening is lower than the top surface of the substrate; forming capacitor structures arranged in arrays along a first direction and a second direction in the capacitor region; the first electrode of the capacitor structure is exposed in the first opening; the capacitor structure extends along a third direction; forming a common terminal lead-out structure in the first opening to electrically connect the first electrode of the capacitor structure to the substrate. The method for forming a three-dimensional semiconductor storage device as described in claim 1 is characterized in that, before forming the capacitor structure arranged in array along the first direction and the second direction in the capacitor region, it also includes: forming an active structure arranged in array along the first direction and the second direction in the transistor region in the storage region; the active structure extends along the third direction, and the active structure includes a first source/drain region, a channel region, and a second source/drain region; the second electrode of the capacitor structure is electrically connected to the first source/drain region in the active structure. The method for forming a three-dimensional semiconductor storage device as described in claim 2 is characterized in that it further includes: etching the isolation structure to form a second opening exposing the channel region; the isolation structure between the bottom of the second opening and the substrate forms a shallow trench isolation structure; the thickness of the shallow trench isolation structure in the first direction is greater than the thickness of the initial oxide layer between the substrate and the storage stack structure; forming a word line structure extending along the first direction in the second opening; forming a bit line structure arranged along the first direction, extending along the second direction, and electrically connected to the second source/drain region in the conductive line region. The method for forming a three-dimensional semiconductor storage device as described in claim 2 is characterized in that it further includes: etching the isolation structure to form a third opening exposing the second source/drain region; the isolation structure between the bottom of the third opening and the substrate forms a shallow trench isolation structure; the thickness of the shallow trench isolation structure in the first direction is greater than the thickness of the initial oxide layer between the substrate and the storage stack structure; forming a plurality of bit line structures extending along the first direction in the third opening, the bit line structures being electrically connected to the second source/drain region; forming a word line structure arranged along the first direction, extending along the second direction, and located on both sides of the channel region in the conductive line region. The method for forming a three-dimensional semiconductor storage device as described in claim 1 is characterized in that the common terminal lead structure for electrically connecting the first electrode of the capacitor structure to the substrate is formed in the first opening, comprising: sequentially forming a metal silicide layer and an adhesive layer on the substrate surface exposed by the first opening; depositing a conductive material on the adhesive layer to fill the first opening; the conductive material comprises polysilicon. The method for forming a three-dimensional semiconductor storage device as described in claim 2 is characterized in that the storage stack structure includes dielectric layers and semiconductor layers alternately stacked along the first direction; the capacitor structure arranged in array along the first direction and the second direction is formed in the capacitor region, comprising: etching the dielectric layer in the third direction to form a fourth opening of the semiconductor layer exposing the capacitor region, the fourth opening being aligned with the first direction. The first opening is connected to the first semiconductor layer; the second electrode, the capacitor dielectric layer and the first electrode of the capacitor structure are sequentially formed on the surface of the semiconductor layer exposed by the first opening and the fourth opening; the common terminal lead structure that electrically connects the first electrode of the capacitor structure to the substrate is formed in the first opening, including: filling the conductive material in the first opening and between the capacitor structure to form the common terminal lead structure. A three-dimensional semiconductor storage device, characterized in that it includes: a substrate; a storage structure located on the substrate; the storage structure includes capacitor structures arranged in an array along a first direction and a second direction; the capacitor structure extends along a third direction; the first direction is the thickness direction of the substrate, and the second direction and the third direction are both perpendicular to the first direction; a common end lead structure, the bottom surface of the common end lead structure is lower than the top surface of the substrate; the common end lead structure is a conductive material, electrically connected to the first electrode of the capacitor structure and the substrate, and electrically connects the first electrode of the capacitor structure to the substrate. The three-dimensional semiconductor storage device as described in claim 7 is characterized in that the storage structure further includes: An active structure extending along the third direction; the active structure includes a first source/drain region, a channel region and a second source/drain region arranged in sequence along the third direction; the second electrode of the capacitor structure is electrically connected to the first source/drain region. The three-dimensional semiconductor storage device as described in claim 8 is characterized in that it further includes: a word line structure extending along the first direction; the word line structure is located on two opposite sides of the channel region along the second direction; a shallow trench isolation structure is located between the word line structure and the substrate; the thickness of the shallow trench isolation structure in the first direction is greater than the thickness of the initial oxide layer; the initial oxide layer is located between the substrate and the storage structure; a bit line structure is arranged along the first direction, extends along the second direction, and is connected to the second source/drain region; the capacitor structure is symmetrically distributed on both sides of the bit line structure along the third direction; or, the capacitor structure is located on one side of the bit line structure. The three-dimensional semiconductor storage device as described in claim 8 is characterized in that it further includes: a bit line structure extending along the first direction; the bit line structure is electrically connected to the second source/drain region; a shallow trench isolation structure is located between the bottom of the bit line structure and the substrate; the thickness of the shallow trench isolation structure in the first direction is greater than the thickness of the initial oxide layer; the initial oxide layer is located between the substrate and the storage structure; a word line structure is arranged along the first direction, extends along the second direction, and is located on two opposite sides of the channel region along the first direction; the capacitor structure is symmetrically distributed on both sides of the bit line structure along the third direction; or, the capacitor structure is located on one side of the bit line structure. The three-dimensional semiconductor storage device as described in claim 8 is characterized in that it also includes: a metal silicide layer located between the common terminal lead-out structure and the substrate; an adhesive layer located between the common terminal lead-out structure and the metal silicide layer; and the material of the common terminal lead-out structure includes polysilicon.