TWI869099B - Manufacturing method of waferless interposer - Google Patents

Abstract

A manufacturing method of a waferless interposer includes steps of providing a carrier wafer, forming a first redistribution layer, at least by which a wire pattern is formed, on the carrier wafer, forming a passivation layer to protect the wire pattern, flipping the carrier wafer and adhering it to a supporting substrate so that the passivation layer contacts and adheres to the supporting substrate, and removing the carrier wafer to form a waferless interposer adhered to the supporting substrate. The carrier wafer is merely used as a carrier, which means that the carrier wafer is reusable. In addition, the benefits of eliminating the need for an expensive process of through silicon via, mitigating the risk of chip first process, and allowing the waferless interposer to be shipped individually are further achieved.

Description

Manufacturing method of waferless interposer

The present invention relates to a manufacturing method, and in particular to a manufacturing method of a waferless interposer suitable for advanced processes.

Advanced packaging is a technology used in semiconductor manufacturing that involves packaging integrated circuit chips (ICs) in smaller, thinner, more efficient or more functional packages to meet the needs of modern electronic devices. Faced with the increasing number of input/output ports on chips, the demand for advanced packaging has become increasingly important. For example, the demand for chips used in the field of artificial intelligence (AI) has increased significantly, and the requirements for advanced packaging specifications, production capacity and yield have become very critical.

Among the current semiconductor manufacturing technologies, there are only two production technologies that can meet the actual needs of advanced packaging: CoWoS (Chip on Wafer on Substrate) and InFO (Integrated Fan-Out). The CoWoS technology stacks chips on a wafer through the CoW (Chip on Wafer) process, and then connects the CoW part to the substrate through the WoS (Wafer on Substrate) process to package multiple chips together, thereby achieving the technical effect of reducing size and power consumption while maintaining high performance. InFO technology, that is, integrated fan-out technology, allows the pins to exceed the chip, can support more pins, make the pin density higher, and at the same time improve the heat dissipation effect.

However, in InFO technology, since it is a chip-first packaging technology, the chip must be fixed and arranged at the bottom before proceeding to the subsequent process. Therefore, if there is a yield problem in the manufacturing process, the chip will be scrapped and cause serious losses. In CoWoS technology, although it is a chip-last packaging technology, it requires wafers as materials, and must be processed by wafer grinding and thinning and silicon through-hole (TSV), which requires a lot of cost and time in both materials and processes. During the grinding process, it may also cause defects such as local or overall uneven thickness or wafer edge damage, resulting in low yield. In addition, the production process of the interlayer requires the use of an ultrathin wafer handling system, which increases the complexity and cost of the process.

In addition, whether it is advanced packaging using CoWoS technology or InFO technology, there will be problems of residual stress and stress accumulation during its manufacturing process, resulting in poor quality of the intermediate layer and the final product.

Therefore, it is necessary to provide a waferless interposer manufacturing method to solve the problems existing in the prior art.

The motivation of the present invention is to provide a waferless interposer manufacturing method, aiming to solve and improve the above-mentioned problems and shortcomings of the prior art.

The main purpose of the present invention is to provide a method for manufacturing a waferless interposer, which forms a waferless interposer by flipping a carrier wafer over and attaching it to a supporting substrate and then removing the carrier wafer, so that the carrier wafer is only used as a carrier tool and can be reused. At the same time, because the wafer does not belong to the material itself and there is no need to arrange the chip at the bottom first, it is possible to achieve the effect of not having to perform an expensive through silicon via (TSV) process and avoiding the risks derived from starting with a chip (Chip First), and the interposer can be shipped separately.

Furthermore, since the wafer-free interposer manufacturing method of the present invention does not require wafer grinding and thinning in any step, a high-quality wafer-free interposer with low stress and low deformation can be provided.

According to one aspect of the present invention, a method for manufacturing a waferless interposer is provided, comprising the steps of: (a) providing a carrier wafer; (b) forming a first redistribution wiring layer on the carrier wafer, wherein at least the first redistribution wiring layer forms a wire pattern; (c) forming a protective layer to protect the wire pattern; (d) turning over the carrier wafer and bonding it to a supporting substrate so that the protective layer contacts and bonds with the supporting substrate; and (e) removing the carrier wafer to form a waferless interposer bonded to the supporting substrate.

In one embodiment of the present invention, in the step (b), the first redistribution layer forms the conductor pattern, and in the step (c), the protection layer is formed on the first redistribution layer.

In one embodiment of the present invention, the method further includes a step between the step (b) and the step (c): (b1) forming a second redistribution wiring layer on the first redistribution wiring layer, wherein in the step (b1), the first redistribution wiring layer and the second redistribution wiring layer form the conductor pattern, and in the step (c), the protective layer is formed on the second redistribution wiring layer.

In one embodiment of the present invention, after step (e), the method further includes the steps of: (f) bonding a plurality of chips to the waferless interposer; (g) packaging the plurality of chips and the waferless interposer into an advanced package; and (h) removing the supporting substrate.

In one embodiment of the present invention, the first redistribution layer has a plurality of conductive contacts, in the step (e), the plurality of conductive contacts are exposed on a first surface of the waferless interposer, and in the step (f), the plurality of chips are connected to the plurality of conductive contacts so that the plurality of chips are electrically connected to the waferless interposer.

In one embodiment of the present invention, between step (c) and step (d), there is further included a step of: (c1) forming a plurality of through holes in the protective layer, wherein in step (e), the plurality of through holes are located on a second surface of the waferless interposer.

In one embodiment of the present invention, the step (g) is performed from the first surface of the waferless interposer toward a direction away from the second surface of the waferless interposer.

In one embodiment of the present invention, after step (h), the method further includes the following steps: (i) assembling the advanced package with a circuit board so that a plurality of solder balls on the circuit board are connected to the conductive pattern through the plurality of through holes, thereby electrically connecting the circuit board to the waferless interposer.

In one embodiment of the present invention, in the step (d), the bonding of the protective layer and the supporting substrate is achieved by using an adhesive tape, and the step (h) is achieved by performing a debonding operation.

In one embodiment of the present invention, the carrier wafer includes a light-transmitting substrate and a carrier layer formed on the light-transmitting substrate, and the step (e) is implemented by irradiating the carrier layer with a laser through the light-transmitting substrate to vaporize and decompose the carrier layer.

Therefore, the waferless interposer manufacturing method provided by the present invention has at least the following advantages compared to the prior art:

1. The carrier wafer is only used as a carrier tool and can be reused, which can effectively reduce material costs;

Second, there is no need for through silicon via (TSV) and wafer grinding and thinning processes during the manufacturing process, which can effectively reduce the cost and time of manufacturing;

3. Avoid risks arising from chip first; and

4. Waferless interposers can be shipped separately by attaching them to a supporting substrate, packaged with a chip and shipped after removing the supporting substrate, or assembled with a circuit board after debonding. They are flexible enough and can be manufactured according to actual needs.

In order to make the above and other purposes, features, and advantages of the present invention more clearly understood, the preferred embodiments of the present invention are specifically cited below, and are described in detail with reference to the attached drawings. Furthermore, the directional terms mentioned in the present invention, such as up, down, top, bottom, front, back, left, right, inside, outside, side, periphery, center, horizontal, transverse, vertical, longitudinal, axial, radial, topmost or bottommost, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to explain and understand the present invention, but not to limit the present invention.

Please refer to FIG. 1, which shows a flow chart of a method for manufacturing a waferless interposer according to a preferred embodiment of the present invention. As shown in FIG. 1, according to a preferred embodiment of the present invention, a method for manufacturing a waferless interposer suitable for an advanced process is provided, comprising the following steps. First, as shown in step S10, a carrier wafer is provided. Secondly, as shown in step S20, a first redistribution layer (RDL) is formed on the carrier wafer, wherein at least the first redistribution layer forms a wire pattern, for example, the first redistribution layer forms the wire pattern. Next, as shown in step S30, a protective layer (Passivation Layer) is formed to protect the wire pattern, for example, the protective layer is formed on the first redistribution layer. Then, as shown in step S40, the carrier wafer is turned over and bonded to the supporting substrate so that the protective layer contacts and bonds with the supporting substrate. In some embodiments, the supporting substrate may be a fixture, such as a dedicated plate designed for support, but is not limited thereto. Then, as shown in step S50, the carrier wafer is removed to form a waferless interposer bonded to the supporting substrate. In other words, the waferless interposer includes at least a first redistribution wiring layer and a protective layer, wherein the supporting substrate, the protective layer and the first redistribution wiring layer are stacked in order from bottom to top, and the protective layer is in direct contact with the supporting substrate. Since the supporting substrate provides sufficient strength and support, the waferless interposer can be attached to the supporting substrate and shipped separately to meet actual needs. From the above description, it can be seen that the carrier wafer is only used as a carrier tool rather than the material itself, so the carrier wafer can be reused. At the same time, because the carrier wafer does not belong to the material itself, there is no need to perform expensive through silicon via (TSV) process. In addition, the waferless interposer manufacturing method of the present invention does not need to arrange the chip at the bottom first, thus avoiding the risks derived from the chip first process.

In some embodiments, the carrier wafer includes a transparent substrate and a carrier layer formed on the transparent substrate, and the above-mentioned step S50, i.e., the step of removing the carrier wafer, is preferably achieved by irradiating the carrier layer through the transparent substrate with a laser to vaporize and separate the carrier layer. Specifically, the light-transmitting substrate may be made of quartz glass, borosilicate glass, sodium silicate glass or sapphire glass; the carrier layer may be a buffer layer, and may be a ceramic optical film, a metal film or a non-metallic film, such as a ceramic optical film such as gallium nitride (GaN), aluminum nitride (AlN), aluminum oxide (AlO) or zinc oxide (ZnO), a metal film such as gold (Au), silver (Ag), copper ( _Cu ), aluminum (Al), nickel (Ni), titanium (Ti) or titanium tungsten (TiW), or a non-metallic film such as silicon nitride ( _SixNx ), silicon oxide ( _SixOx ), silicon (Si) or silicon carbide (SiC), _but not limited thereto. In addition, in step S50, the laser used can be an infrared laser (IR Laser), a visible light laser, an ultraviolet laser (UV Laser) or a deep ultraviolet laser (DUV Laser), etc., and an appropriate laser is selected in combination with the materials of the transparent carrier and the supporting layer to achieve the technical effect of penetrating the transparent carrier to irradiate the supporting layer and vaporize and decompose the supporting layer.

In some embodiments, the waferless interposer manufacturing method of the present invention can form more than two redistribution layers according to the requirements of circuit layout to form a three-dimensional wiring pattern.

The following will describe an embodiment of the method for manufacturing a waferless interposer of the present invention, including the steps of forming a first redistribution wiring layer and forming a second redistribution wiring layer. Please refer to FIG. 2, which shows a flow chart of the method for manufacturing a waferless interposer according to another preferred embodiment of the present invention. As shown in FIG. 2, the method for manufacturing a waferless interposer of the present invention may further include a step S25 between step S20 and step S30, forming a second redistribution wiring layer on the first redistribution wiring layer. In addition, in step S25, the first redistribution wiring layer and the second redistribution wiring layer form a wire pattern, and in step S30, a protective layer is formed on the second redistribution wiring layer to protect the wire pattern. In other words, the waferless interposer in step S50 of this embodiment includes a first redistribution wiring layer, a second redistribution wiring layer and a protective layer, wherein the supporting substrate, the protective layer, the second redistribution wiring layer and the first redistribution wiring layer are stacked in sequence from bottom to top.

The following will describe an embodiment of the waferless interposer manufacturing method of the present invention including the steps of forming a first redistribution wiring layer, forming a second redistribution wiring layer, and forming a third redistribution wiring layer. Please refer to FIG. 3, which shows a flow chart of the waferless interposer manufacturing method according to another preferred embodiment of the present invention. As shown in FIG. 3, the waferless interposer manufacturing method of the present invention includes a step S25 between step S20 and step S30, forming a second redistribution wiring layer on the first redistribution wiring layer, and further includes a step S28 between step S25 and step S30, forming a third redistribution wiring layer on the second redistribution wiring layer. In this embodiment, in step S28, the first redistribution wiring layer, the second redistribution wiring layer and the third redistribution wiring layer form a wiring pattern, and in step S30, a protective layer is formed on the third redistribution wiring layer to protect the wiring pattern. That is, the waferless interposer in step S50 of this embodiment includes the first redistribution wiring layer, the second redistribution wiring layer, the third redistribution wiring layer and the protective layer, wherein the supporting substrate, the protective layer, the third redistribution wiring layer, the second redistribution wiring layer and the first redistribution wiring layer are stacked in sequence from bottom to top.

In some embodiments, the waferless interposer manufactured by the waferless interposer manufacturing method of the present invention can be shipped as a product by attaching it to a supporting substrate in the manner described above, or it can be shipped as a product after being packaged with a chip and removing the supporting substrate. This will be further described below.

Please refer to FIG. 4 , which shows a flow chart of a method for manufacturing a waferless interposer according to another preferred embodiment of the present invention. As shown in FIG. 4 , the method for manufacturing a waferless interposer of the present invention may further include step S60, step S70, and step S80 after step S50. After step S50 is completed, as shown in step S60, a plurality of chips are bonded to the waferless interposer. Then, as shown in step S70, a plurality of chips are packaged with the waferless interposer into an advanced package, such as a 2.5D or 3D package, but not limited thereto. Then, as shown in step S80, the supporting substrate is removed. In some embodiments, the waferless interposer manufacturing method of the present invention uses adhesive tape to achieve bonding between the protective layer of the waferless interposer and the supporting substrate in step S40, and in step S80, a debonding operation is performed to remove the supporting substrate, such as directly removing the adhesive tape to separate the supporting substrate from the waferless interposer, but not limited thereto. After step S80 is completed, the waferless interposer and the advanced package can be shipped as products.

In some embodiments, the waferless interposer manufactured by the waferless interposer manufacturing method of the present case can be shipped as a product after being bonded to a supporting substrate or packaged with a chip and removing the supporting substrate in the manner described above, or assembled with a circuit board after debonding, which is flexible enough and can be manufactured according to actual needs. This will be further described below.

Please refer to FIG. 5, which shows a flow chart of a method for manufacturing a waferless interposer according to another preferred embodiment of the present invention. As shown in FIG. 5, the method for manufacturing a waferless interposer of the present invention further includes step S35 between step S30 and step S40, i.e., a step of forming a plurality of through holes in the protective layer, wherein the positions of the plurality of through holes can be designed in accordance with the actual needs and in combination with the conductor pattern. In addition, after step S80, step S90 is further included, i.e., a step of assembling the advanced package with the circuit board, so that a plurality of solder balls on the circuit board are connected to the conductive pattern through a plurality of through holes, thereby electrically connecting the circuit board with the waferless interposer. After step S90 is completed, that is, after the electrical connection between the waferless interposer and the circuit board is completed, it can be shipped as a product.

Please refer to FIG. 6 in conjunction with FIGS. 7 to 16, wherein FIG. 6 shows a flow chart of a method for manufacturing a waferless interposer according to another preferred embodiment of the present invention, FIG. 7 shows a schematic diagram of step S10 of the method for manufacturing a waferless interposer shown in FIG. 6, FIG. 8 shows a schematic diagram of step S20 of the method for manufacturing a waferless interposer shown in FIG. 6, FIG. 9 shows a schematic diagram of step S25 of the method for manufacturing a waferless interposer shown in FIG. 6, FIG. 10 shows a schematic diagram of step S30 and step S35 of the method for manufacturing a waferless interposer shown in FIG. 6, and FIG. 11 shows a schematic diagram of step S30 and step S35 of the method for manufacturing a waferless interposer shown in FIG. 6 is a schematic diagram of step S40 of the manufacturing method of the waferless interposer shown in FIG. 6, FIG. 12 is a schematic diagram of step S50 of the manufacturing method of the waferless interposer shown in FIG. 6, FIG. 13 is a schematic diagram of step S60 of the manufacturing method of the waferless interposer shown in FIG. 6, FIG. 14 is a schematic diagram of step S70 of the manufacturing method of the waferless interposer shown in FIG. 6, FIG. 15 is a schematic diagram of step S80 of the manufacturing method of the waferless interposer shown in FIG. 6, and FIG. 16 is a schematic diagram of step S90 of the manufacturing method of the waferless interposer shown in FIG.

As shown in FIGS. 6 to 16 , a method for manufacturing a waferless interposer in a preferred embodiment of the present invention includes the following steps. First, as shown in step S10, a carrier wafer 1 is provided. Second, as shown in step S20, a first redistribution wiring layer 21 is formed on the carrier wafer 1, and the first redistribution wiring layer 21 has a plurality of conductive contacts 211, and the plurality of conductive contacts 211 are formed in step S20. Next, as shown in step S25, a second redistribution wiring layer 22 is formed on the first redistribution wiring layer 21, wherein the first redistribution wiring layer 21 and the second redistribution wiring layer 22 form a wiring pattern. Then, as shown in step S30, a protective layer 23 is formed to protect the wire pattern, wherein the protective layer 23 is formed on the second redistribution layer 22. Then, as shown in step S35, a plurality of through holes 230 are formed in the protective layer 23. Then, as shown in step S40, the carrier wafer 1 is turned over and bonded to the supporting substrate 3, so that the protective layer 23 contacts and bonds with the supporting substrate 3, wherein the supporting substrate 3 can be a fixture, but is not limited thereto. Then, as shown in step S50, the carrier wafer 1 is removed to form a waferless interposer 2 bonded to the supporting substrate 3. In this step S50, a plurality of conductive contacts 211 are exposed on the first surface of the waferless interposer 2, i.e., the surface of the waferless interposer 2 farthest from the supporting substrate 3, and a plurality of through holes 230 are located on the second surface of the waferless interposer 2, i.e., the surface where the waferless interposer 2 contacts and bonds with the supporting substrate 3. Then, as shown in step S60, a plurality of chips 4 are bonded to the waferless interposer 2. In this step S60, the plurality of chips 4 are connected to the plurality of conductive contacts 211, so that the plurality of chips 4 are electrically connected to the waferless interposer 2. Then, as shown in step S70, the plurality of chips 4 and the waferless interposer 2 are packaged into an advanced package 5, specifically, the packaging is performed from the first surface of the waferless interposer 2 to the direction away from the second surface of the waferless interposer 2. Next, as shown in step S80, the supporting substrate 3 is removed. Finally, as shown in step S90, the advanced package 5 is assembled with the circuit board 6, so that the plurality of solder balls 61 on the circuit board 6 are connected to the conductive pattern through the plurality of through holes 230, thereby electrically connecting the circuit board 6 to the waferless interposer 2.

In summary, the present invention provides a method for manufacturing a waferless interposer, which forms a waferless interposer by flipping a carrier wafer and attaching it to a supporting substrate and then removing the carrier wafer, so that the carrier wafer is only used as a carrier tool and can be reused. At the same time, because the wafer does not belong to the material itself and there is no need to arrange the chips at the bottom first, it is possible to achieve the effect of not having to perform an expensive through silicon via (TSV) process and avoiding the risk of starting with a chip first, and the interposer can be shipped separately. Furthermore, because the waferless interposer manufacturing method of the present invention does not require wafer grinding and thinning in any of its steps, it can provide a high-quality waferless interposer with low stress and low deformation.

Although the present invention has been disclosed with preferred embodiments, they are not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the attached patent application.

1: Wafer carrier

2: Waferless interposer

21: First redistribution layer

211: Conductive contact

22: Second redistribution layer

23: Protective layer

230:Through hole

3: Support substrate

4: Chip

5: Advanced Packaging

6: Circuit board

61: Solder ball

S10: Step

S20: Step

S25: Step

S28: Step

S30: Step

S35: Step

S40: Step

S50: Step

S60: Step

S70: Step

S80: Step

S90: Steps

FIG. 1 shows a flow chart of a method for manufacturing a waferless interposer according to a preferred embodiment of the present invention. FIG. 2 shows a flow chart of a method for manufacturing a waferless interposer according to another preferred embodiment of the present invention. FIG. 3 shows a flow chart of a method for manufacturing a waferless interposer according to another preferred embodiment of the present invention. FIG. 4 shows a flow chart of a method for manufacturing a waferless interposer according to another preferred embodiment of the present invention. FIG. 5 shows a flow chart of a method for manufacturing a waferless interposer according to another preferred embodiment of the present invention. FIG. 6 shows a flow chart of a method for manufacturing a waferless interposer according to another preferred embodiment of the present invention. FIG. 7 shows a schematic diagram of step S10 of the method for manufacturing a waferless interposer shown in FIG. 6. FIG8 is a schematic diagram showing step S20 of the method for manufacturing a waferless interposer shown in FIG6. FIG9 is a schematic diagram showing step S25 of the method for manufacturing a waferless interposer shown in FIG6. FIG10 is a schematic diagram showing step S30 and step S35 of the method for manufacturing a waferless interposer shown in FIG6. FIG11 is a schematic diagram showing step S40 of the method for manufacturing a waferless interposer shown in FIG6. FIG12 is a schematic diagram showing step S50 of the method for manufacturing a waferless interposer shown in FIG6. FIG13 is a schematic diagram showing step S60 of the method for manufacturing a waferless interposer shown in FIG6. FIG14 is a schematic diagram showing step S70 of the method for manufacturing a waferless interposer shown in FIG6. FIG. 15 is a schematic diagram showing step S80 of the method for manufacturing the waferless interposer shown in FIG. 6 . FIG. 16 is a schematic diagram showing step S90 of the method for manufacturing the waferless interposer shown in FIG. 6 .

S10: Step

S20: Step

S30: Step

S40: Step

S50: Step

Claims (9)

A method for manufacturing a waferless interposer comprises the steps of: (a) providing a carrier wafer; (b) forming a first redistribution wiring layer on the carrier wafer, wherein at least the first redistribution wiring layer forms a wire pattern; (c) forming a protective layer to protect the wire pattern; (d) turning over the carrier wafer and bonding it to a supporting substrate so that the protective layer contacts and bonds with the supporting substrate; (e) removing the carrier wafer to form a waferless interposer bonded to the supporting substrate; (f) bonding a plurality of chips to the waferless interposer; (g) packaging the plurality of chips and the waferless interposer into an advanced package; and (h) removing the supporting substrate. The method for manufacturing a waferless interposer as described in claim 1, wherein in the step (b), the first redistribution layer forms the conductor pattern, and in the step (c), the protective layer is formed on the first redistribution layer. The method for manufacturing a waferless interposer as described in claim 1 further includes a step between the step (b) and the step (c): (b1) forming a second redistribution wiring layer on the first redistribution wiring layer, wherein in the step (b1), the first redistribution wiring layer and the second redistribution wiring layer form the conductor pattern, and in the step (c), the protective layer is formed on the second redistribution wiring layer. A method for manufacturing a waferless interposer as described in claim 1, wherein the first redistribution layer has a plurality of conductive contacts, in the step (e), the plurality of conductive contacts are exposed on a first surface of the waferless interposer, and in the step (f), the plurality of chips are connected to the plurality of conductive contacts so that the plurality of chips are electrically connected to the waferless interposer. The method for manufacturing a waferless interposer as described in claim 4 further includes a step between step (c) and step (d): (c1) forming a plurality of through holes in the protective layer, wherein in step (e), the plurality of through holes are located on a second surface of the waferless interposer. A method for manufacturing a waferless interposer as described in claim 5, wherein the step (g) is to perform packaging from the first surface of the waferless interposer toward a direction away from the second surface of the waferless interposer. The method for manufacturing a waferless interposer as described in claim 5 further comprises the following steps after step (h): (i) assembling the advanced package with a circuit board so that a plurality of solder balls on the circuit board are connected to the conductive pattern through the plurality of through holes, thereby electrically connecting the circuit board to the waferless interposer. The method for manufacturing a waferless interposer as described in claim 1, wherein in step (d), the bonding of the protective layer and the supporting substrate is achieved by using a tape, and step (h) is achieved by performing a debonding operation. A method for manufacturing a waferless interposer as described in claim 1, wherein the carrier wafer includes a light-transmitting substrate and a carrier layer formed on the light-transmitting substrate, and step (e) is achieved by irradiating the carrier layer with a laser through the light-transmitting substrate to vaporize and decompose the carrier layer.