TWI868725B - Non-volatile memory and program method thereof - Google Patents

Abstract

A non-volatile memory and a programming method thereof are provided. The programming method includes: reading a plurality of first memory cells of Nth word line, and judging whether an effective threshold voltage larger than a preset threshold or not to generate a judge result, where N is a positive integer larger than 0; and, when a program operation being performed on a plurality of second memory cells of N+1th word line, deciding whether to adjust at least one selected program verify voltage of a plurality of program verify voltages by an offset value according to the judge result.

Description

Non-volatile memory and programming method

The present invention relates to a non-volatile memory and a programming method.

In recent years, mobile electronic devices, such as tablets, laptops, smartphones, and solid-state drives, have begun to use NAND flash memory as their main data storage medium. Therefore, the demand for low-cost and high-density NAND flash memory has been growing rapidly. In order to overcome the problem of flash memory cell size reduction, various types of flash memory cells with three-dimensional stacked charge trapping layers have been proposed.

However, as the spacing in the memory cell decreases, the lateral movement of charge between the memory cells causes a serious degradation in data retention. And setting more layers in the memory cell will also lead to higher resistance and cause overdrive problems.

The present invention provides a non-volatile memory and a programming method.

The programming method of the present invention includes: performing a reading operation on a plurality of first memory cells of the Nth word line, and determining whether the equivalent critical voltage of the first memory cell is greater than a preset threshold value to generate a determination result, wherein N is a positive integer greater than 1; and, when performing a programming operation on a plurality of second memory cells of the N+1th word line, determining whether to adjust at least one selected programming verification voltage among a plurality of programming verification voltages by an offset value according to the determination result.

The non-volatile memory of the present invention includes a memory cell array and a controller. The memory cell array has a plurality of memory cell strings, each of which is coupled to a plurality of word lines. The controller is coupled to the memory cell array to: perform a read operation on a plurality of first memory cells of the Nth word line, and determine whether the equivalent critical voltage of the first memory cell is greater than a preset threshold value to generate a determination result, wherein N is a positive integer greater than 1; and, when performing a programming operation on a plurality of second memory cells of the N+1th word line, determine whether to adjust at least one selected programming verification voltage among a plurality of programming verification voltages by an offset value according to the determination result.

Based on the above, the non-volatile memory of the present invention can read the critical voltage state of the memory cell of the previous word line when performing the programming operation of the memory cell of the current word line. Then, it is determined whether to adjust the programming verification voltage in the programming operation of the memory cell of the current word line according to the equivalent critical voltage of the memory cell of the previous word line. Through the above-mentioned adjustment operation of the programming verification voltage, the overdrive phenomenon generated by the non-volatile memory during the programming operation can be improved. Furthermore, when the stored data in the memory cell decays, the critical voltage distribution of the memory cell can be made more concentrated, effectively improving its data retention.

310~370, 360’, 370’, 460’, 470’: memory cells

510, 520: curve

600: Non-volatile memory

610: Memory cell array

620: Controller

630: Sense amplifier

700: memory cell string

A, B, C, D, E, F, G, PV: programmed verification voltage

CH: Columnar channel structure

CL: Channel layer

CTL: Charge Trapping Layer

D1, D2: Direction

DC: Dielectric Core

DV: offset voltage

F’, G’, PVL: Programming verification voltage after adjustment

ID0: programmed verification current

ID1: Programming verification current after adjustment

S110, S120, S210~S252: Steps

SC1, SC2: reference current

VPASSR: Pass voltage

WL1~WLm, WLn+1, WLn: character line

FIG1 is a flow chart showing a method for programming a non-volatile memory according to an embodiment of the present invention.

FIG2 is a flow chart showing a method for programming a non-volatile memory according to another embodiment of the present invention.

FIG3 is a schematic diagram showing the programming action of the non-volatile memory of an embodiment of the present invention.

Figures 4A and 4B are schematic diagrams showing the distribution of memory cells in the volatile memory of the embodiment of the present invention after programming.

FIG5 is a schematic diagram showing the adjustment action of the non-volatile memory program verification voltage in an embodiment of the present invention.

FIG6 is a schematic diagram of a non-volatile memory according to an embodiment of the present invention.

FIG7 is a schematic diagram of a memory cell string in a non-volatile memory according to an embodiment of the present invention.

Please refer to FIG. 1, which shows a flow chart of a programming method for a non-volatile memory according to an embodiment of the present invention. In step S110, a read operation is performed on a plurality of memory cells of the Nth word line that have completed the programming operation, and a judgment result is generated by judging whether the equivalent critical voltage of the plurality of memory cells of the Nth word line is greater than a preset threshold. The plurality of memory cells of the Nth word line may have been programmed to correspond to different logical values. When a program or operation is performed on the N+1th word line, a read operation may be performed on the plurality of memory cells of the Nth word line, and the equivalent critical voltage of the plurality of memory cells of the Nth word line is obtained. Where N is a positive integer greater than 1.

In detail, the controller of the non-volatile memory can set a reference current corresponding to the above-mentioned preset threshold. In addition, the controller can read multiple memory cells on the Nth word line to obtain the read current. The sense amplifier of the non-volatile memory can generate a comparison result based on the comparison of the reference current and the read current. In this way, the controller can determine the state of the equivalent critical voltage on the Nth word line based on the comparison result.

Specifically, when the above comparison result indicates that the read current is less than the reference current, it means that the equivalent critical voltage of multiple memory cells on the Nth word line is greater than the preset threshold value. In other words, multiple memory cells on the Nth word line have an equivalent critical voltage for high (in a high critical voltage state). Conversely, when the above comparison result indicates that the read current is not less than the reference current, it means that the equivalent critical voltage of multiple memory cells on the Nth word line is not greater than the preset threshold value. In other words, multiple memory cells on the Nth word line have an equivalent critical voltage for low (in a low critical voltage state).

In step S120, when programming is performed on a plurality of memory cells of the N+1th word line, it is possible to determine whether to adjust an offset value of at least one selected programming verification voltage among a plurality of programming verification voltages according to the judgment result generated in step S110 [S252]. In detail, when programming is performed on a plurality of memory cells of the N+1th word line, a plurality of programming verification voltages corresponding to a plurality of logic values may be set. Furthermore, when the comparison result obtained in step S110 indicates that the equivalent critical voltage of the memory cell of the Nth word line is greater than the preset threshold, the controller of the non-volatile memory can set one or more of the programming verification voltages as the selected programming verification voltage, and at least one selected programming verification voltage corresponding to the N+1th word line is reduced by an offset value.

Then, the controller can perform programming and programming verification actions on the memory cells of the N+1th word line according to the adjusted programming verification voltage.

In contrast, if the comparison result obtained in step S110 indicates that the equivalent critical voltage of the memory cell of the Nth word line is not greater than the preset threshold, the controller of the non-volatile memory does not adjust all the set programming verification voltages, and performs programming and programming verification actions on the memory cell of the N+1th word line.

In this embodiment, the programming action of the non-volatile memory can reduce the programming verification voltage of the programming verification action of the memory cells of the current word line according to the critical voltage state of the memory cells of the previous word line. In this way, the phenomenon of insufficient driving current of the memory cells on the unselected word line can be avoided. In addition, the programming verification voltage set by the critical voltage state of the memory cells of the corresponding adjacent word line can also effectively improve its data retention and enhance the accuracy of the stored data.

Please refer to FIG. 2 below, which is a flow chart of a programming method for a non-volatile memory according to another embodiment of the present invention. In this embodiment, the non-volatile memory may be an anti-integrated flash memory. In step S210, a programming action for the N+1th word line WLn+1 is initiated. Please refer to FIG. 3 below, which is a schematic diagram of a programming action for a non-volatile memory according to an embodiment of the present invention. In the programming action for the N+1th word line WLn+1, a plurality of programming verification voltages A, B, C, D, E, F, and G corresponding to a plurality of logic values are set, wherein the programming verification voltages A<B<C<D<E<F<G. In step S220, a programming verification operation is first performed on some memory cells of the N+1th word line WLn+1, and it is determined whether the memory cells 310, 320, 330, 340 pass the programming verification voltages A, B, C, and D, respectively. If the memory cells 310, 320, 330, 340 pass the programming verification operation of the programming verification voltages A, B, C, and D, respectively, step S230 can be executed. In contrast, if the memory cells 310, 320, 330, 340 fail the programming verification voltages A, B, C, D, the programming actions and programming verification actions of the memory cells 310, 320, 330, 340 can be re-executed.

In step S230, a read operation can be performed on the memory cells of the Nth word line WLn to determine the equivalent critical voltage of the memory cells of the Nth word line WLn. Regarding the equivalent critical voltage of the memory cells of the Nth word line WLn, a read operation can be performed on all memory cells of the word line WLn to obtain a read current, and the read current can be compared with a preset reference current to determine whether the Nth word line WLn is in a high critical voltage state or a low critical voltage state.

In step S240, it is determined whether the equivalent critical voltage of the word line WLn is in a high critical voltage state. When the word line WLn is in a high critical voltage state, step S252 is executed. Conversely, when the word line WLn is in a low critical voltage state, step S251 is executed.

In step S251, the controller can maintain the values of the programming verification voltages E, F, and G unchanged. In step S252, the controller selects the programming verification voltages F and G as the selected programming verification voltages, and adjusts the programming verification voltages F and G by reducing the programming verification voltages F and G by an offset value DV to generate adjusted programming verification voltages F' and G' respectively. Then, the controller can perform programming and verification actions of memory cell 350 according to programming verification voltage E, perform programming and verification actions of memory cell 360' according to adjusted programming verification voltage F', and perform programming and verification actions of memory cell 370' according to adjusted programming verification voltage G'.

It is worth noting that, through the adjustment operation for the programming verification voltage, the voltage value of the critical voltage of the memory cell 360' is lower than the voltage value of the critical voltage of the memory cell 360 after the programming operation for the unadjusted programming verification voltage F.

Please note that due to the limitation of the size of the cache space in the non-volatile memory, in step S220, some memory cells in word line WLn+1 (e.g., memory cells 310, 320, 330, and 340) are first programmed to complete the verification action. In order to perform the reading action of the equivalent critical voltage of the memory cells of word line WLn, a cache space of a certain size is required. Therefore, by first completing the programming verification action of some memory cells in word line WLn+1 in step S220, a cache space of sufficient size can be released to provide the reading action of the equivalent critical voltage of the memory cells of word line WLn.

Therefore, in step S220, the number of partial memory cells in word line WLn+1 that complete the programming verification action first can be set to correspond to the size of the cache space in the non-volatile memory. Specifically, when the size of the cache space in the non-volatile memory is large enough, the controller in step S220 can execute step S230 after the programming verification action corresponding to programming verification voltage A is completed. Alternatively, in step S220, the controller can execute step S230 after the programming verification action corresponding to programming verification voltages A and B is completed, or after the programming verification action corresponding to programming verification voltages A, B, and C is completed. When the size of the cache space in the non-volatile memory is not large enough, in step S220, the controller may also execute step S230 only after the programming actions corresponding to the programming verification voltages A, B, C, D, and E are completed.

In addition, in step S252, the number of programming verification voltages selected for adjustment can be changed. The designer can select only the highest programming verification voltage G for adjustment, or can select programming verification voltages G and F for adjustment, or can select more programming verification voltages G, F, E (or more) for adjustment, without any restrictions. The designer can determine the number of programming verification voltage adjustments based on the distribution range of programming verification voltages A~G and the adjustable space.

The size of the offset voltage DV can be set according to the data attenuation caused by the charge attraction in the memory cell of the adjacent word line in the non-volatile memory. The above data attenuation can be obtained by testing the actual non-volatile memory.

Please note that when the memory cells of the Nth word line WLn are in a high critical voltage state, the memory cells of the word line WLn have a lower impact on the memory cells of the N+1th word line WLn+1. Under such conditions, the non-volatile memory controller in the embodiment of the present invention first lowers the programming verification voltage of the memory cells of the N+1th word line WLn+1 during the programming operation. When the memory cells in the remaining word lines experience data attenuation due to the influence of the memory cells in the adjacent word lines, they can overlap with the distribution range of the adjusted memory cells in the N+1th word line WLn+1, effectively improving the problem of data preservation.

Please refer to FIG. 4A and FIG. 4B below, which are schematic diagrams showing the distribution state of the memory cells of the volatile memory of the embodiment of the present invention after the programming action. It can be clearly seen from FIG. 4A that by respectively reducing the programming verification voltages F and G to F' and G', the distribution of the critical voltages of the memory cells 460' and 470' can be moved toward the low voltage direction, and the distance between the maximum critical voltage of the memory cell 470' and the pass voltage VPASSR can be increased. In other words, through the programming action of the present invention, the equivalent resistance value of the memory cell string formed by the memory cells in the word line WLn+1 can be reduced, and the overdriving action of the memory cells in the programming action can be improved.

In FIG. 4B , after data attenuation occurs, the critical voltage distribution range of the adjusted memory cells 460' and 470' can overlap with the critical voltage distribution range of the memory cells after attenuation occurs, and form a critical voltage distribution range of the memory cells 460 and 470 with relatively high cohesion. Effectively improve the data retention of non-volatile memory.

By the way, the vertical axes of the curves in Figure 3, Figure 4A, and Figure 4B are all the number of memory cells.

Please refer to FIG. 5 below, which is a schematic diagram of the adjustment action of the non-volatile memory execution programming verification voltage in an embodiment of the present invention. In FIG. 5, during the process of the memory cell executing the programming action, the current ID-voltage VG relationship curve can move according to the direction of, for example, curve 510 to curve 520.

When adjusting the programming verification voltage for the programming verification action of the memory cell, it may be necessary to adjust the word line voltage of the memory cell. In this case, it will take extra time because of the need to discharge and recharge the word line again.

Based on the above, according to the embodiment of the present invention, when the programming verification voltage PV needs to be adjusted to the adjusted programming verification voltage PVL (wherein the adjusted programming verification voltage PVL and the original programming verification voltage PV have an offset value DV), the controller can maintain the word line voltage of the memory cell at the programming verification voltage PV, and compare the current of the memory cell with the reference current SC1 to perform the programming verification action. At this time, the characteristic curve of the memory cell is curve 510, and the reference current SC1 can be set corresponding to the curve 510 and the programming verification voltage PV.

Under such conditions, the above-mentioned programming verification action can be equivalent to the programming verification action performed according to the adjusted programming verification voltage PVL and the reference current SC2. Among them, the reference current SC2 is determined according to the curve 520 and the programming verification voltage PV. That is to say, in this embodiment, without adjusting the word line voltage of the memory cell, the programming verification action of the adjusted programming verification voltage PVL can be effectively completed, and the working rate of the programming verification action can be improved.

Please refer to FIG. 6 below, which is a schematic diagram of a non-volatile memory of an embodiment of the present invention. The non-volatile memory 600 includes a memory cell array 610, a controller 620, and a sense amplifier 630. The memory cell array 610 may have a plurality of memory cell strings, each memory cell string coupled to a plurality of word lines. The memory cell string may be a NAND flash memory cell string. The controller 620 is coupled to the memory cell array 610. The controller 620 may be used to execute each step of the programmed action of the aforementioned embodiment. The sense amplifier 630 is coupled to the memory cell array 610 and can be used to perform data reading and programming verification operations of the memory cell array 610.

The controller 620 may be a processor with computing capabilities. Alternatively, the controller 620 may be a hardware circuit designed by a hardware description language (HDL) or any other digital circuit design method known to those skilled in the art, and implemented by a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or an application-specific integrated circuit (ASIC).

The sense amplifier 630 can be implemented using a sense amplifying circuit known to those skilled in the art without any particular limitation.

Please refer to FIG. 7 below, which is a schematic diagram of a memory cell string in a non-volatile memory according to an embodiment of the present invention. The memory cell string 700 includes a dielectric core DC, a channel layer CL, a charge capturing layer CTL, and word lines WL0~WLm formed by a plurality of metal layers. The channel layer CL is, for example, made of polysilicon material to surround the dielectric core DC, and the charge capturing layer CTL surrounds the channel layer CL. The dielectric core DC, the channel layer CL, and the charge capturing layer CTL extend along a direction D1 and form a columnar channel structure CH. The word lines WL0~WLm extend along a direction D2 and are respectively coupled to a plurality of portions of the columnar channel structure CH to form a plurality of memory cells. Memory cells in the same columnar channel structure CH can form a memory cell string.

In summary, when the non-volatile memory of the present invention performs the programming action of the current word line, it can obtain the equivalent critical voltage state of the memory cells of the previous word line by reading the memory cells of the previous word line, and adjust the programming verification voltage of part of the programming action of the current word line according to the equivalent critical voltage state of the memory cells of the previous word line. In this way, the over-drive state and data retention of the non-volatile memory can be improved, and the overall performance of the non-volatile memory can be enhanced.

S110, S120: Steps

Claims (18)

A programming method, applicable to a non-volatile memory, comprises: Performing a read operation on a plurality of first memory cells of an Nth word line, and determining whether an equivalent critical voltage of the first memory cells is greater than a preset threshold to generate a determination result, wherein N is a positive integer greater than 0; and When performing a programming operation on a plurality of second memory cells of an N+1th word line, determining whether to adjust an offset value of at least one selected programming verification voltage among a plurality of programming verification voltages according to the determination result. The programming method as described in claim 1, wherein the programming operation for the first part of the second memory cells of the N+1th word line is completed before the reading operation is performed on the first memory cells of the Nth word line. The programming method as described in claim 1, wherein a reading operation is performed on the first memory cells of the Nth word line, and the step of determining whether the equivalent critical voltage of the first memory cells is greater than the preset threshold to generate the determination result includes: Setting a reference current corresponding to the preset threshold; Reading the first memory cells of the Nth word line to obtain a read current; and Comparing the read current and the reference current to obtain the comparison result. A programming method as described in claim 3, wherein when the read current is less than the reference current, it indicates that the equivalent critical voltage of the first memory cells is greater than the preset threshold; when the read current is not less than the reference current, it indicates that the equivalent critical voltage of the first memory cells is not greater than the preset threshold. The programming method as described in claim 1, wherein the step of determining whether to adjust the offset value of at least one selected programming verification voltage among the programming verification voltages according to the judgment result includes: When the equivalent critical voltage of the first memory cells is greater than the preset threshold value, the offset value of at least one selected programming verification voltage among the programming verification voltages is reduced. The programming method as described in claim 5, wherein the step of determining whether to adjust the offset value of at least one selected programming verification voltage among the programming verification voltages according to the judgment result further includes: When the equivalent critical voltage of the first memory cells is not greater than the preset threshold value, maintaining the at least one selected programming verification voltage among the programming verification voltages unchanged. The programming method as described in claim 2 further includes: Performing a programming operation on a second portion of the second memory cells of the N+1th word line according to at least one adjusted programming verification voltage. A programming method as described in claim 7, wherein a critical voltage of the second portion of the second memory cells is greater than a critical voltage of the first portion of the second memory cells. A non-volatile memory comprises: a memory cell array having a plurality of memory cell strings, each of which is coupled to a plurality of word lines; and a controller coupled to the memory cell array, for: performing a read operation on a plurality of first memory cells of an Nth word line, and determining whether an equivalent critical voltage of the first memory cells is greater than a preset threshold value to generate a determination result, wherein N is a positive integer greater than 0; and when performing a programming operation on a plurality of second memory cells of an N+1th word line, determining whether to adjust an offset value of at least one selected programming verification voltage among a plurality of programming verification voltages according to the determination result. A non-volatile memory as described in claim 9, wherein the controller completes a first portion of programming operations on the second memory cells of the N+1th word line before performing a read operation on the first memory cells of the Nth word line. A non-volatile memory as described in claim 9, wherein the controller is further used to: set a reference current corresponding to the preset threshold; read the first memory cells of the Nth word line to obtain a read current; and compare the read current and the reference current through a sense amplifier to obtain the comparison result. A non-volatile memory as described in claim 11, wherein when the read current is less than the reference current, it indicates that the equivalent critical voltage of the first memory cells is greater than the preset threshold; when the read current is not less than the reference current, it indicates that the equivalent critical voltage of the first memory cells is not greater than the preset threshold. The non-volatile memory as described in claim 9, wherein the controller is further used to: When the equivalent critical voltage of the first memory cells is greater than the preset threshold value, reduce the offset value of at least one selected programming verification voltage among the programming verification voltages. A non-volatile memory as described in claim 13, wherein the controller is further used to: When the equivalent critical voltage of the first memory cells is not greater than the preset threshold, maintain at least one selected programming verification voltage among the programming verification voltages unchanged. A non-volatile memory as described in claim 10, wherein the controller is further used to: Perform programming actions on a second portion of the second memory cells of the N+1th word line based on at least one adjusted programmed verification voltage. A non-volatile memory as described in claim 15, wherein a critical voltage of the second portion of the second memory cells is greater than a critical voltage of the first portion of the second memory cells. A non-volatile memory as described in claim 9, wherein each of the memory cell strings is an inverted flash memory cell string. A non-volatile memory as described in claim 9, wherein each of the memory cell strings forms a columnar channel structure.

Images