TWI868782B - In memory searching device - Google Patents

Abstract

An in memory searching device includes a plurality of first memory cell strings, a controller and a sensing circuit. The first memory cell strings are commonly coupled to a first common bit line. Each of the first memory strings includes a plurality of first data storage layers. The first data storage layers respectively include a plurality of first memory cell pairs. The first memory cell pairs are respectively coupled to a plurality of first word line pairs. The controller selects at least one of the first data storage layers to be at least one selected data storage layers, and provides search data to at least one selected word line pair of the at least one selected data storage layers. The sensing circuit senses a current on the common bit line to generate a search result.

Description

In-memory search device

The present invention relates to an in-memory search device, and in particular to an in-memory search device capable of improving search efficiency.

With the advancement of electronic technology, the development of artificial intelligence is becoming more mature. As a result, the need to search for large amounts of data has arisen. Accordingly, in-memory search devices have been introduced. As the amount of data to be searched increases, how to apply in-memory search devices to perform data search actions on large amounts of data has become an important topic for technicians in this field.

The present invention provides a memory search device that can perform a hierarchical data search on the memory to improve the efficiency of the data search operation.

The memory search device of the present invention includes a plurality of first memory cell strings, a controller, and a sensing circuit. The first memory cell strings are commonly coupled to a first common bit line. Each first memory cell string includes a plurality of first data storage layers. The first data storage layers respectively include a plurality of first memory cell pairs, and the first memory cell pairs are respectively coupled to a plurality of first word line pairs. The controller is coupled to the first memory cell strings, selects one of the first data storage layers as at least one selected data storage layer, and provides search data to at least one selected word line pair corresponding to at least one selected data storage layer. The sensing circuit is coupled to the first common bit line, and senses the current on the first common bit line to generate a search result.

Based on the above, the in-memory search device of the present invention can divide the memory into multiple data storage layers. When performing a data search action, the data search action can be performed on one or more data storage layers, which can speed up the efficiency of data search.

100, 500: Search device in memory

110, 120, 411~41(N), 511~5AN: memory cell string

130: Controller

140:Sensor

501: Sensor and encoder

BL, BL1~BLA: common bit line

Is1, IA, IB: current

M1~MZ: memory cells

MC1, MC2: memory cells

SD: Search data

SL1~SLA, SLB, SL11~SLN1, SLA1~SLAN, 610: Select the data storage layer

SSL1, SSL2, GSL, CSL: Select signal

SW1, SW2, SW(N): switch selection

VA, VB, Vmax, Vmin: Search voltage

Vg1, Vg2: bias voltage

VH1~VH4: voltage

Vpass: pass voltage

VT_A, VT_B: voltage curve

VT1, VT4: voltage distribution

WL11~WL2(Z), WL1_1~WL1_512, WL2_1~WL2_512, WL3_1~WL3_512, WL4_1~WL4_512 , WL89_1~WL89_512, WL90_1~WL90_512, WL89_1~WL89_512, WL90_1~WL90_512: character line

X, Y, Z: axial direction

FIG1 is a schematic diagram of an in-memory search device according to an embodiment of the present invention.

FIG2 is a schematic diagram showing another implementation of the in-memory search device of the embodiment of FIG1 of the present invention.

FIG3 is a schematic diagram showing another implementation of the in-memory search device of the embodiment of FIG1 of the present invention.

FIG. 4A and FIG. 4B are schematic diagrams showing the data search action of the in-memory search device of an embodiment of the present invention.

Figures 5A to 5C are schematic diagrams showing another embodiment of the in-memory search device and the implementation of the data search action of the present invention.

Figures 6A to 6D are schematic diagrams showing multiple execution modes of a data search action for selecting a data storage layer in an in-memory search device according to an embodiment of the present invention.

Please refer to FIG. 1 , which shows a schematic diagram of an in-memory search device according to an embodiment of the present invention. The in-memory search device 100 includes a plurality of memory cell strings 110, 120, a controller 130, and a sensor 140. The memory cell strings 110, 120 are coupled to a common bit line BL. The memory cell string 110 is coupled to the common bit line BL via a selection switch SW1, and the memory cell string 120 is coupled to the common bit line BL via a selection switch SW2. The selection switches SW1 and SW2 are respectively controlled by selection signals SSL1 and SSL2 to be turned on or off. The memory cell strings 110 and 120 may include multiple memory cells. Taking the memory cell string 110 as an example, the memory cell string 110 includes multiple memory cells M1 to MZ connected in series. The memory cells M1 to MZ may be inverse-type flash memory cells.

Each of the memory cell strings 110 and 120 has a plurality of memory cells coupled in series. The plurality of memory cells on the memory cell string 110 are respectively coupled to a plurality of word lines WL11~WL1(Z). The plurality of memory cells on the memory cell string 120 are respectively coupled to a plurality of word lines WL21~WL2(Z). In the present embodiment, the plurality of memory cells on each of the memory cell strings 110 and 120 can be grouped in pairs. The two memory cells in a single memory cell string 110 and 120 can form a data storage layer. Taking the memory cell string 110 as an example, memory cells M1 and M2 can form a data storage layer; memory cells M3 and M4 can form another data storage layer; ...; memory cells MZ-1 and MZ can form the last data storage layer in the diagram.

In other embodiments of the present invention, two non-adjacent flash memory cells can also be used in a single memory cell string to form a data storage layer. The method shown in FIG. 1 of this embodiment is only an example for illustration and is not intended to limit the scope of the present invention.

On the other hand, the controller 130 is coupled to the memory cell strings 110 and 120. When performing a data search action, the controller 130 can select at least one of the data storage layers in the memory cell strings 110 and 120 as one or more selected data storage layers. For example, in FIG1 , when performing a data search action, the controller 130 can select the data storage layer formed by the memory cells M1 and M2 in the memory cell string 110 as the selected data storage layer SL1. In addition, the controller 130 selects the second memory cell in the memory cell string 120 corresponding to the selected data storage layer SL1 as the selected data storage layer SL2.

In addition, the controller 130 may provide search data SD to a selected word line pair (including word lines WL11 and WL12) on the selected data storage layer SL1 and a selected word line pair (including word lines WL21 and WL22) on the selected data storage layer SL2, so as to perform a data search operation for the search data SD on the selected data storage layers SL1 and SL2. When the search data SD is digital data, the controller 130 may provide a plurality of bits of the search data SD to the word lines WL11 and WL12 on the selected data storage layer SL1 and the word lines WL21 and WL22 on the selected data storage layer SL2, respectively. When the search data SD is analog data, the controller 130 can provide multiple analog component voltages of the search data SD to the word lines WL11, WL12, WL21, and WL22 respectively.

The controller 130 of the embodiment of the present invention can be constructed by using a digital circuit. Or it can be implemented by using a memory controller known to those skilled in the art, without any specific limitation.

In the above data search action, the memory cells in the selected data storage layers SL1 and SL2 can be compared with the search data SD received on the word lines WL11, WL12, WL21 and WL22 according to the storage data they have, and the search results are generated. In this embodiment, the memory cells in the selected data storage layers SL1 and SL2 can generate a current on the common bit line BL according to the comparison action between the storage data they have and the search data SD. In this embodiment, the sensor 140 coupled to the common bit line BL can generate a search result by sensing the current on the common bit line BL. It is worth mentioning that in this embodiment, the data similarity represented by the search result is positively correlated with the current on the common bit line BL.

Please refer to FIG. 2 below, which is a schematic diagram of another embodiment of the in-memory search device of the embodiment of FIG. 1 of the present invention. In FIG. 2, two data storage layers in the memory cell string 110 are selected as selected data storage layers SL1 and SL3. Correspondingly, two data storage layers in the memory cell string 120 are selected as selected data storage layers SL2 and SL4. When performing a data search operation, the search data can be synchronously provided to the two selected word line pairs (including word lines WL11, WL12, WL13, WL14) corresponding to the selected data storage layers SL1 and SL3 and the two selected word line pairs (including word lines WL21, WL22, WL23, WL24) corresponding to the selected data storage layers SL2 and SL4. In this way, compared to the implementation method of Figure 1, data search operations of relatively large size data can be performed, and the bandwidth of the data search operation is effectively improved.

It is worth mentioning that in this embodiment, the selected data storage layers SL1 and SL3 can be adjacent data storage layers. In other embodiments of the present invention, the selected data storage layers can also be two data storage layers that are not adjacent in position. The embodiment of Figure 2 is only an example for illustration and is not intended to limit the scope of implementation of the present invention.

Please refer to FIG. 3 below, which is a schematic diagram of another embodiment of the memory search device of the embodiment of FIG. 1 of the present invention. In FIG. 3, all data storage layers in the memory cell string 110 can be selected at the same time as the selected data storage layers SL1~SLA. All data storage layers in the corresponding memory cell string 120 can be selected at the same time as the selected data storage layers SL2~SLB.

When performing a data search operation, the search data can be synchronously provided to the selected word line pairs (including word lines WL11~WL1(Z)) corresponding to the selected data storage layers SL1~SLA and the selected word line pairs (including word lines WL21~WL2(Z)) corresponding to the selected data storage layers SL2~SLB. In this way, compared with the implementation methods of Figures 1 and 2, data search operations of larger size data can be performed, effectively improving the bandwidth of the data search operation.

Please refer to FIG. 4A and FIG. 4B below, which are schematic diagrams of the data search action of the in-memory search device of the embodiment of the present invention. In FIG. 4A and FIG. 4B, the in-memory search device 400 includes a plurality of memory cell strings 411~41(N). The memory cell strings 411~41(N) are respectively coupled to the common bit line BL through the selection switches SW1~SW(N). The selection switches SW1~SW(N) are respectively controlled by the selection signals SSL1~SSLN. When performing the data search action, the selection switches SW1~SW(N) can be turned on simultaneously according to the selection signals SSL1~SSLN.

In this embodiment, as shown in FIG. 4A , in the first interval of the data search operation, a corresponding data storage layer in the memory cell strings 411 to 41 (N) is simultaneously set as the selected data storage layer SL11 to SLN1. The controller can also provide multiple components of the search data to the selected word line pair (including word lines WL1_1 to WL1_512 and word lines WL2_1 to WL2_512) on the selected data storage layer SL11 to SLN1. In this way, the in-memory search device 400 can complete the first layer of data search operation.

Incidentally, during the data search operation, the memory search device 400 can provide a pass voltage Vpass to multiple word lines of the unselected data storage layer. In addition, each memory cell string 411~41(N) has multiple switches controlled by the selection signals GSL and CSL.

Next, in FIG. 4B , in the second interval of the data search operation, another corresponding data storage layer in the memory cell string 411~41(N) is simultaneously set as the selected data storage layer SL12~SLN2. The controller can also provide multiple components of the search data to the selected word line pair (including word lines WL3_1~WL3_512 and word lines WL4_1~WL4_512) on the selected data storage layer SL12~SLN2. In this way, the in-memory search device 400 can complete the second layer data search operation.

By analogy with the description of FIG. 4A and FIG. 4B , the in-memory search device 400 can select each data storage layer in the memory cell string 411~41(N) one by one as the selected data storage layer according to the time sequence, and perform the data search action accordingly.

It is worth mentioning that in other embodiments of the present invention, in the same time period during the data search action, corresponding to each memory cell string, multiple data storage layers can also be selected as the selected data storage layer, and the data search action can be performed synchronously. In this way, the efficiency of the data search action can be effectively improved.

Please refer to FIG. 5A to FIG. 5C below, which are schematic diagrams showing an in-memory search device and an implementation method of a data search action according to another embodiment of the present invention. In FIG. 5A, the in-memory search device 500 includes a plurality of memory cell strings 511~5AN and a sensor and encoder 501. The memory cell strings 511~51N are commonly coupled to a common bit line BL1 through the selection switches they have; the memory cell strings 521~52N are commonly coupled to a common bit line BL2 through the selection switches they have; ...; the memory cell strings 5A1~5AN are commonly coupled to a common bit line BLA through the selection switches they have. In this embodiment, the memory cell strings 511~5AN can be arranged in a cube structure. In the memory search device 500, each common bit line BL1~BLA extends along the Y axis, each word line extends along the X axis, and multiple memory cells in each memory cell string 511~5AN are coupled in series along the Z axis. In addition, each memory cell string 511~5AN has multiple switches controlled by selection signals GSL and CSL.

The sensor and encoder 501 is coupled to the common bit lines BL1~BLA. The sensor in the sensor and encoder 501 is used to sense the current on the common bit lines BL1~BLA to generate a search result. The encoder in the sensor and encoder 501 is used to encode the search result to generate an encoded search result.

Incidentally, the sensor in the sensor and encoder 501 may be a sense amplifier, and may be implemented using a sense amplifier circuit known to a person skilled in the art. The encoder in the sensor and encoder 501 may be a digital circuit, and may be disposed in a page buffer.

When the in-memory search device 500 performs a data search operation, in a single time period, the in-memory search device 500 can set a data storage layer corresponding to a position in each memory cell string 511~5AN as a selected data storage layer. In this embodiment, the in-memory search device 500 can set the selected data storage layers SL11~SL1N for the memory cell strings 511~51N, respectively; set the selected data storage layers SL21~SL2N for the memory cell strings 521~52N, respectively; ...; and set the selected data storage layers SLA1~SLAN for the memory cell strings 5A1~5AN, respectively.

In this embodiment, based on the mutual correspondence in position, the selected data storage layers SL11~SL1N are respectively coupled to the selected word line pairs corresponding to the selected data storage layers SL21~SL2N, and the selected data storage layers SL21~SL2N are also respectively coupled to the selected word line pairs corresponding to the selected data storage layers SLA1~SLAN.

On the other hand, in the data search action, the search data SD can be split into multiple parts and provided to multiple selected word line pairs coupled to the selected data storage layers SL11~SLAN. The multiple selected word line pairs include word lines WL89_1~WL89_512 and word lines WL90_1~WL90_512. Among them, word lines WL89_1~WL89_512 form multiple word line pairs with word lines WL90_1~WL90_512 respectively.

In addition, the word lines of the unselected data storage layer receive the pass voltage Vpass.

In the data search action of FIG. 5A , the number of selected data storage layers of each memory cell string 511 to 5AN is 1 (n=1). Furthermore, in executing the search action, the in-memory search device 500 can sequentially set a data storage layer of each memory cell string 511 to 5AN in accordance with the time sequence in different time intervals through the controller to obtain the selected data storage layer, and then transmit the search data SD to the selected word line pairs of the selected data storage layer to execute the data search action.

In the implementation of FIG. 5B , the in-memory search device 500 can set the number of selected data storage layers of each memory cell string 511~5AN to 2 (n=2) in the same time period of the data search action. And by splitting the search data SD into multiple components and providing them to multiple selected word line pairs corresponding to multiple selected data storage layers, the data search action is performed. In this embodiment, the selected word line pairs include word lines WL1_1~WL4_1, WL1_2~WL4_2, ..., WL1_512~WL4_512.

In executing the search operation, the in-memory search device 500 can use the controller to sequentially set the two data storage layers of each memory cell string 511~5AN in different time periods according to the time sequence to obtain two selected data storage layers respectively, and then transmit the search data SD to the multiple selected word line pairs of the selected data storage layer to execute the data search operation.

In the implementation of FIG. 5C , the in-memory search device 500 can simultaneously set all data storage layers of each memory cell string 511 to 5AN as selected data storage layers during the data search operation. The number of selected data storage layers n=Z/2, where Z is the number of memory cells in each memory cell string 511 to 5AN. In addition, the search data SD is split into multiple components and provided to multiple selected word line pairs corresponding to multiple selected data storage layers to perform the data search operation. In this way, the data search operation for all stored data of the entire in-memory search device 500 can be completed through a one-time search operation.

According to the above description, it can be known that the in-memory search device 500 of the present invention can perform data search actions by setting the number n of selected data storage layers according to the needs of the clock, which can effectively improve the efficiency of the data search action.

Please refer to FIG. 6A to FIG. 6D below, which are schematic diagrams showing multiple execution modes of the data search action of the selected data storage layer in the memory search device of the embodiment of the present invention. In FIG. 6A, the selected data storage layer 610 of the embodiment of the present invention includes memory cells MC1 and MC2. The memory cells MC1 and MC2 can be single-level cells (SLC), multiple-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), or storage cells storing analog data. The word lines of memory cells MC1 and MC2 can respectively receive bias voltages Vg1 and Vg2 generated according to the search data, and generate a current Is1 reflecting the search result on the common bit line BL1 according to the search result.

In FIG6B , the selected data storage layer 610 may have storage data DAT. The storage data DAT includes a first bit D1 and a second bit D2. The storage data DAT may be encoded according to the voltage distributions VT1 to VT4 of the critical voltages Vth1 and Vth2 of the memory cells MC1 and MC2, as shown in the following table:

When performing a data search operation, the voltage received by the gates of the memory cells MC1 and MC2 through the corresponding word lines can be one of the voltages VH1 to VH4. The voltage received by the memory cells MC1 and MC2 is generated according to the corresponding search data. Taking two-bit search data as an example, the corresponding relationship between the search data and the voltages VH1 to VH4 is shown in Table 2:

When performing a data search, memory cells MC1 and MC2 can generate a current Is1 on the bit line BL1 according to the voltage received by the gate and the voltage difference between the stored data.

Next, please refer to Figure 6C, taking the above voltage distributions VT1~VT4 as 0V to 1V, 1.5V to 2.5V, 3V to 4V, 4.5V to 5.5V, and voltages VH1~VH4 as 5.5V, 7V, 8.5V, and 10V, as an example. The peak values of the voltage distributions VT1~VT4 correspond to voltages of 0.5V, 2V, 3.5V, and 5V, respectively.

When performing a search operation, when the search data is [0 0], the bias voltages Vg1 and Vg2 received by the gates of memory cells MC1 and MC2 are respectively equal to VH1 and VH4. If the storage data of memory cells MC1 and MC2 is [0 0] at this time, the critical voltage Vth1 of memory cell MC1 is in voltage distribution VT1, and the critical voltage Vth2 of memory cell MC2 is in voltage distribution VT4. At this time, on memory cell MC1, the difference between the bias voltage Vg1 and the critical voltage Vth1 can be 5.5V-1V=4.5V. Calculated with each 1.5V as a level L, the difference between the bias voltage Vg1 and the critical voltage Vth1 on the memory cell MC1 can be 3L. On the memory cell MC2, the difference between the bias voltage Vg2 and the critical voltage Vth2 can be 10V-5.5V=4.5V. The difference between the bias voltage Vg2 and the critical voltage Vth2 on the memory cell MC2 can be 3L.

That is to say, under this condition, when the search data matches the storage data, the memory cells MC1 and MC2 can generate a current Is1 corresponding to 3L.

When performing a search operation, when the search data is [0 0], the bias voltages Vg1 and Vg2 received by the gates of memory cells MC1 and MC2 are respectively equal to VH1 and VH4. If the storage data of memory cells MC1 and MC2 is [0 1] at this time, the critical voltage Vth1 of memory cell MC1 is in voltage distribution VT2, and the critical voltage Vth2 of memory cell MC2 is in voltage distribution VT3. The difference between the bias voltage Vg1 (=VH1) and the critical voltage Vth1 (=VT2) of memory cell MC1 can be 2L. The difference between the bias voltage Vg2 (=VH4) and the critical voltage Vth2 (=VT3) of the memory cell MC2 can be 4L.

Since memory cells MC1 and MC2 are connected in series, selecting data storage layer 610 can generate a current Is1 corresponding to 2L.

When performing a search operation, when the search data is [0 0], the bias voltages Vg1 and Vg2 received by the gates of memory cells MC1 and MC2 are respectively equal to VH1 and VH4. If the storage data of memory cells MC1 and MC2 is [1 0] at this time, the critical voltage Vth1 of memory cell MC1 is in voltage distribution VT3, and the critical voltage Vth2 of memory cell MC2 is in voltage distribution VT2. The difference between the bias voltage Vg1 (=VH1) and the critical voltage Vth1 (=VT3) of memory cell MC1 can be 1L. The difference between the bias voltage Vg2 (=VH4) and the critical voltage Vth2 (=VT2) of the memory cell MC2 can be 5L. Since the memory cells MC1 and MC2 are connected in series, the selected data storage layer 610 can generate a current Is1 corresponding to 1L.

When performing a search operation, when the search data is [0 0], the bias voltages Vg1 and Vg2 received by the gates of memory cells MC1 and MC2 are respectively equal to VH1 and VH4. If the storage data of memory cells MC1 and MC2 is [1 1] at this time, the critical voltage Vth1 of memory cell MC1 is in voltage distribution VT4, and the critical voltage Vth2 of memory cell MC2 is in voltage distribution VT1. The difference between the bias voltage Vg1 (=VH1) and the critical voltage Vth1 (=VT4) of memory cell MC1 can be 0L. The difference between the bias voltage Vg2 (=VH4) and the critical voltage Vth2 (=VT1) of the memory cell MC2 can be 6L. Since the memory cells MC1 and MC2 are connected in series, selecting the data storage layer 610 can generate a current Is1 corresponding to 0L.

From the above description, it is not difficult to know that the size of the current Is1 generated by the data storage layer 610 is positively correlated with the similarity between the search data and the storage data.

It is worth mentioning that, as long as the number of voltage distributions and the number of bias voltages received by memory cells MC1 and MC2 are appropriately adjusted, the data storage layer 610 selected in the embodiment of the present invention can also be used to store storage data of various different levels and perform search actions for search data of corresponding levels.

In FIG. 6D , the memory cells MC1 and MC2 in the data storage layer 610 are selected and can also be used to record analog storage data. A data search operation is performed for the analog search data. The critical voltage of the memory cell MC1 can be the voltage curve VT_A, and the critical voltage of the memory cell MC2 can be the voltage curve VT_B. The memory cells MC1 and MC2 can be independently programmed so that the critical voltages correspond to the voltage curves VT_A and VT_B, respectively.

In addition, currents IA and IB represent the channel currents of memory cells MC1 and MC2, respectively.

In this embodiment, the search data may be search voltages VA and VB, wherein the search voltages VA and VB have a relationship: VB=Vmax+Vmin-VA. Vmax and Vmin are respectively the maximum analog search voltage and the minimum analog search voltage in the search action. In this embodiment, the maximum analog search voltage Vmax and the minimum analog search voltage Vmin are both constants, such as 9V and 0V respectively.

When the search voltage VA is equal to 0.7V and the search voltage VB is equal to 8.3V, the memory cell MC1 does not provide current but the memory cell MC2 can provide current. When the search voltage VA is equal to 4.05V and the search voltage VB is equal to 4.95V, neither the memory cell MC1 nor the memory cell MC2 provides current. When the search voltage VA is equal to 8.52V and the search voltage VB is equal to 0.48V, the memory cell MC1 provides current but the memory cell MC2 does not provide current.

In this way, the magnitude of the current Is1 generated by the memory cells MC1 and MC2 in the selected data storage layer 610 can be used as a basis for the similarity between the stored data and the search data in the generated search results. Similarly, the magnitude of the current Is1 is positively correlated with the similarity between the stored data and the search data in the search results.

Incidentally, in other embodiments of the present invention, the voltage curves of the critical voltage of the memory cell MC1 and the critical voltage of the memory cell MC2 can also be interchanged. That is, the critical voltage of the memory cell MC1 can have a voltage curve VT_B, and the critical voltage of the memory cell MC2 can have a voltage curve VT_A.

In summary, the present invention enables the in-memory search device to set one or more data storage layers in the memory cell string as one or more selected data storage layers.

And provide multiple parts of the search data to the selected character line pairs of one or more selected data storage layers at the same time, and perform data search actions on one or more selected data storage layers synchronously. In this way, the rate of data search actions in the memory can be effectively increased, improving the performance of data search actions.

100: Search device in memory

110, 120: memory cell string

130: Controller

140:Sensor

BL: Common bit line

M1~MZ: memory cells

SD: Search data

SL1, SL2: Select the data storage layer

SSL1, SSL2: Select signal

SW1, SW2: switch selection

WL11~WL2(Z): character line

Claims (14)

A memory search device includes: a plurality of first memory cell strings, which are commonly coupled to a first common bit line, each of which includes a plurality of first data storage layers, each of which includes a plurality of first memory cell pairs, each of which is coupled to a plurality of first word line pairs; a controller, which is coupled to the first memory cell strings, selects at least one of the first data storage layers as at least one selected data storage layer, and provides a search data to at least one selected data storage layer corresponding to the at least one selected data storage layer. a word line pair in the first common bit line; a sensing circuit coupled to the first common bit line to sense the current on the first common bit line to generate a search result; and a plurality of second memory cell strings commonly coupled to a second common bit line, each of the second memory cell strings comprising a plurality of second data storage layers, the second data storage layers respectively corresponding to the first data storage layers, the second data storage layers respectively comprising a plurality of second memory cell pairs, the second memory cell pairs and the corresponding second memory cell pairs respectively coupled to the same first word line pairs. The in-memory search device as described in claim 1, wherein when the number of the at least one selected data storage layer is N, the controller synchronously selects N of the first data storage layers as the at least one selected data storage layer, wherein N is a positive integer. The in-memory search device as described in claim 2, wherein the controller selects N of the first data storage layers in a time sequence as the at least one selected data storage layer. An in-memory search device as described in claim 1, wherein the controller provides a pass voltage to multiple unselected word lines of multiple unselected data storage layers. The in-memory search device as described in claim 1, wherein the at least one selected data storage layer includes each selected first data storage layer and each corresponding second data storage layer. The in-memory search device as described in claim 1, wherein when the search data is digital data, the controller provides multiple bits of the search data to at least one selected word line pair corresponding to the at least one selected data storage layer. The in-memory search device as described in claim 1, wherein when the search data is analog data, the controller provides multiple analog component voltages of the search data to at least one selected word line pair corresponding to the at least one selected data storage layer. An in-memory search device as described in claim 1, wherein the data similarity of the search result is positively correlated with the current on the first common bit line. The in-memory search device as described in claim 1, wherein the critical voltage of each memory cell in each first memory cell pair is programmed in a first voltage range according to the corresponding storage data, and the controller sets the search data in a second voltage range, and the first voltage range does not overlap with the second voltage range. An in-memory search device as described in claim 9, wherein the stored data is digital data or analog data. An in-memory search device as described in claim 1, wherein the two memory cells in each first memory cell pair are arranged adjacently or non-adjacently. The in-memory search device as described in claim 1 further includes: An encoder coupled to the sensing circuit to encode the search result to generate an encoded search result. An in-memory search device as described in claim 12, wherein the encoded search result is multi-bit digital data or analog voltage. The in-memory search device as described in claim 1, wherein when the number of the at least one selected data storage layer is N, the selected data storage layers are arranged adjacent to each other or not adjacent to each other.

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